Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure comprises: a substrate; a lower electrode layer located on the surface of the substrate; a magnetic tunnel junction located on the surface of the lower electrode layer; an upper electrode layer located on the surface of the magnetic tunnel junction; a flip enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer; a piezoelectric layer for controlling the magnetic moment direction of the flip enhancement layer, when the flip enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is located between the flip enhancement layer and the upper electrode layer, when the flip enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is located between the flip enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction. The piezoelectric layer can reduce the write power consumption of the magnetic random access memory while improving the reliability and stability of the magnetic random access memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] MRAM (Magnetic Random Access Memory) is a non-volatile magnetic random access memory. It has the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM), and its power consumption is much lower than DRAM. Compared with flash memory (Flash), its performance will not degrade with the increase of usage time. Due to the above characteristics of MRAM, it is considered to be able to replace SRAM, DRAM, EEPROM and Flash.

[0003] Unlike traditional random access memory chip manufacturing technology, the data in MRAM is not stored in the form of charge or current, but in a magnetic state, and is sensed by measuring resistance without interfering with the magnetic state. MRAM uses a magnetic tunnel junction (MTJ) structure to store data. Generally speaking, an MRAM unit consists of a transistor (1T) and a magnetic tunnel junction (MTJ) to form a storage unit. The magnetic tunnel junction (MTJ) structure includes at least two magnetic layers and a tunneling layer for isolating the two magnetic layers. The current flows vertically from one magnetic layer through the tunneling layer or "through" another magnetic layer. One of the magnetic layers is a fixed magnetic layer, which fixes the electrode in a specific direction through a strong fixed field. The other magnetic layer is a freely rotatable magnetic layer that keeps the electrode on one side.

[0004] However, the reliability and stability of existing magnetic random access memories still need to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure to improve the performance and reliability of a magnetic random access memory.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a lower electrode layer located on the surface of the substrate; a magnetic tunnel junction located on the surface of the lower electrode layer; an upper electrode layer located on the surface of the magnetic tunnel junction; a flip enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer; a piezoelectric layer, wherein the piezoelectric layer is used to control the magnetic moment direction of the flip enhancement layer, when the flip enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is located between the flip enhancement layer and the upper electrode layer, when the flip enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is located between the flip enhancement layer and the lower electrode layer, and when the flip enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is located between the flip enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction.

[0007] Optionally, the material of the piezoelectric layer is a piezoelectric material.

[0008] Optionally, the material of the piezoelectric layer includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

[0009] Optionally, the thickness of the piezoelectric layer is greater than 0 nanometers, and the thickness of the piezoelectric layer is less than 10 nanometers.

[0010] Optionally, the magnetic moment direction of the inversion enhancement layer is perpendicular or parallel to the normal direction of the substrate surface.

[0011] Optionally, it further includes: a first insertion layer, wherein the first insertion layer is located between the flip enhancement layer and the magnetic tunnel junction.

[0012] Optionally, it further includes: a second insertion layer, wherein the second insertion layer is located between the inversion enhancement layer and the piezoelectric layer.

[0013] Optionally, when the inversion enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the semiconductor structure further includes: a seed layer located between the lower electrode layer and the magnetic tunnel junction.

[0014] Optionally, when the inversion enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the semiconductor structure further includes: a buffer layer located between the lower electrode layer and the piezoelectric layer.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a piezoelectric layer on the surface of the lower electrode layer; forming a flip enhancement layer on the surface of the piezoelectric layer, the piezoelectric layer is used to control the magnetic moment direction of the flip enhancement layer; forming a magnetic tunnel junction on the surface of the flip enhancement layer, when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; forming an upper electrode layer on the surface of the magnetic tunnel junction.

[0016] Optionally, the method further includes: forming a first insertion layer between the magnetic tunnel junction and the flip enhancement layer.

[0017] Optionally, the method further includes: forming a second insertion layer between the inversion enhancement layer and the piezoelectric layer.

[0018] Optionally, the method further includes: forming a buffer layer between the piezoelectric layer and the lower electrode layer.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a magnetic tunnel junction on the surface of the lower electrode layer; forming a flip enhancement layer on the surface of the magnetic tunnel junction; forming a piezoelectric layer on the surface of the flip enhancement layer, the piezoelectric layer is used to control the magnetic moment direction of the flip enhancement layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; forming an upper electrode layer on the surface of the piezoelectric layer.

[0020] Optionally, the method further includes: forming a first insertion layer between the flip enhancement layer and the magnetic tunnel junction.

[0021] Optionally, the method further includes: forming a second insertion layer between the piezoelectric layer and the inversion enhancement layer.

[0022] Optionally, the method further includes: forming a seed layer between the magnetic tunnel junction and the lower electrode layer.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] In the semiconductor structure provided by the technical solution of the present invention, when no data is written, that is, when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction. Since the semiconductor structure further includes a piezoelectric layer located between the flip enhancement layer and the upper electrode layer, or between the flip enhancement layer and the lower electrode layer, and used to control the magnetic moment direction of the flip enhancement layer, when writing data, the piezoelectric layer can generate stress through an external bias voltage, and the magnetic moment direction of the flip enhancement layer is flipped 90 degrees through the stress, that is, the magnetic moment direction of the flip enhancement layer is perpendicular to the magnetic moment direction of the magnetic tunnel junction, so that the flip enhancement layer can provide an additional bias magnetic field for the magnetic tunnel junction when writing data, so as to reduce the write power consumption; at the same time, when no data is written, due to the absence of an external bias voltage, the stress generated by the piezoelectric layer disappears, so that the magnetic moment direction of the flip enhancement layer is flipped 90 degrees again, that is, the magnetic moment direction of the flip enhancement layer returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction, and the flip enhancement layer does not generate a bias magnetic field that affects the magnetic moment direction of the free layer of the magnetic tunnel junction, so that when no data is written, the influence of the flip enhancement layer on the magnetic moment direction of the free layer of the magnetic tunnel junction can be reduced, thereby improving the reliability and stability of the magnetic random access memory. In summary, by means of the flip enhancement layer and the piezoelectric layer, the reliability and stability of the magnetic random access memory can be improved while reducing the write power consumption of the magnetic random access memory.

[0025] Furthermore, since there is a second insertion layer between the inversion enhancement layer and the piezoelectric layer, on the one hand, the inversion enhancement layer of magnetic material and the piezoelectric layer of non-magnetic material can be isolated by the second insertion layer, thereby reducing the mutual influence such as diffusion between the materials of the inversion enhancement layer and the materials of the piezoelectric layer; on the other hand, the second insertion layer can better enable the inversion enhancement layer to form a magnetic moment in a specific direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of a cross-sectional structure of a semiconductor structure;

[0027] Figures 2 to 4 is a structural schematic diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention;

[0028] Figures 5 to 7 is a schematic diagram of the working principle of the semiconductor structure according to an embodiment of the present invention;

[0029] Figures 8 to 10 is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention;

[0030] Figures 11 to 13 It is a schematic diagram of the working principle of a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the reliability and stability of existing magnetic random access memories still need to be improved.

[0032] The reasons why the performance and reliability of existing magnetic random access memories still need to be improved are described in detail below with reference to the accompanying drawings.

[0033] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0034] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0035] Please refer to Figure 1 The semiconductor structure includes: a substrate 100; a lower electrode layer 110 located on the surface of the substrate; a magnetic tunnel junction 120 located on the surface of the lower electrode layer 110, wherein the magnetic tunnel junction 120 includes a first magnetic film 121, an insulating film 122 located on the surface of the first magnetic film 121, and a second magnetic film 123 located on the surface of the insulating film 122, wherein the first magnetic film 121 is a reference layer, and the second magnetic film 123 is a free layer; a flip enhancement layer 130 located on the surface of the magnetic tunnel junction 120, wherein the flip enhancement layer 130 provides a bias magnetic field for the magnetic tunnel junction 120; and an upper electrode layer 140 located on the surface of the flip enhancement layer 130.

[0036] In the above method, due to the addition of the flip enhancement layer 130 whose magnetic moment direction is perpendicular to the magnetic moment direction of the second magnetic film 123, an additional bias magnetic field is provided for the magnetic tunnel junction 120, thereby reducing the power consumption required for flipping the magnetic moment direction of the second magnetic film 123 when writing data, that is, the write power consumption of the magnetic random access memory can be reduced.

[0037] However, since the magnetic moment direction of the flip enhancement layer 130 is always perpendicular to the magnetic moment direction of the second magnetic film 123, that is, regardless of whether data is written, the additional bias magnetic field provided by the flip enhancement layer 130 always exists. Therefore, when data is not written, the bias magnetic field will affect the magnetic moment direction of the second magnetic film 123. In particular, when the magnetic tunnel junction 130 is simultaneously affected by the ambient temperature (such as temperature increase) and the bias magnetic field, the magnetic moment direction of the second magnetic film 123 is prone to flip, resulting in poor reliability and stability of the magnetic random access memory.

[0038] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, which can reduce the write power consumption of the magnetic random access memory when writing data through a flip enhancement layer and a piezoelectric layer located between the flip enhancement layer and the upper electrode layer, or between the flip enhancement layer and the lower electrode layer. At the same time, when no data is written, the reliability and stability of the magnetic random access memory are improved.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 2 to 4 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0041] Please refer to Figure 2 , providing a substrate 200.

[0042] In this embodiment, the substrate 200 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0043] The material of the substrate 200 includes semiconductor material.

[0044] In this embodiment, the material of the substrate 200 includes silicon.

[0045] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0046] Subsequently, a lower electrode layer is formed on the surface of the substrate 200; a piezoelectric layer is formed on the surface of the lower electrode layer; a flip enhancement layer is formed on the surface of the piezoelectric layer; a magnetic tunnel junction is formed on the surface of the flip enhancement layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; an upper electrode layer is formed on the surface of the magnetic tunnel junction. For the specific process of forming the lower electrode layer, the piezoelectric layer, the flip enhancement layer, the magnetic tunnel junction and the upper electrode layer, please refer to Figure 3 to Figure 4 .

[0047] Please refer to Figure 3, a lower electrode material layer 210 is formed on the surface of the substrate 200; a piezoelectric material layer 220 is formed on the surface of the lower electrode material layer 210; a flip enhancement material layer 230 is formed on the surface of the piezoelectric material layer 220; a magnetic tunnel junction material layer 240 is formed on the surface of the flip enhancement material layer 230; an upper electrode material layer 250 is formed on the surface of the magnetic tunnel junction material layer 240; and a patterned layer 260 is formed on the surface of the upper electrode material layer 250.

[0048] The lower electrode material layer 210 provides materials for forming a lower electrode layer.

[0049] In this embodiment, the process of forming the lower electrode material layer 210 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0050] The piezoelectric material layer 220 provides material for forming a piezoelectric layer.

[0051] In this embodiment, the process of forming the piezoelectric material layer 220 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0052] The rollover enhancement material layer 230 provides materials for forming a rollover enhancement layer.

[0053] In this embodiment, the process of forming the rollover enhancement material layer 230 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0054] The magnetic tunnel junction material layer 240 provides materials for forming a magnetic tunnel junction.

[0055] In this embodiment, the magnetic tunnel junction material layer 240 includes: a first magnetic material layer 241 located on the surface of the flip enhancement material layer 230, a tunneling material layer 242 located on the surface of the first magnetic material layer, and a second magnetic material layer 243 located on the surface of the tunneling material layer.

[0056] In this embodiment, the process of forming the first magnetic material layer 241 , the tunneling material layer 242 and the second magnetic material layer 243 includes: a chemical vapor deposition process or an atomic layer deposition process.

[0057] In other embodiments, the method for forming the tunneling material layer includes: forming an initial tunneling material layer on the surface of the first magnetic material layer using a deposition process; and performing an oxidation process on the initial tunneling material layer to form a tunneling material layer.

[0058] The first magnetic material layer 241 provides material for forming a first magnetic film, the second magnetic material layer 243 provides material for forming a second magnetic film, and the tunneling material layer 242 provides material for forming a tunneling layer.

[0059] The upper electrode material layer 250 provides materials for forming an upper electrode layer.

[0060] In the present embodiment, the process of forming the upper electrode material layer 250 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0061] In this embodiment, before forming the piezoelectric material layer 220 , a buffer material layer 290 is formed on the surface of the lower electrode material layer 210 .

[0062] The buffer material layer 290 provides material for forming a buffer layer.

[0063] In this embodiment, before forming the inversion enhancing material layer 230 , a second insertion material layer 280 is formed on the surface of the piezoelectric material layer 220 .

[0064] The second insertion material layer 280 provides material for forming a second insertion layer.

[0065] In this embodiment, the process of forming the second insertion material layer 280 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0066] In this embodiment, before forming the magnetic tunnel junction material layer 240 , a first insertion material layer 270 is formed on the surface of the inversion enhanced material layer 230 .

[0067] The first insertion material layer 270 provides material for forming a first insertion layer.

[0068] In this embodiment, the process of forming the first insertion material layer 270 includes a spin coating process, an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0069] Please refer to Figure 4 , using the patterned layer 260 as a mask, the upper electrode material layer 250, the magnetic tunnel junction material layer 240, the flip enhancement material layer 230, the piezoelectric material layer 220 and the lower electrode material layer 210 are etched until the surface of the substrate 200 is exposed to form an upper electrode layer 251, a magnetic tunnel junction 300, a flip enhancement layer 231, a piezoelectric layer 221 and a lower electrode layer 211.

[0070] Specifically, in this embodiment, the lower electrode material layer 210 is etched to form a lower electrode layer 211 on the surface of the substrate 200; the piezoelectric material layer 220 is etched to form a piezoelectric layer 221 on the surface of the lower electrode layer 211; the inversion enhancement material layer 230 is etched to form a inversion enhancement layer 231 on the surface of the piezoelectric layer 221; the magnetic tunnel junction material layer 240 is etched to form a magnetic tunnel junction 300 on the surface of the inversion enhancement layer 231; and the upper electrode material layer 250 is etched to form an upper electrode layer 251 on the surface of the magnetic tunnel junction 300.

[0071] The piezoelectric layer 221 is used to control the magnetic moment direction of the inversion enhancement layer 231 .

[0072] When no external voltage is applied to the piezoelectric layer 221 , the magnetic moment direction of the inversion enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300 .

[0073] In this embodiment, the process of etching the upper electrode material layer 250 , the magnetic tunnel junction material layer 240 , the inversion enhancement material layer 230 , the piezoelectric material layer 220 and the lower electrode material layer 210 includes a reactive ion etching process or an ion beam etching process.

[0074] In this embodiment, the material of the lower electrode layer 211 includes tantalum, aluminum or copper.

[0075] In this embodiment, the material of the piezoelectric layer 221 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

[0076] In this embodiment, the thickness of the piezoelectric layer 221 is in a range of 1 nanometer to 2 nanometers. When the thickness of the piezoelectric layer 221 is in a range of 1 nanometer to 2 nanometers, the magnetic moment direction of the flip enhancement layer 231 can be better controlled.

[0077] In other embodiments, the thickness of the piezoelectric layer 221 is between 0 nanometers and 1 nanometer, or is greater than 2 nanometers and less than 10 nanometers.

[0078] In this embodiment, the material of the piezoelectric layer 221 is a piezoelectric material.

[0079] In this embodiment, the inversion enhancement layer 231 includes: more than one inversion enhancement film (not shown) overlapped along the substrate normal direction.

[0080] When the inversion enhancement layer 231 includes two or more inversion enhancement films, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) located between adjacent inversion enhancement films.

[0081] In this embodiment, the material of the inversion enhancement layer 231 includes one or more combinations of cobalt iron, cobalt iron boron or nickel iron.

[0082] In this embodiment, the magnetic moment direction of the inversion enhancement layer 231 is perpendicular or parallel to the normal direction of the surface of the substrate 200 .

[0083] In this embodiment, the magnetic tunnel junction 300 includes: a first magnetic film 301 located on the surface of the flip enhancement layer 231 ; a tunneling layer 302 located on the surface of the first magnetic film 301 ; and a second magnetic film 303 located on the surface of the tunneling layer 302 .

[0084] In this embodiment, the first magnetic film 301 is a free layer, and the second magnetic film 303 is a fixed layer.

[0085] The material of the first magnetic film 301 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0086] The material of the second magnetic film 303 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0087] The material of the tunneling layer 302 includes magnesium oxide.

[0088] The magnetic tunnel junction 300 may be a perpendicular anisotropic magnetic tunnel junction or an in-plane anisotropic magnetic tunnel junction.

[0089] In this embodiment, the material of the upper electrode layer 251 includes tantalum, aluminum or copper.

[0090] In this embodiment, the patterned layer 260 is used as a mask to etch the upper electrode material layer 250, the magnetic tunnel junction material layer 240, the flip enhancement material layer 230, the piezoelectric material layer 220 and the lower electrode material layer 210, and at the same time, the first insertion material layer 270, the second insertion material layer 280 and the buffer material layer 290 are etched to form a first insertion layer 271, a second insertion layer 281 and a buffer layer 291.

[0091] Specifically, in this embodiment, a first insertion layer 271 is formed between the magnetic tunnel junction 300 and the flip enhancement layer 231 , a second insertion layer 281 is formed between the flip enhancement layer 231 and the piezoelectric layer 221 , and a buffer layer 291 is formed between the piezoelectric layer 221 and the lower electrode layer 211 .

[0092] In this embodiment, the material of the first insertion layer 271 includes a non-magnetic metal material or a non-magnetic dielectric material, and the non-magnetic metal material includes ruthenium or tantalum.

[0093] In other embodiments, the first insertion layer is not formed.

[0094] In this embodiment, the material of the second insertion layer 281 includes a non-magnetic metal material, and the non-magnetic metal material includes ruthenium or tantalum.

[0095] In other embodiments, the second insertion layer is not formed.

[0096] In other embodiments, the buffer layer is not formed.

[0097] It should be noted that the patterned layer 260 is completely consumed and removed during the etching process of forming the upper electrode layer 251 , the magnetic tunnel junction 300 , the flip enhancement layer 231 , the piezoelectric layer 221 and the lower electrode layer 211 .

[0098] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, please continue to refer to Figure 4 , including: a substrate 200; a lower electrode layer 211 located on the surface of the substrate 200; a magnetic tunnel junction 300 located on the surface of the lower electrode layer 211; an upper electrode layer 251 located on the surface of the magnetic tunnel junction 300; a flip enhancement layer 231 located between the magnetic tunnel junction 300 and the lower electrode layer 211; a piezoelectric layer 221 located between the flip enhancement layer 231 and the lower electrode layer 211, wherein the piezoelectric layer 221 is used to control the magnetic moment direction of the flip enhancement layer 231, and when no external voltage is applied to the piezoelectric layer 221, the magnetic moment direction of the flip enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300.

[0099] In this embodiment, the substrate 200 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0100] The material of the substrate 200 includes semiconductor material.

[0101] In this embodiment, the material of the substrate 200 includes silicon.

[0102] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0103] In this embodiment, the material of the lower electrode layer 211 includes tantalum, aluminum or copper.

[0104] In this embodiment, the material of the piezoelectric layer 221 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

[0105] In this embodiment, the thickness of the piezoelectric layer 221 is in a range of 1 nanometer to 2 nanometers. When the thickness of the piezoelectric layer 221 is in a range of 1 nanometer to 2 nanometers, the magnetic moment direction of the flip enhancement layer 231 can be better controlled.

[0106] In other embodiments, the thickness of the piezoelectric layer 221 is between 0 nanometers and 1 nanometer, or is greater than 2 nanometers and less than 10 nanometers.

[0107] In this embodiment, the material of the piezoelectric layer 221 is a piezoelectric material.

[0108] In this embodiment, the inversion enhancement layer 231 includes: more than one inversion enhancement film (not shown) overlapped along the substrate normal direction.

[0109] When the inversion enhancement layer 231 includes two or more inversion enhancement films, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) located between adjacent inversion enhancement films.

[0110] In this embodiment, the material of the inversion enhancement layer 231 includes one or more combinations of cobalt iron, cobalt iron boron or nickel iron.

[0111] In this embodiment, the magnetic moment direction of the inversion enhancement layer 231 is perpendicular or parallel to the normal direction of the surface of the substrate 200 .

[0112] In this embodiment, the magnetic tunnel junction 300 includes: a first magnetic film 301 located on the surface of the flip enhancement layer 231 ; a tunneling layer 302 located on the surface of the first magnetic film 301 ; and a second magnetic film 303 located on the surface of the tunneling layer 302 .

[0113] In this embodiment, the first magnetic film 301 is a free layer, and the second magnetic film 303 is a fixed layer.

[0114] The material of the first magnetic film 301 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0115] The material of the second magnetic film 303 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0116] The material of the tunneling layer 302 includes magnesium oxide.

[0117] The magnetic tunnel junction 300 may be a perpendicular anisotropic magnetic tunnel junction or an in-plane anisotropic magnetic tunnel junction.

[0118] In this embodiment, the material of the upper electrode layer 251 includes tantalum, aluminum or copper.

[0119] In this embodiment, the semiconductor structure further includes: a first insertion layer 271 located between the magnetic tunnel junction 300 and the flip enhancement layer 231 .

[0120] Since the first insertion layer 271 is provided between the magnetic tunnel junction 300 and the flip enhancement layer 231 , the coupling between the flip enhancement layer 231 and the magnetic tunnel junction 300 can be reduced.

[0121] The material of the first insertion layer 271 includes a non-magnetic metal material or a non-magnetic dielectric material. The non-magnetic metal material includes ruthenium or tantalum.

[0122] In other embodiments, the semiconductor structure does not include a first insertion layer.

[0123] In this embodiment, the semiconductor structure further includes: a second insertion layer 281 located between the inversion enhancement layer 231 and the piezoelectric layer 221 .

[0124] Since there is a second insertion layer 281 between the flip enhancement layer 231 and the piezoelectric layer 221, on the one hand, the flip enhancement layer 231 of magnetic material can be isolated from the piezoelectric layer 221 of non-magnetic material through the second insertion layer 281, thereby reducing the mutual influence such as diffusion between the materials of the flip enhancement layer 231 and the piezoelectric layer 221. On the other hand, the second insertion layer 281 can better enable the flip enhancement layer 231 to form a magnetic moment in a specific direction.

[0125] The material of the second insertion layer 281 includes a non-magnetic metal material, and the non-magnetic metal material includes ruthenium or tantalum.

[0126] In other embodiments, the semiconductor structure does not include a second insertion layer.

[0127] In this embodiment, the semiconductor structure further includes: a buffer layer 291 located between the piezoelectric layer 221 and the lower electrode layer 211 .

[0128] In other embodiments, the semiconductor structure does not include a buffer layer.

[0129] Figures 5 to 7 It is a schematic diagram of the working principle of the semiconductor structure according to an embodiment of the present invention.

[0130] It should be noted that Figures 5 to 7The schematic diagram shows the flip enhancement layer 231 and the magnetic moment direction of the magnetic tunnel junction 300 when the magnetic tunnel junction 300 is a perpendicular anisotropic magnetic tunnel junction. When the magnetic tunnel junction 300 is an in-plane anisotropic magnetic tunnel junction, the working principle of the semiconductor structure is the same as the working principle when the magnetic tunnel junction 300 is a perpendicular anisotropic magnetic tunnel junction, and will not be repeated here.

[0131] Please refer to Figure 5 , Figure 5 The initial state of the semiconductor structure is schematically shown. When no data is written, that is, when no external bias voltage is applied to the piezoelectric layer 221 , the magnetic moment direction of the flip enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300 .

[0132] Specifically, at this time, the magnetic moment directions of the switching enhancement layer 231 are parallel to the magnetic moment directions of the first magnetic film 301 , the tunneling layer 302 , and the second magnetic film 303 .

[0133] Please refer to Figure 6 and Figure 7 , Figure 6 Schematically shows the state of the semiconductor structure during the data writing process. Figure 7 The schematic diagram shows the state of the semiconductor structure after the data is written. When writing data, an external bias voltage is applied to the upper electrode layer 251 and the piezoelectric layer 221. The external bias voltage can generate stress in the piezoelectric layer 221, and the magnetic moment direction of the flip enhancement layer 231 is flipped 90 degrees by the stress, that is, the magnetic moment direction of the flip enhancement layer 231 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 300, so that the flip enhancement layer 231 can provide an additional bias magnetic field for the magnetic tunnel junction 300 when writing data.

[0134] Specifically, on the one hand, a bias magnetic field is provided to the magnetic tunnel junction 300 through an external bias voltage, and on the other hand, an additional bias magnetic field is provided to the magnetic tunnel junction 300 through the flip enhancement layer 231 whose magnetic moment direction has been flipped 90 degrees, thereby causing the magnetic moment direction of the first magnetic film 301 serving as the free layer to flip 180 degrees to complete data writing.

[0135] After the data writing is completed, the semiconductor structure is again in a state where no external bias voltage is applied to the upper electrode layer 251 and the piezoelectric layer 221. At this time, the piezoelectric layer 221 no longer generates stress (the piezoelectric layer 221 returns to its original state). Therefore, the magnetic moment direction of the flip enhancement layer 231 returns to the magnetic moment direction of the flip enhancement layer 231 in the initial state of the semiconductor structure. At this time, the magnetic moment direction of the flip enhancement layer 231 is again parallel to the magnetic moment direction of the magnetic tunnel junction 300.

[0136] Since the semiconductor structure includes a piezoelectric layer 221 located between the flip enhancement layer 231 and the lower electrode layer 211, when writing data, the piezoelectric layer 221 can generate stress through an external bias voltage, and the magnetic moment direction of the flip enhancement layer 231 is flipped 90 degrees through the stress, that is, the magnetic moment direction of the flip enhancement layer 231 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 300, so that the flip enhancement layer 231 can provide an additional bias magnetic field for the magnetic tunnel junction 300 when writing data, so as to reduce the write power consumption; at the same time When no data is written, due to the absence of an external bias voltage, the stress generated by the piezoelectric layer 221 disappears, causing the magnetic moment direction of the flip enhancement layer 231 to flip 90 degrees again, that is, the magnetic moment direction of the flip enhancement layer 231 returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction 300, and the flip enhancement layer 231 does not generate a bias magnetic field that affects the magnetic moment direction of the first magnetic film 301. Thus, when no data is written, the influence of the flip enhancement layer 231 on the magnetic moment direction of the first magnetic film 301 can be reduced, thereby improving the reliability and stability of the magnetic random access memory. In summary, through the flip enhancement layer 231 and the piezoelectric layer 221, the reliability and stability of the magnetic random access memory can be improved while reducing the write power consumption of the magnetic random access memory.

[0137] It should be noted that, for ease of understanding, Figures 5 to 7 The magnetic moment directions of the flip enhancement layer 231 and the magnetic tunnel junction 300 are only schematically shown. The magnetic moment directions of the flip enhancement layer 231 and the magnetic tunnel junction 300 may also be different from those of the flip enhancement layer 231 and the magnetic tunnel junction 300. Figures 5 to 7 The magnetic moments in the .

[0138] Figures 8 to 10 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention.

[0139] Please refer to Figure 8 , providing a substrate 400.

[0140] In this embodiment, the substrate 400 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0141] The material of the substrate 400 includes semiconductor material.

[0142] In this embodiment, the material of the substrate 400 includes silicon.

[0143] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0144] Subsequently, a lower electrode layer is formed on the surface of the substrate 400; a magnetic tunnel junction is formed on the surface of the lower electrode layer; a flip enhancement layer is formed on the surface of the magnetic tunnel junction; a piezoelectric layer is formed on the surface of the flip enhancement layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; and an upper electrode layer is formed on the surface of the piezoelectric layer. For the specific process of forming the lower electrode layer, the piezoelectric layer, the flip enhancement layer, the magnetic tunnel junction and the upper electrode layer, please refer to Figures 9 and 10 .

[0145] Please refer to Fig. 9 , a lower electrode material layer 410 is formed on the surface of the substrate 400; a magnetic tunnel junction material layer 420 is formed on the surface of the lower electrode material layer 410; a flip enhancement material layer 430 is formed on the surface of the magnetic tunnel junction material layer 420; a piezoelectric material layer 440 is formed on the surface of the flip enhancement material layer 430; an upper electrode material layer 450 is formed on the surface of the piezoelectric material layer 440; and a patterned layer 460 is formed on the surface of the upper electrode material layer 450.

[0146] The lower electrode material layer 410 provides materials for forming a lower electrode layer.

[0147] In this embodiment, the process of forming the lower electrode material layer 410 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0148] The magnetic tunnel junction material layer 420 provides materials for forming a magnetic tunnel junction.

[0149] In this embodiment, the magnetic tunnel junction material layer 420 includes: a first magnetic material layer 421 located on the surface of the lower electrode material layer 410 , a tunneling material layer 422 located on the surface of the first magnetic material layer 421 , and a second magnetic material layer 423 located on the surface of the tunneling material layer 422 .

[0150] In this embodiment, the process of forming the first magnetic material layer 421 , the tunneling material layer 422 and the second magnetic material layer 423 includes: a chemical vapor deposition process or an atomic layer deposition process.

[0151] In other embodiments, the method for forming the tunneling material layer includes: forming an initial tunneling material layer on the surface of the first magnetic material layer using a deposition process; and performing an oxidation process on the initial tunneling material layer to form a tunneling material layer.

[0152] The first magnetic material layer 421 provides material for forming a first magnetic film, the second magnetic material layer 423 provides material for forming a second magnetic film, and the tunneling material layer 422 provides material for forming a tunneling layer.

[0153] The rollover enhancement material layer 430 provides materials for forming a rollover enhancement layer.

[0154] In this embodiment, the process of forming the rollover enhancement material layer 430 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0155] The piezoelectric material layer 440 provides material for forming a piezoelectric layer.

[0156] In this embodiment, the process of forming the piezoelectric material layer 440 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0157] The upper electrode material layer 450 provides material for forming an upper electrode layer.

[0158] In this embodiment, the process of forming the upper electrode material layer 450 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0159] In this embodiment, before forming the magnetic tunnel junction material film 420 , a seed layer material layer 490 is formed on the surface of the lower electrode material layer 410 .

[0160] The seed layer material layer 490 provides material for forming a seed layer. The seed layer can make the lattice between the magnetic tunnel junction and the lower electrode layer more matched, thereby improving the performance of the magnetic random access memory.

[0161] In this embodiment, before forming the inversion enhancing material layer 430 , a first insertion material layer 470 is formed on the surface of the magnetic tunnel junction material film 420 .

[0162] The first insertion material layer 470 provides material for forming a first insertion layer.

[0163] In this embodiment, the process of forming the first insertion material layer 470 includes a spin coating process, an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0164] In this embodiment, before forming the piezoelectric material layer 440 , a second insertion material layer 480 is formed on the surface of the inversion enhancement material layer 430 .

[0165] The second insertion material layer 480 provides material for forming a second insertion layer.

[0166] In this embodiment, the process of forming the second insertion material layer 480 includes an electroplating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0167] Please refer to Fig.10 , using the patterned layer 460 as a mask, the upper electrode material layer 450, the piezoelectric material layer 440, the flip enhancement material layer 430, the magnetic tunnel junction material layer 420 and the lower electrode material layer 410 are etched until the surface of the substrate 400 is exposed to form an upper electrode layer 451, a magnetic tunnel junction 500, a flip enhancement layer 431, a piezoelectric layer 441 and a lower electrode layer 411.

[0168] Specifically, in this embodiment, the lower electrode material layer 410 is etched to form a lower electrode layer 411 on the surface of the substrate 400; the magnetic tunnel junction material layer 420 is etched to form a magnetic tunnel junction 500 on the surface of the lower electrode layer 411; the inversion enhancement material layer 430 is etched to form a inversion enhancement layer 431 on the surface of the magnetic tunnel junction 500; the piezoelectric material layer 440 is etched to form a piezoelectric layer 441 on the surface of the inversion enhancement layer 431; and the upper electrode material layer 450 is etched to form an upper electrode layer 451 on the surface of the piezoelectric layer 441.

[0169] The piezoelectric layer 441 is used to control the magnetic moment direction of the inversion enhancement layer 431 .

[0170] When no external voltage is applied to the piezoelectric layer 441 , the magnetic moment direction of the inversion enhancement layer 431 is parallel to the magnetic moment direction of the magnetic tunnel junction 500 .

[0171] In this embodiment, the process of etching the upper electrode material layer 450 , the magnetic tunnel junction material layer 420 , the inversion enhancement material layer 430 , the piezoelectric material layer 440 and the lower electrode material layer 410 includes a reactive ion etching process or an ion beam etching process.

[0172] In this embodiment, the material of the lower electrode layer 411 includes tantalum, aluminum or copper.

[0173] In this embodiment, the material of the piezoelectric layer 441 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

[0174] In this embodiment, the thickness of the piezoelectric layer 441 is in the range of 1 nanometer to 2 nanometers. When the thickness of the piezoelectric layer 441 is in the range of 1 nanometer to 2 nanometers, the magnetic moment direction of the flip enhancement layer 431 can be better controlled.

[0175] In other embodiments, the thickness of the piezoelectric layer 441 is between 0 nanometers and 1 nanometer, or is greater than 2 nanometers and less than 10 nanometers.

[0176] In this embodiment, the material of the piezoelectric layer 441 is a piezoelectric material.

[0177] In this embodiment, the inversion enhancement layer 431 includes: more than one inversion enhancement film (not shown) overlapped along the substrate normal direction.

[0178] When the inversion enhancement layer 431 includes two or more inversion enhancement films, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) located between adjacent inversion enhancement films.

[0179] In this embodiment, the material of the inversion enhancement layer 431 includes one or more combinations of cobalt iron, cobalt iron boron or nickel iron.

[0180] In this embodiment, the magnetic moment direction of the inversion enhancement layer 431 is perpendicular or parallel to the normal direction of the surface of the substrate 400 .

[0181] In this embodiment, the magnetic tunnel junction 500 includes: a first magnetic film 501 located on the surface of the lower electrode layer 411 ; a tunneling layer 502 located on the surface of the first magnetic film 501 ; and a second magnetic film 503 located on the surface of the tunneling layer 502 .

[0182] In this embodiment, the second magnetic film 503 is a free layer, and the first magnetic film 501 is a fixed layer.

[0183] The material of the first magnetic film 501 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0184] The material of the second magnetic film 503 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0185] The material of the tunneling layer 502 includes magnesium oxide.

[0186] The magnetic tunnel junction 500 may be a perpendicular anisotropic magnetic tunnel junction or an in-plane anisotropic magnetic tunnel junction.

[0187] In this embodiment, the material of the upper electrode layer 451 includes tantalum, aluminum or copper.

[0188] In this embodiment, the patterned layer 460 is used as a mask to etch the upper electrode material layer 450, the magnetic tunnel junction material layer 420, the flip enhancement material layer 430, the piezoelectric material layer 440 and the lower electrode material layer 410, while the first insertion material layer 470, the second insertion material layer 480 and the seed layer material layer 490 are etched to form a first insertion layer 471, a second insertion layer 481 and a seed layer 491.

[0189] Specifically, in this embodiment, a first insertion layer 471 is formed between the magnetic tunnel junction 500 and the flip enhancement layer 431 , a second insertion layer 481 is formed between the flip enhancement layer 431 and the piezoelectric layer 441 , and a seed layer 491 is formed between the magnetic tunnel junction 500 and the lower electrode layer 411 .

[0190] In this embodiment, the material of the first insertion layer 471 includes a non-magnetic metal material or a non-magnetic dielectric material, and the non-magnetic metal material includes ruthenium or tantalum.

[0191] In other embodiments, the first insertion layer is not formed.

[0192] In this embodiment, the material of the second insertion layer 481 includes a non-magnetic metal material, and the non-magnetic metal material includes ruthenium or tantalum.

[0193] In other embodiments, the second insertion layer is not formed.

[0194] In other embodiments, no seed layer is formed.

[0195] It should be noted that the patterned layer 460 is completely consumed and removed during the etching process of forming the upper electrode layer 451 , the magnetic tunnel junction 500 , the flip enhancement layer 431 , the piezoelectric layer 441 and the lower electrode layer 411 .

[0196] Correspondingly, another embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, please continue to refer to Fig.10 , including: a substrate 400; a lower electrode layer 411 located on the surface of the substrate 400; a magnetic tunnel junction 500 located on the surface of the lower electrode layer 411; an upper electrode layer 451 located on the surface of the magnetic tunnel junction 500; a flip enhancement layer 431 located between the magnetic tunnel junction 500 and the upper electrode layer 451; a piezoelectric layer 441 located between the flip enhancement layer 431 and the upper electrode layer 451, wherein the piezoelectric layer 441 is used to control the magnetic moment direction of the flip enhancement layer 431, and when no external voltage is applied to the piezoelectric layer 441, the magnetic moment direction of the flip enhancement layer 431 is parallel to the magnetic moment direction of the magnetic tunnel junction 500.

[0197] In this embodiment, the substrate 400 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0198] The material of the substrate 400 includes semiconductor material.

[0199] In this embodiment, the material of the substrate 400 includes silicon.

[0200] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0201] In this embodiment, the material of the lower electrode layer 411 includes tantalum, aluminum or copper.

[0202] In this embodiment, the material of the piezoelectric layer 441 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

[0203] In this embodiment, the thickness of the piezoelectric layer 441 is in the range of 1 nanometer to 2 nanometers. When the thickness of the piezoelectric layer 441 is in the range of 1 nanometer to 2 nanometers, the magnetic moment direction of the flip enhancement layer 431 can be better controlled.

[0204] In other embodiments, the thickness of the piezoelectric layer 441 is between 0 nanometers and 1 nanometer, or is greater than 2 nanometers and less than 10 nanometers.

[0205] In this embodiment, the material of the piezoelectric layer 441 is a piezoelectric material.

[0206] In this embodiment, the inversion enhancement layer 431 includes: more than one inversion enhancement film (not shown) overlapped along the substrate normal direction.

[0207] When the inversion enhancement layer 431 includes two or more inversion enhancement films, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) located between adjacent inversion enhancement films.

[0208] In this embodiment, the material of the inversion enhancement layer 431 includes one or more combinations of cobalt iron, cobalt iron boron or nickel iron.

[0209] In this embodiment, the magnetic moment direction of the inversion enhancement layer 431 is perpendicular or parallel to the normal direction of the surface of the substrate 400 .

[0210] In this embodiment, the magnetic tunnel junction 500 includes: a first magnetic film 501 located on the surface of the lower electrode layer 411 ; a tunneling layer 502 located on the surface of the first magnetic film 501 ; and a second magnetic film 503 located on the surface of the tunneling layer 502 .

[0211] In this embodiment, the first magnetic film 501 is a fixed layer, and the second magnetic film 503 is a free layer.

[0212] The material of the first magnetic film 501 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0213] The material of the second magnetic film 503 includes one or a combination of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron or nickel-iron.

[0214] The material of the tunneling layer 502 includes magnesium oxide.

[0215] The magnetic tunnel junction 500 may be a perpendicular anisotropic magnetic tunnel junction or an in-plane anisotropic magnetic tunnel junction.

[0216] In this embodiment, the material of the upper electrode layer 451 includes tantalum, aluminum or copper.

[0217] In this embodiment, the semiconductor structure further includes: a first insertion layer 471 located between the magnetic tunnel junction 500 and the flip enhancement layer 431 .

[0218] Since the first insertion layer 471 is provided between the magnetic tunnel junction 500 and the flip enhancement layer 431 , the coupling between the flip enhancement layer 431 and the magnetic tunnel junction 500 can be reduced.

[0219] The material of the first insertion layer 471 includes a non-magnetic metal material or a non-magnetic dielectric material. The non-magnetic metal material includes ruthenium or tantalum.

[0220] In other embodiments, the semiconductor structure does not include a first insertion layer.

[0221] In this embodiment, the semiconductor structure further includes: a second insertion layer 481 located between the inversion enhancement layer 431 and the piezoelectric layer 441 .

[0222] Since there is a second insertion layer 481 between the flip enhancement layer 431 and the piezoelectric layer 441, on the one hand, the flip enhancement layer 431 of magnetic material and the piezoelectric layer 441 of non-magnetic material can be isolated by the second insertion layer 481, thereby reducing the mutual influence such as diffusion between the materials of the flip enhancement layer 431 and the piezoelectric layer 441. On the other hand, the second insertion layer 481 can better enable the flip enhancement layer 431 to form a magnetic moment in a specific direction.

[0223] The material of the second insertion layer 481 includes a non-magnetic metal material, and the non-magnetic metal material includes ruthenium or tantalum.

[0224] In other embodiments, the semiconductor structure does not include a second insertion layer.

[0225] In this embodiment, the semiconductor structure further includes: a seed layer 491 located between the magnetic tunnel junction 500 and the lower electrode layer 411 .

[0226] In other embodiments, the semiconductor structure does not include a seed layer.

[0227] Figures 11 to 13 It is a schematic diagram of the working principle of a semiconductor structure according to another embodiment of the present invention.

[0228] It should be noted that Figures 11 to 13 The schematic diagram shows the flip enhancement layer 431 and the magnetic moment direction of the magnetic tunnel junction 500 when the magnetic tunnel junction 500 is an in-plane anisotropic magnetic tunnel junction. When the magnetic tunnel junction 500 is a perpendicular anisotropic magnetic tunnel junction, the working principle of the semiconductor structure is the same as the working principle when the magnetic tunnel junction 500 is an in-plane anisotropic magnetic tunnel junction, and will not be repeated here.

[0229] Please refer to Fig.11 , Fig.11 The initial state of the semiconductor structure is schematically shown. When no data is written, that is, when no external bias voltage is applied to the piezoelectric layer 441 , the magnetic moment direction of the flip enhancement layer 431 is parallel to the magnetic moment direction of the magnetic tunnel junction 500 .

[0230] Specifically, at this time, the magnetic moment directions of the switching enhancement layer 431 are parallel to the magnetic moment directions of the first magnetic film 501 , the tunneling layer 502 , and the second magnetic film 503 .

[0231] Please refer to Fig.12 and Fig.13 , Fig.12 Schematically shows the state of the semiconductor structure during the data writing process. Fig.13The schematic diagram shows the state of the semiconductor structure after writing data. When writing data, an external bias voltage is applied to the upper electrode layer 451 and the piezoelectric layer 441. The external bias voltage can generate stress in the piezoelectric layer 441, and the magnetic moment direction of the flip enhancement layer 431 is flipped 90 degrees by the stress, that is, the magnetic moment direction of the flip enhancement layer 431 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 500, so that the flip enhancement layer 431 can provide an additional bias magnetic field for the magnetic tunnel junction 500 when writing data.

[0232] Specifically, on the one hand, a bias magnetic field is provided to the magnetic tunnel junction 500 through an external bias voltage, and on the other hand, an additional bias magnetic field is provided to the magnetic tunnel junction 500 through the flip enhancement layer 431 whose magnetic moment direction has been flipped 90 degrees, thereby causing the magnetic moment direction of the second magnetic film 503 serving as the free layer to flip 180 degrees to complete data writing.

[0233] After the data writing is completed, the semiconductor structure is again in a state where no external bias voltage is applied to the upper electrode layer 451 and the piezoelectric layer 441. At this time, the piezoelectric layer 441 no longer generates stress (the piezoelectric layer 441 returns to its original state). Therefore, the magnetic moment direction of the flip enhancement layer 431 returns to the magnetic moment direction of the flip enhancement layer 431 in the initial state of the semiconductor structure. At this time, the magnetic moment direction of the flip enhancement layer 431 is parallel to the magnetic moment direction of the magnetic tunnel junction 500 again.

[0234] Since the semiconductor structure includes a piezoelectric layer 441 located between the flip enhancement layer 431 and the upper electrode layer 451, when writing data, the piezoelectric layer 441 can generate stress through an external bias voltage, and the magnetic moment direction of the flip enhancement layer 431 is flipped 90 degrees through the stress, that is, the magnetic moment direction of the flip enhancement layer 431 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 500, so that the flip enhancement layer 431 can provide an additional bias magnetic field for the magnetic tunnel junction 500 when writing data, so as to reduce the write power consumption; at the same time When no data is written, due to the absence of an external bias voltage, the stress generated by the piezoelectric layer 441 disappears, causing the magnetic moment direction of the flip enhancement layer 431 to flip 90 degrees again, that is, the magnetic moment direction of the flip enhancement layer 431 returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction 500, and the flip enhancement layer 431 does not generate a bias magnetic field that affects the magnetic moment direction of the second magnetic film 503. Thus, when no data is written, the influence of the flip enhancement layer 431 on the magnetic moment direction of the second magnetic film 503 can be reduced, thereby improving the reliability and stability of the magnetic random access memory. In summary, through the flip enhancement layer 431 and the piezoelectric layer 441, the reliability and stability of the magnetic random access memory can be improved while reducing the write power consumption of the magnetic random access memory.

[0235] It should be noted that, for ease of understanding, Figures 11 to 13 The magnetic moment directions of the flip enhancement layer 431 and the magnetic tunnel junction 500 are only schematically shown. The magnetic moment directions of the flip enhancement layer 431 and the magnetic tunnel junction 500 may also be different from those of the flip enhancement layer 431 and the magnetic tunnel junction 500. Figures 11 to 13 The magnetic moments in the .

[0236] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A lower electrode layer located on the surface of the substrate; A magnetic tunnel junction located on the surface of the lower electrode layer; An upper electrode layer located on the surface of the magnetic tunnel junction; A flip enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer; A piezoelectric layer, the piezoelectric layer is used to control the magnetic moment direction of the flip enhancement layer, when the flip enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is located between the flip enhancement layer and the upper electrode layer, when the flip enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is located between the flip enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the flip enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; a first insertion layer, the first insertion layer being located between the flip enhancement layer and the magnetic tunnel junction; A second insertion layer is disposed between the inversion enhancement layer and the piezoelectric layer.

2. The semiconductor structure according to claim 1, wherein: The material of the piezoelectric layer is piezoelectric material.

3. The semiconductor structure according to claim 2, wherein: The material of the piezoelectric layer includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

4. The semiconductor structure according to claim 1, wherein: The thickness of the piezoelectric layer is greater than 0 nanometers, and the thickness of the piezoelectric layer is less than 10 nanometers.

5. The semiconductor structure according to claim 1, wherein: The magnetic moment direction of the inversion enhancement layer is perpendicular or parallel to the normal direction of the substrate surface.

6. The semiconductor structure according to claim 1, wherein: When the inversion enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the semiconductor structure further includes: a seed layer located between the lower electrode layer and the magnetic tunnel junction.

7. The semiconductor structure according to claim 1, wherein: When the inversion enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the semiconductor structure further includes: a buffer layer located between the lower electrode layer and the piezoelectric layer.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a piezoelectric layer on the surface of the lower electrode layer; Forming a reversal enhancement layer on the surface of the piezoelectric layer, wherein the piezoelectric layer is used to control the magnetic moment direction of the reversal enhancement layer; A magnetic tunnel junction is formed on the surface of the inversion enhancement layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the inversion enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; forming an upper electrode layer on the surface of the magnetic tunnel junction; forming a first insertion layer between the magnetic tunnel junction and the inversion enhancement layer; A second insertion layer is formed between the inversion enhancement layer and the piezoelectric layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: A buffer layer is formed between the piezoelectric layer and the lower electrode layer.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a magnetic tunnel junction on the surface of the lower electrode layer; forming a flip enhancement layer on the surface of the magnetic tunnel junction; A piezoelectric layer is formed on the surface of the inversion enhancement layer, wherein the piezoelectric layer is used to control the magnetic moment direction of the inversion enhancement layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the inversion enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; forming an upper electrode layer on the surface of the piezoelectric layer; A first insertion layer is formed between the flip enhancement layer and the magnetic tunnel junction A second insertion layer is formed between the piezoelectric layer and the inversion enhancement layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: A seed layer is formed between the magnetic tunnel junction and the lower electrode layer.

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