Output stage compensated operational amplifier

Abstract

A circuit includes a first transconductance stage (504) having an output. The circuit further includes an output transconductance stage (408), and a first source degenerated transistor (M3A, RDA) having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage (504). The circuit also includes a second transistor (M4A) having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage (408).

Description

Background Technology

[0001] Operational amplifiers (op amps) are used for a variety of purposes. One such purpose is as a buffer to provide a reference voltage to an analog-to-digital converter (ADC). Larger capacitors may be coupled to the op amp, and such op amps are typically output-terminated for stability (i.e., to reduce ringing at the output node of the buffer). Summary of the Invention

[0002] In one example, a circuit includes a first transconductance stage coupled to an input node. The circuit also includes an output transconductance stage and a second transconductance stage coupled between the first transconductance stage and the output transconductance stage. The second transconductance stage includes a transistor with a first source degradation. Attached Figure Description

[0003] To describe the various examples in detail, reference will now be made to the accompanying illustrations, in which:

[0004] Figure 1 This illustrates an example of an op amp that has a limited output current range due to stability issues.

[0005] Figure 2 Explanation and solution Figure 1 Another example of the stability problem of op amp.

[0006] Figure 3 exhibit Figure 2 A more detailed illustration of an example.

[0007] Figure 4 This illustrates another example of an op amp that has a limited output current range due to stability issues.

[0008] Figure 5 Explanation and solution Figure 4 The stability problem of op amp.

[0009] Figure 6 exhibit Figure 4 A more detailed illustration of an example.

[0010] Figure 7 This section describes another example of an op amp with a Class AB output stage, which has a limited output current range due to stability issues.

[0011] Figure 8 Demonstrating solutions Figure 7 The stability problem of op amp.

[0012] Figure 9 exhibit Figure 8 A more detailed illustration of an example.

[0013] Figure 10 Another example of an op amp with a class AB output stage is described that has a limited output current range due to stability issues.

[0014] Figure 11 An op amp that solves the stability issues of Figure 10 is shown.

[0015] Figure 12 A more detailed schematic of an example of Figure 11 is shown. DETAILED DESCRIPTION

[0016] Some op amps not only have a large capacitor as mentioned above, but also support a large direct current (DC) current for a class A or class AB output stage. The transconductance of the output stage of an op amp can vary with the current into / out of the load. Figure 1 An example of at least a portion of an op amp 100 is shown. In this example, the op amp 100 includes three stages— an input transconductance stage 102, an output transconductance stage 106, and a transconductance stage 104 coupled between the input transconductance stage 102 and the output transconductance stage 106. The input transconductance stage 102 includes a transconductance (GM) amplifier GM1 (GM1 also refers to the value of the transconductance of the amplifier), a resistor R1, and a capacitor C1. The transconductance stage 104 includes a GM amplifier GM2 (GM2 also refers to the value of the transconductance of the amplifier), a resistor R2, and a capacitor C2. The output transconductance stage 106 includes transistors M1 and M2. The transconductance of M1 is GMOUT.

[0017] The GM amplifier GM1 is a differential amplifier with positive (+) and negative (-) inputs and positive and negative outputs. The resistor R1 and capacitor C1 are coupled in parallel between the positive and negative outputs of the GM amplifier GM1 and across the positive and negative inputs of the GM amplifier GM2. The GM amplifier GM2 also has positive and negative inputs and a single output coupled to a resistor R2 and a capacitor C2 as shown. The resistor R2 and capacitor C2 are coupled in parallel between the output of the GM amplifier GM2 and ground. The output of the GM amplifier GM2 is also coupled to the control input of the transistor M1. In this example, the transistor M1 is a p-type metal oxide semiconductor field effect transistor (PMOS transistor) and the transistor M2 is an n-type metal oxide semiconductor field effect transistor (NMOS transistor). The control input of the transistor M1 is the gate of M1, which is coupled to the output of the GM amplifier GM2, resistor R2, and resistor C2. The gate of M2 is biased at a voltage labeled NBIAS, which is sufficient to turn on transistor M2 and operate the transistor in the saturation region. The drains of transistors M1 and M2 are connected together at node 110, which provides the output voltage of the op amp 100. The capacitor CL is external to the op amp 100, i.e., the capacitor CL is provided separate from the semiconductor die that includes the GM amplifier GM1, GM amplifier GM2, resistor R1, resistor R2, capacitor C1, capacitor C2, transistor M1, and transistor M2. The current source IDC represents the DC current to the load. In this example, the load current is a "source" current, since the current flows from the supply voltage node VDDA through transistor M1 and through the load to ground.

[0018] The bandwidth of the op amp 100 is given by:

[0019] BW = GM1 * R1 * GM2 * R2 * GMOUT / CL (1)

[0020] where BW is the bandwidth of the op amp. The transconductance of M1 (GMOUT) varies with the DC load current (IDC). Thus, GMOUT increases as the load current increases. Furthermore, according to equation (1), as GMOUT increases, the bandwidth (BW) of the op amp 100 also increases. As such, the bandwidth of the op amp is directly proportional to the load current. The non-dominant pole of the transfer function of the op amp is at a frequency given by 1 / (R1*C1) and by 1 / (R2*C2). Although the bandwidth of the op amp increases as the load current increases, the non-dominant pole does not scale with the load current and thus remains at 1 / (R1*C1) and 1 / (R2*C2). As such, as the load current increases, the phase margin of the op amp decreases, and as the phase margin gets low (e.g., 15 degrees), the output voltage will oscillate. In Figure 1In this example, the phase margin decreases as the load current increases, so an upper limit is imposed on the DC current to the load to avoid instability.

[0021] Figure 2 Demonstrating solutions Figure 1 An example of at least a portion of op amp 200 is provided to address the instability problem of op amp 100. In this example, op amp 200 comprises four stages—an input transconductance stage 202, an output transconductance stage 208, and transconductance stages 204 and 206 coupled between the input transconductance stage 202 and the output transconductance stage 208. Input transconductance stage 202 comprises a GM amplifier GM1, a resistor R1, and a capacitor C1. Transconductance stage 204 comprises a GM amplifier GM2, a resistor R2, and a capacitor C2. Output transconductance stage 208 comprises transistors M1 and M2.

[0022] and Figure 1 Similar to the example, GM amplifier GM1 is a differential amplifier with positive (+) and negative (-) inputs and positive and negative outputs. Resistor R1 and capacitor C1 are coupled in parallel between the positive and negative outputs of GM amplifier GM1 and across the positive and negative inputs of GM amplifier GM2. GM amplifier GM2 also has positive and negative inputs and a single output coupled to resistor R2 and capacitor C2 as shown. Resistor R2 and capacitor C2 are coupled in parallel between the output of GM2 and ground.

[0023] Transconductance stage 206 includes transistors M3 and M4 and resistor RD. In this example, transistor M3 is an NMOS transistor, and transistor M4 is a PMOS transistor. The source of transistor M4 is coupled to the supply voltage node VDDA. The drains of transistors M3 and M4 are connected together. The source of transistor M3 is connected to resistor RD. Resistor RD is coupled between transistor M3 and ground. The inclusion of resistor RD connected to the source of transistor M3 means that transistor M3 is "source degraded". Thus, transconductance stage 206 includes a source-degraded transistor. The output of GM amplifier GM2 is coupled to the gate of transistor M3. The transconductance of transistor M3 is GM3, and the transconductance of transistor M4 is GM4.

[0024] The output transconductance stage includes transistors Ml and M2. Transistor Ml is a PMOS transistor, and transistor M2 is an NMOS transistor. The transconductance of transistor Ml is GMOUT. The gate of transistor Ml is connected to the gate of transistor M4. The gates of transistors Ml and M4 are connected to the drain of transistor M4. Transistors Ml and M4 are configured as a current mirror, such that the drain current through transistor M4 is proportional to the drain current through transistor Ml. The drains of transistors Ml and M2 are connected together at node 210, which provides the output voltage of op amp 200. The source of transistor M2 is connected to ground. An external capacitor CL is connected to node 210.

[0025] The bandwidth of op amp 200 is given by:

[0026]

[0027] where GM3D is the transconductance of source-degenerated transistor M3, and is given by:

[0028] GM3D = GM3 / (l + GM3*RD) (3)

[0029] As explained above, GMOUT scales with the DC load current, and thus increases as the load current increases. However, due to the current mirror configuration of transistors Ml and M4, the bandwidth of op amp 200 is proportional to the ratio of GMOUT to GM4, as can be seen from the above equation 2. Furthermore, as the load current increases, the drain current through transistor M4 also increases due to the current mirror configuration of transistors Ml and M4, and thus, the ratio of GMOUT to GM4 does not change. Increasing the drain current through transistor M4 causes the drain current through transistor M3 to increase. From this, the drain current through transistor M3 is proportional to the DC load current. The bandwidth of op amp 200 varies in part with GM3D. As can be seen from equation (3), GM3D approaches 1 / RD as GM3 gets large. That is, GM3D increases as the load current increases, but saturates at 1 / RD due to transistor M3 being source-degenerated. In summary, the effect of including source-degenerated transistor M3 is that the bandwidth of op amp 200 does not change significantly with changes in the DC load current, unlike the case of op amp 100. Figure 1 Thus, op amp 200 is more stable (has a greater phase margin) over a larger range of DC load currents than op amp 100.

[0030] Figure 3 It is shown that Figure 2A more detailed schematic of op amp 200 is shown. Additional details are shown for GM amplifiers GM1 and GM2. In this example, GM amplifier GM1 includes NMOS transistors M5, M6, and M9, and PMOS transistors M7 and M8. The sources of transistors M7 and M8 are connected to the supply voltage node VDDA. The drains of transistors M5 and M7 are connected together at node 310, and the drains of transistors M6 and M8 are connected together at node 320. Figure 2 Resistor R1 in Figure 3 In this example, two resistors R1A and R1B are connected in series between nodes 310 and 320. The intermediate connection point 325 of the series-connected resistors R1A and R1B is connected to the gates of transistors M7 and M8. The sources of transistors M5 and M6 are connected together and connected to the drain of M9. The source of transistor M9 is connected to the negative supply voltage node VSSA. The gate of transistor M9 is biased via a bias voltage BIAS1 such that tail current flows through transistor pair M7 and M5, or through transistor pair M8 and M6, depending on the relative magnitudes of the input voltages at the gates of transistors M5 and M6. The input voltage at the gate of transistor M6 is the reference voltage VREF, and the input voltage at the gate of transistor M5 is the output voltage from node 210. In one example, from Figure 2 Capacitor C1 is the parasitic capacitance at nodes 310 and 320. The parasitic capacitance at node 310 is the sum of the gate parasitic capacitance of transistor M10, the drain parasitic capacitance of transistor M5, and the drain parasitic capacitance of transistor M7. The parasitic capacitance at node 320 is the sum of the gate parasitic capacitance of transistor M11, the drain parasitic capacitance of transistor M8, and the drain parasitic capacitance of transistor M6.

[0031] The output from transconductance stage 202 is obtained across nodes 310 and 320 as shown. Transconductance stage 204 includes transistors M10 through M18. In this example, transistors M10, M11, M12, M17, and M18 are NMOS transistors, and transistors M13, M14, M15, and M16 are PMOS transistors. Node 310 is connected to the gate of transistor M10, and node 320 is connected to the gate of transistor M11. Transistors M10 and M11 include the input transistors of transconductance stage 204. The sources of transistors M10 and M11 are connected together and connected to the drain of transistor M12. The gate of transistor M12 is biased at a bias voltage BIAS2 such that tail current flows through transistor M10 or through transistor M11, depending on the relative magnitude of the input voltages of transconductance stage 204 at the gates of transistors M10 and M11.

[0032] The sources of transistors M13 and M14 are connected together and connected to the supply voltage node VDDA. The gates of transistors M13 and M14 are connected together and connected to the bias voltage BIAS3. The drain of transistor M13 is connected to the source of transistor M15, and the drain of transistor M14 is connected to the source of transistor M16. The gates of transistors M15 and M16 are connected together and connected to the bias voltage BIAS4. The drains of transistors M15 and M17 are connected together at node 330. The drains of transistors M16 and M18 are connected together at node 340. Figure 2 Resistor R2 is connected between nodes 330 and 340 as shown. The drain and gate of transistor M17 are connected together, and also connected to the gate of transistor M18. The sources of transistors M12, M17, and M18 are connected together and connected to the negative supply voltage node VSSA. Node 340 is connected to the gate of transistor M3. The capacitance of capacitor C2 is the sum of the parasitic capacitance of transistor M3, the drain parasitic capacitance of transistor M16, and the drain parasitic capacitance of transistor M18.

[0033] Figure 4 The example shown is op amp 400, which is similar to Figure 1 The op amp has an output transconductance stage 408 that includes a PMOS transistor M20 and an NMOS transistor M21. Transconductance stages 102 and 504 are respectively connected to... Figure 1 Stages 102 and 104 are the same or similar. The source of transistor M20 is connected to the supply voltage node VDDA, and its drain is connected at the output node 410 to the drain of transistor M21 and to capacitor CL as shown. The source of transistor M21 is connected to ground. In this example, the load current is a "sinking" current because the current flows from the supply voltage node VDDA through the load and through transistor M21 to ground. The bandwidth of op amp 400 is determined by the above equation (1), and therefore op amp 400 suffers from the same stability problem as op amp 100 (instability due to the increase in DC load current IDC).

[0034] Figure 5 This is an example of op amp 500, which is related to the above about Figure 3 Solve in roughly the same way as described Figure 4stability issues of the op amp 400. That is, the intermediate transconductance stage 406 is included between the transconductance stage 504 and the output transconductance stage 408. The transconductance stage 406 includes transistors M3A, M4A, and resistor RDA. In this example, transistor M4A is an NMOS transistor, and transistor M3A is a PMOS transistor. The source of transistor M4A is connected to ground, and the drains of transistors M4A and M3A are connected together. The gates of transistors M4A and M21 are connected together and to the drain of transistor M4A. The sources of transistors M4A and M21 are connected together. Thus, transistors M4A and M21 are configured as a current mirror, as in Figure 2 the condition of transistors M1 and M4 in the example of

[0035] Resistor RDA is connected between the source of transistor M3A and the supply voltage node VDDA, thereby configuring transistor M3A as a source-degenerated transistor, as in Figure 2 the condition of source-degenerated transistor M3 in op amp 400. The bandwidth of op amp 400 is determined by equations (2) and (3). Thus, the effect of including source-degenerated transistor M3A is that the bandwidth of op amp 500 does not change significantly with changes in DC load current, unlike Figure 4 the condition of op amp 400. Thus, op amp 500 is more stable (has a greater phase margin) over a greater range of DC load current than op amp 400.

[0036] Figure 6 shows Figure 5 a more detailed schematic diagram of op amp 500. For Figure 5 transconductance stages 102 and 504 of op amp 400 are shown with additional details. Figure 6 Input transconductance stage 102 in op amp 400 has transistors M5 to M8, and is configured in the same circuit architecture as Figure 3 input transconductance stage 102 of op amp 500. Figure 6 Transconductance stage 504 in op amp 500 includes transistors M22 to M25 and resistor R2. Transistors M22, M23, and M26 are NMOS transistors, and transistors M24 and M25 are PMOS transistors. The sources of transistors M24 and M25 are connected together and to the supply voltage node VDDA. The drains of transistors M24 and M22 are connected together at node 610, and the drains of transistors M25 and M23 are connected together at node 620. Resistor R2 is connected between nodes 610 and 620, and node 610 is also connected to the gates of transistors M24 and M25. The sources of transistors M22 and M23 are connected to the drain of transistor M26. The source of transistor M26 is connected to VSSA. The gate of transistor M26 is biased via BIAS2. Node 620 is connected to the gate of transistor M3A.

[0037] Figures 1 to 6 Examples include instances of op amps that have a Class A output stage, i.e., an output stage that only provides (or sinks) current. For example, in Figures 1 to 3 In the middle, the output transconductance stage of the op amp supplies current to the load, while... Figures 4 to 6 In this example, the output transconductance stage of the op amp absorbs current from the load. Figure 7 An example of op amp700 is shown, where the output transconductance stage 706 includes a PMOS transistor M30 connected to an NMOS transistor M31. In one direction, current flows from VDDA through transistor M30, through the load, and through capacitor CL. In the opposite direction, current flows from the load through transistor M31 to ground. The transconductance of transistor M30 is GMPOUT, and the transconductance of transistor M31 is GMNOUT.

[0038] The op amp 700 includes (as described above) an input transconductance stage 102 and a transconductance stage 702. Transconductance stage 702 includes a transconductance amplifier GM2, resistors R3A and R3B, and transistors M32 and M33. The resistance of R3A is the same as that of R3B. The transconductance of transistor M32 is GM5, and the transconductance of transistor M33 is GM6. The bandwidth of op amp 700...

[0039]

[0040] Where R3 is the resistance of R3A and R3B. Figure 1 op amp 100 and Figure 4 The same instability problem exists in op amp 700 as in op amp 400. That is, as the load current of op amp 700 increases, the GMPOUT of transistor M30 or the GMNOUT of transistor M31 increases and therefore the bandwidth increases, causing the non-dominant electrode to operate at frequencies within the bandwidth of the op amp.

[0041] Figure 8 Demonstrating solutions Figure 7 The instability problem of op amp 700 is addressed in op amp 800. op amp 800 includes input transconductance stage 202, transconductance stage 802, transconductance stage 804, and output transconductance stage 706. Transconductance stages 802 and 804 are coupled between input transconductance stage 202 and output transconductance stage 706. Transconductance stage 802 is similar to... Figure 7 The transconductance stage 702 is connected, but resistor RDP1 is connected between the source of transistor M32 and VDDA. Therefore, transistor M32 is source degraded.

[0042] Transconductance stage 804 includes transistors M34-M37 and resistor RDP2. Resistor RDP2 is connected between the source of transistor M34 and VDDA, and thus configures transistor M34 as a source degenerated transistor. The drain of transistor M34 is connected to the drain of transistor M36 and to the gates of transistors M36 and M37. The drains of transistors M35 and M37 are connected together and to the gates of transistors M35 and M30. The sources of transistors M35 and M30 are connected together at supply voltage node VDDA. The sources of transistors M36 and M37 are connected to ground. Transistors M35 and M30 are configured as a current mirror. Transistors M36 and M37 are also configured as a current mirror.

[0043] The transconductances of transistors M34, M35, M36, and M37 are GM7, GM8, GM9, and GM10, respectively. Resistor RDP1 degenerates and limits the effective transconductance of transistor M32, and similarly, resistor RDP2 degenerates and limits the effective transconductance of transistor M34. Transconductance stage 804 facilitates degeneration of transistor M34, and is a high bandwidth stage of relatively low gain. The bandwidth of op amp 800 is provided in equation (5) below:

[0044]

[0045] A change in load current causes a corresponding change in GMPOUT as explained above. Because transistors M30 and M35 are configured as a current mirror, the drain current through transistor M35 tracks the drain current through transistor M30, and thus the change in GM8 of transistor M35 is also proportional to the change in GMPOUT. As can be observed from equation (5), the bandwidth of op amp 800 varies with the ratio of GMPOUT to GM8. Thus, a change in load current that causes a change in GMPOUT does not substantially change the bandwidth of the op amp. The bandwidth also varies with the ratio of GM7 to 1 + (GM7)(RDP2). GM7 can vary with a change in load current, but as GM7 increases, the ratio of GM7 to 1 + (GM7)(RDP2) approaches 1 / GM7. The bandwidth further varies with the ratio of GM5 to 1 + (GM5)(RDP1). GM5 can vary with a change in load current, but as GM5 increases, the ratio of GM5 to 1 + (GM5)(RDP1) approaches limiting 1 / GM5.

[0046] Figure 9 Op amp 800 is also illustrated, but with additional details. The implementation of input transconductance stage 202 is the same as shown in and described above in Figure 3 Figure 9 ​Transconductance stage 802 includes transistors M33 and M38 through M42 and resistor RDP1. Transistors M38, M39, and M42 are NMOS transistors, and transistors M40 and M41 are PMOS transistors. The sources of transistors M40 and M41 are connected together and connected to the supply voltage node VDDA. The drains of transistors M40 and M38 are connected together at node 810, and the drains of transistors M41 and M39 are connected together at node 820. Resistors R3A and R3B are connected in series between nodes 810 and 820, and the node between resistors R3A and R3B is connected to the gates of transistors M40 and M41. The sources of transistors M38 and M39 are connected to the drain of transistor M42. The source of transistor M46 is connected to VSSA. The gate of transistor M42 is biased via BIAS2. Node 820 is connected to the gate of transistor M34.

[0047] as Figure 7 The status of op amp 700 in the middle, Figure 10 An example of an op amp1000 with a class AB output transconductance stage 706 is shown. The input transconductance stage 102 of the op amp1000 is also connected to... Figure 7 The input transconductance stage 102 of op amp 700 is the same. The intermediate transconductance stage 1002 includes transconductance amplifier GM2, resistors R4A and R4B, and transistors M45 and M46. The transconductance of transistor M45 is GM11, and the transconductance of transistor M46 is GM12. Transistor M45 is a PMOS transistor, and transistor M46 is an NMOS transistor. The drains of transistors M45 and M46 are connected together and connected to the gates of transistors M45 and M30. Transconductance amplifier GM2 drives the gates of transistors M46 and M31. op amp 1000 suffers from the same instability problems as op amp 700.

[0048] Figure 11 Demonstrating solutions Figure 10 The instability problem of op amp 1000 is addressed in op amp 1100. op amp 1100 includes input transconductance stage 202, transconductance stage 1102, transconductance stage 1104, and output transconductance stage 706. Transconductance stages 1102 and 1104 are coupled between input transconductance stage 202 and output transconductance stage 706. Transconductance stage 1102 is similar to... Figure 10 The transconductance stage 1002 is connected, but resistor RDN1 is connected between the source of transistor M46 and ground. Therefore, transistor M46 is source-degraded.

[0049] The transconductance stage 1104 includes transistors M47-M50 and resistor RDN2. Resistor RDN2 is connected between the source of transistor M47 and ground, and thus configures transistor M47 as a source degenerated transistor. The drain of transistor M47 is connected to the drain of transistor M49 and to the gates of transistors M49 and M50. The drains of transistors M48 and M50 are connected together and to the gates of transistors M48 and M31. The sources of transistors M48 and M31 are connected together at a ground node. The sources of transistors M36 and M37 are connected to ground. Transistors M48 and M31 are configured as a current mirror. Transistors M49 and M50 are also configured as a current mirror.

[0050] The bandwidth of the op amp 1100 is given by equation (6).

[0051]

[0052] A change in load current causes a corresponding change in GMNOUT. Because transistors M31 and M48 are configured as a current mirror, the drain current through transistor M48 tracks the drain current through transistor M31, and thus the change in GM16 of transistor M48 is also proportional to the change in GMNOUT. As can be observed from equation (6), the bandwidth of the op amp 1100 varies with the ratio of GMNOUT to GM16. Thus, a change in load current that causes a change in GMNOUT does not substantially change the bandwidth of the op amp 1100. The bandwidth also varies with the ratio of GM15 to 1 + (GM15)(RDN2). GM15 can change with a change in load current, but as GM15 increases, the ratio of GM15 to 1 + (GM15)(RDN2) approaches 1 / GM15. The bandwidth further varies with the ratio of GM12 to 1 + (GM12)(RDN1). GM12 can change with a change in load current, but as GM12 increases, the ratio of GM12 to 1 + (GM12)(RDN1) approaches 1 / GM12. By source degenerating transistors M46 and M47 and including current mirrors M48 / M31 and M49 / M50, the bandwidth of the op amp 1100 does not change significantly with a change in DC load current nearly as much as the case of the op amp 1000 of FIG. 1. Figure 10 Thus, the op amp 1100 is more stable (has a greater phase margin) over a greater range of DC load current than the op amp 1000.

[0053] Figure 12 The op amp 1100 is also illustrated, but with additional details. The implementation of the input transconductance stage 202 is the same as shown in FIG. 2 and described above. Figure 3 The implementation of the input transconductance stage 202 is the same as shown in FIG. 2 and described above. Figure 12The transconductance stage 1102 in Figure 11 includes transistors M51-M59 and resistor RDN1. Transistors M57 and M58 comprise an input transistor pair, and transistor M59 is biased by voltage BIAS2. Transistors M51 and M52 are NMOS transistors, and transistors M53-M56 are PMOS transistors. The sources of transistors M55 and M56 are connected together and to the supply voltage node VDDA. The gates of transistors M55 and M56 are biased by BIAS5. The drain of transistor M55 is connected to the source of transistor M53 and to the drain of transistor M57, and the drain of transistor M56 is connected to the source of transistor M54 and to the drain of transistor M58. The gates of transistors M53 and M54 are biased by BIAS6. The drains of transistors M53 and M51 are connected together at node 1110, and the drains of transistors M54 and M52 are connected together at node 1120. Resistors R4A and R4B are connected in series between nodes 1110 and 1120, and the node between resistors R4A and R4B is connected to the gates of transistors M51 and M52. The sources of transistors M51 and M52 are connected to VSSA. Node 1110 is connected to the gate of transistor M47, and node 1120 is connected to the gate of transistor M46.

[0054] Modifications are possible in the described examples, and other examples are possible. The scope of the claims should not be limited to the described examples.

Claims

1. An amplifier circuit comprising: a first transconductance stage coupled to an input node; an output transconductance stage including a third transistor having a third control input and third and fourth current terminals; and a second transconductance stage coupled between the first transconductance stage and the output transconductance stage, the second transconductance stage including a first source degenerated transistor; a second transistor including a second control input and first and second current terminals, the second control input and the third control input coupled together and the first current terminal and the third current terminal coupled together, and the second current terminal coupled to the first source degenerated transistor.

2. The circuit of claim 1, wherein: the first source degenerated transistor includes a control input and fifth and sixth current terminals; the second transconductance stage includes the second transistor; and the sixth current terminal is coupled to the second current terminal.

3. The circuit of claim 2, wherein an output node of the first transconductance stage is coupled to the control input of the first source degenerated transistor.

4. The circuit of claim 1, further comprising a second source degenerated transistor coupled between the first transconductance stage and the output transconductance stage.

5. The circuit of claim 4, wherein the second source degenerated transistor includes a control input coupled to an output node of the first transconductance stage.

6. The circuit of claim 1, wherein: the output transconductance stage includes a fourth transistor having a fourth control input and fifth and sixth current terminals; the second transconductance stage includes a fifth transistor having a fifth control input and seventh and eighth current terminals; and the sixth current terminal is coupled to the seventh current terminal and the fourth control input is coupled to the fifth control input.

7. An amplifier circuit comprising: a first transconductance stage having an output; an output transconductance stage including a third transistor having a third control input; a first source degenerated transistor having a first control input and first and second current terminals, the first control input coupled to the output of the first transconductance stage; and a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the second current terminal and to the output transconductance stage, the third control input coupled to the third current terminal and to the second control input.

8. The circuit of claim 7, further comprising a second source degenerated transistor coupled between the first transconductance stage and the output transconductance stage.

9. The circuit of claim 8, wherein the second source degenerated transistor includes a fourth control input coupled to an output node of the first transconductance stage.

10. The circuit of claim 7, further comprising a second transconductance stage, wherein the first transconductance stage is coupled between the second transconductance stage and the first control input of the first source degenerated transistor.

11. The circuit of claim 7, wherein the output transconductance stage is one of a class A or a class AB output stage.

12. An amplifier circuit comprising: a first transconductance stage having an output; a second transconductance stage having an input and an output, the input of the second transconductance stage coupled to the output of the first transconductance stage; an output transconductance stage having a fourth transistor; and a third transconductance stage coupled between the second transconductance stage and the output transconductance stage, the third transconductance stage including a first source degenerated transistor having a first control input coupled to the output of the second transconductance stage, the third transconductance stage further including a fifth transistor coupled to the first source degenerated transistor, and the fifth transistor coupled to the fourth transistor in a current mirror configuration.

13. The circuit of claim 12, wherein the second transconductance stage comprises a second source degenerated transistor.

14. The circuit of claim 13, wherein the second transconductance stage comprises a transconductance amplifier having an output, and wherein the second source degenerated transistor includes a control input coupled to the output of the transconductance amplifier.

15. The circuit of claim 14, wherein the third transconductance stage includes a current mirror coupled to the first source degenerated transistor.

16. The circuit of claim 12, wherein the output transconductance stage includes an output, and the circuit further comprises a capacitor coupled to the output of the output transconductance stage. ​

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