A battery non-switch anti-spark protection method and circuit

Abstract

The present invention provides a battery non-switch anti-spark protection method and circuit. The method obtains the voltages of the main discharge circuit and the pre-discharge circuit of the battery; a comparison voltage is preset. When the battery is not installed, the voltages of both the main discharge circuit and the pre-discharge circuit are 0V, both of which are lower than the indicated comparison voltage. At this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit. When the battery is connected, when the voltage of the pre-discharge circuit increases to be greater than the comparison voltage, at this time, a high level is output to the main discharge circuit, and a low level is output to the pre-discharge circuit. When the battery-powered vehicle changes from riding to stationary, and there is no current in the main discharge circuit for a period of time, when the voltage of the main discharge circuit drops below the preset voltage, at this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit. The present invention uses a current detection resistor to distinguish the main discharge circuit and the pre-discharge circuit during discharge, avoiding the problem that the power supply generates sparks and causes damage to some devices.

Description

Technical Field

[0001] The present invention relates to the field of battery protection, and more specifically, to a battery non-switch anti-spark protection method and circuit. Background Art

[0002] Since electric vehicles need to frequently replace the battery, when replacing the battery, the large capacitor in the controller is charged. At the moment of charging, there will be a large current, thus forming a spark, which may damage some components.

[0003] A Chinese patent with a publication date of August 31, 2011 and a publication number of CN102170117A discloses a battery protection device, which includes that one output end of a charge and discharge control logic device is connected to the gate of a first MOS transistor, and the other output end is connected to the gate of a second MOS transistor; the source of the first MOS transistor is grounded, the drain is connected to the source of the second MOS transistor, and the drain of the second MOS transistor is connected to the negative pole of the discharge port; it also includes: a feedback end and a discharge control unit: one end of the discharge control unit is connected to the feedback end, and the other end is connected to the discharge port; the feedback end is used to obtain the feedback voltage when the battery is connected to the load; the discharge control unit is used to control the discharge switch transistor to conduct with a time delay and make the on-resistance of the discharge switch transistor change from large to small when the feedback voltage is obtained at the feedback section, so that the battery discharge current is applied to the load. However, this patent does not consider the main discharge circuit and the pre-discharge circuit of the electric vehicle. Summary of the Invention

[0004] The primary object of the present invention is to provide a battery non-switch anti-spark protection method, which can effectively avoid the problem that the connector part generates a spark when the power supply is connected to the capacitor on the vehicle, resulting in damage to some components.

[0005] The secondary object of the present invention is to provide a battery non-switch anti-spark protection circuit.

[0006] To solve the above technical problems, the technical solution of the present invention is as follows:

[0007] A battery non-switch anti-spark protection method includes the following steps:

[0008] Obtain the voltages of the main discharge circuit and the pre-discharge circuit of the battery;

[0009] Preset a comparison voltage and a judgment current;

[0010] When the battery is not installed, the voltages of the main discharge circuit and the pre-discharge circuit are both 0V, both lower than the comparison voltage. At this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit;

[0011] When the battery is connected, when the voltage of the pre-discharge circuit increases to be greater than the comparison voltage, at this time, a high level is output to the main discharge circuit, and a low level is output to the pre-discharge circuit;

[0012] When the battery is loaded on the vehicle and transitions from riding to stationary, and there is no main discharge circuit current for a period of time, when the voltage of the main discharge circuit drops below the preset voltage, a low level is output to the main discharge circuit and a high level is output to the pre-discharge circuit. After there is no main discharge circuit discharge current for a period of time, when it is detected that the pre-discharge circuit current is greater than the judgment current, the main discharge circuit is switched back, a high level is output to the main discharge circuit, and a low level is output to the pre-discharge circuit, and so on.

[0013] A battery non-switch anti-spark protection circuit is electrically connected to the main discharge circuit and the pre-discharge circuit of the battery, and includes a current detection resistor RN1 for detecting the main discharge circuit current, a current detection resistor RN2 for detecting the pre-discharge circuit current, a first comparison sub-circuit, a second comparison sub-circuit, a first delay sub-circuit, a second delay sub-circuit, a NAND gate sub-circuit, a first drive sub-circuit, and a second drive sub-circuit, wherein:

[0014] The input end of the first comparison sub-circuit is connected in parallel with the current detection resistor RN1, the output end of the first comparison sub-circuit is electrically connected to the input end of the first delay sub-circuit, and the output end of the first delay sub-circuit is electrically connected to the first input end of the NAND gate sub-circuit;

[0015] The input end of the second comparison sub-circuit is connected in parallel with the current detection resistor RN2, the output end of the second comparison sub-circuit is electrically connected to the input end of the second delay sub-circuit, and the output end of the second delay sub-circuit is electrically connected to the second input end of the NAND gate sub-circuit;

[0016] The output end of the NAND gate sub-circuit is electrically connected to the input end of the first drive sub-circuit and the input end of the second drive sub-circuit respectively;

[0017] The output end of the first drive sub-circuit is electrically connected to the gate of the drive NMOS transistor in the main discharge circuit, and the output end of the second drive sub-circuit is electrically connected to the gate of the drive NMOS transistor in the pre-discharge circuit.

[0018] Preferably, the first comparison sub-circuit includes an operational amplifier U4, a comparator U5, a resistor R22, a resistor R23, a resistor R24, a resistor R19, and a resistor R20, wherein:

[0019] One end of the resistor R22 is electrically connected to one end of the current detection resistor RN1, and the other end of the resistor R22 is electrically connected to one end of the resistor R24 and the inverting input end of the operational amplifier U4 respectively;

[0020] One end of the resistor R23 is electrically connected to the other end of the current detection resistor RN1, and the other end of the resistor R23 is electrically connected to the non-inverting input end of the operational amplifier U4;

[0021] The output terminal of the operational amplifier U4 is electrically connected to the other end of the resistor R24 and the inverting input terminal of the comparator U5 respectively;

[0022] The non-inverting input terminal of the comparator U5 is electrically connected to one end of the resistor R19 and one end of the resistor R20 respectively, and the output terminal of the comparator U5 is electrically connected to the input terminal of the first delay sub-circuit;

[0023] The negative power supply terminal of the comparator U5, the negative power supply terminal of the operational amplifier U4, and the other end of the resistor R20 are all grounded, and the positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R19 are connected to a 3.3V voltage.

[0024] Preferably, the second comparison sub-circuit includes an operational amplifier U1, a comparator U2, resistors R6, R7, R8, R3, R1, R2, and a capacitor C5, where:

[0025] One end of the resistor R6 is grounded, and the other end of the resistor R6 is electrically connected to one end of the resistor R8 and the inverting input terminal of the operational amplifier U1 respectively;

[0026] One end of the resistor R7 is electrically connected to one end of the current detection resistor RN2, and the other end of the resistor R7 is electrically connected to the non-inverting input terminal of the operational amplifier U1;

[0027] The output terminal of the operational amplifier U1 is electrically connected to the other end of the resistor R8 and one end of the resistor R3 respectively;

[0028] The other end of the resistor R3 is electrically connected to one end of the capacitor C5 and the inverting input terminal of the comparator U2 respectively. The non-inverting input terminal of the comparator U2 is electrically connected to one end of the resistor R1 and one end of the resistor R2 respectively. The output terminal of the comparator U2 is electrically connected to the input terminal of the second delay sub-circuit;

[0029] The negative power supply terminal of the operational amplifier U1, the negative power supply terminal of the comparator U2, the other end of the capacitor C5, and the other end of the resistor R2 are all grounded. The positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R1 are connected to a 3.3V voltage.

[0030] Preferably, the first delay sub-circuit includes a resistor R21, a capacitor C15, and a diode D1, where:

[0031] The output terminal of the first comparison sub-circuit is electrically connected to one end of the resistor R21 and the cathode of the diode D1 respectively. The other end of the resistor R21 is electrically connected to the anode of the diode D1, the first input terminal of the NAND gate sub-circuit, and one end of the capacitor C15 respectively. The other end of the capacitor C15 is grounded.

[0032] Preferably, the second delay sub - circuit includes a resistor R5, a resistor R9, and a capacitor C7, where:

[0033] One end of the resistor R5 is electrically connected to the output end of the second comparison sub - circuit, the other end of the resistor R5 is electrically connected to one end of the resistor R7, the other end of the resistor R7 is respectively electrically connected to the second input end of the NAND gate sub - circuit and one end of the capacitor C7, and the other end of the capacitor C7 is grounded.

[0034] Preferably, the NAND gate sub - circuit includes a diode D4, a diode D5, a resistor R10, a resistor R11, and an NMOS transistor M3, where:

[0035] The negative electrode of the diode D4 is electrically connected to the output end of the second delay sub - circuit, and the positive electrode of the diode D4 is respectively electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3;

[0036] The negative electrode of the diode D5 is electrically connected to the output end of the first delay sub - circuit, and the positive electrode of the diode D5 is respectively electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3;

[0037] The drain of the NMOS transistor M3 is respectively electrically connected to the input end of the first drive sub - circuit and the input end of the second drive sub - circuit;

[0038] The other end of the resistor R10 is connected to a 3.3V voltage;

[0039] The source of the NMOS transistor M3 is grounded;

[0040] One end of the resistor R11 is electrically connected to an 11V power supply, and the other end of the resistor R11 is respectively electrically connected to the first input end of the first drive sub - circuit and the input end of the second drive sub - circuit.

[0041] Preferably, the second drive sub - circuit includes a resistor R15, an NMOS transistor M4, a NAND gate U3A, and a NAND gate U3B, where:

[0042] The gate of the NMOS transistor M4 is respectively electrically connected to the other end of the resistor R11 and the output end of the NAND gate sub - circuit. The drain of the NMOS transistor M4 is respectively electrically connected to the first input end of the NAND gate U3A and one end of the resistor R15. The other end of the resistor R15 is connected to an 11V power supply. The second input end of the NAND gate U3A is connected to a discharge protection signal. The output end of the NAND gate U3A is respectively electrically connected to the first input end and the second input end of the NAND gate U3B. The output end of the NAND gate U3B outputs a drive voltage for driving the pre - discharge circuit.

[0043] The first driving sub-circuit includes NAND gates U3C and U3D, where:

[0044] The first input terminal of NAND gate U3C is electrically connected to the other end of resistor R11 and the output terminal of the NAND gate sub-circuit respectively. The second input terminal of NAND gate U3C receives the discharge protection signal. The output terminal of NAND gate U3C is electrically connected to the first input terminal and the second input terminal of NAND gate U3D respectively. The output terminal of NAND gate U3D outputs a driving voltage for driving the main discharge circuit.

[0045] Preferably, the second delay sub-circuit further includes NMOS transistor M1, NMOS transistor M2, resistor R12, resistor R18, resistor R4, diode D3, and capacitor C14, where:

[0046] The drain of NMOS transistor M1 is electrically connected to the output terminal of the second comparison sub-circuit. The gate of NMOS transistor M1 is electrically connected to one end of resistor R12, the gate of NMOS transistor M2, one end of resistor R18, one end of resistor R4, and the cathode of diode D3 respectively. The source of NMOS transistor M1 is electrically connected to the other end of resistor R12 and the source of NMOS transistor M2 respectively. The drain of NMOS transistor M2 is electrically connected to the other end of resistor R5.

[0047] The other end of resistor R14 is electrically connected to one end of capacitor C14. The other end of capacitor C14 is electrically connected to the output terminal of the second driving sub-circuit.

[0048] The other end of resistor R4 and the anode of diode D3 are both grounded.

[0049] Preferably, the first delay sub-circuit further includes resistor R14, resistor R13, diode D2, capacitor C1, and NMOS transistor M6, where:

[0050] The gate of NMOS transistor M6 is electrically connected to the other end of resistor R21, the cathode of diode D2, one end of resistor R14, and one end of resistor R13 respectively. The other end of resistor R13 is electrically connected to one end of capacitor C1. The other end of capacitor C1 is electrically connected to the output terminal of the first driving sub-circuit.

[0051] The source of NMOS transistor M6, the anode of diode D2, and the other end of resistor R14 are all grounded.

[0052] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0053] The present invention provides a method and a circuit for preventing ignition without a switch in a lithium battery, which are mainly applied in the field of electric vehicles. When discharging, a current detection resistor is used to distinguish the main discharge circuit and the pre-discharge circuit. Through the present invention, the problem that the plug-in part generates ignition when the power supply is connected to the capacitor on the vehicle, resulting in damage to some devices, can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a schematic flow chart of the method of the present invention.

[0055] Figure 2 It is a schematic circuit structure diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] The drawings are only for illustrative purposes and should not be construed as a limitation to this patent;

[0057] For better illustration of this embodiment, some components in the drawings are omitted, enlarged or reduced, which do not represent the dimensions of the actual product;

[0058] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0059] The technical solutions of the present invention will be further described below with reference to the drawings and embodiments.

[0060] Embodiment 1

[0061] This embodiment provides a method for preventing ignition and protecting a battery without a switch. As Figure 1 shown, it includes the following steps:

[0062] Obtain the voltages of the main discharge circuit and the pre-discharge circuit of the battery;

[0063] Preset a comparison voltage and a judgment current;

[0064] When the battery is not installed, the voltages of both the main discharge circuit and the pre-discharge circuit are 0V, both lower than the comparison voltage. At this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit;

[0065] When the battery is connected, the voltage of the pre-discharge circuit increases to be greater than the comparison voltage. At this time, a high level is output to the main discharge circuit, and a low level is output to the pre-discharge circuit;

[0066] When the battery is installed in the vehicle and switches from riding to stationary, and there is no current in the main discharge circuit for a period of time, when the voltage of the main discharge circuit drops below the preset voltage, a low level is output to the main discharge circuit and a high level is output to the pre-discharge circuit. After there is no discharge current in the main discharge circuit for a period of time, when it is detected that the current in the pre-discharge circuit is greater than the judgment current, switch back to the main discharge circuit, output a high level to the main discharge circuit, and output a low level to the pre-discharge circuit, and repeat this process.

[0067] Embodiment 2

[0068] This embodiment provides a battery non-switch anti-spark protection circuit, which is electrically connected to the main discharge circuit and the pre-discharge circuit of the battery, as Figure 2 shown, and includes a current detection resistor RN1 for detecting the current in the main discharge circuit, a current detection resistor RN2 for detecting the current in the pre-discharge circuit, a first comparison sub-circuit, a second comparison sub-circuit, a first delay sub-circuit, a second delay sub-circuit, a NAND gate sub-circuit, a first drive sub-circuit and a second drive sub-circuit, where:

[0069] The input end of the first comparison sub-circuit is connected in parallel with the current detection resistor RN1, the output end of the first comparison sub-circuit is electrically connected to the input end of the first delay sub-circuit, and the output end of the first delay sub-circuit is electrically connected to the first input end of the NAND gate sub-circuit;

[0070] The input end of the second comparison sub-circuit is connected in parallel with the current detection resistor RN2, the output end of the second comparison sub-circuit is electrically connected to the input end of the second delay sub-circuit, and the output end of the second delay sub-circuit is electrically connected to the second input end of the NAND gate sub-circuit;

[0071] The output end of the NAND gate sub-circuit is electrically connected to the input end of the first drive sub-circuit and the input end of the second drive sub-circuit respectively;

[0072] The output end of the first drive sub-circuit is electrically connected to the gate of the drive NMOS transistor in the main discharge circuit, and the output end of the second drive sub-circuit is electrically connected to the gate of the drive NMOS transistor in the pre-discharge circuit.

[0073] The first comparison sub-circuit includes an operational amplifier U4, a comparator U5, a resistor R22, a resistor R23, a resistor R24, a resistor R19 and a resistor R20, where:

[0074] One end of the resistor R22 is electrically connected to one end of the current detection resistor RN1, and the other end of the resistor R22 is electrically connected to one end of the resistor R24 and the inverting input end of the operational amplifier U4 respectively;

[0075] One end of the resistor R23 is electrically connected to the other end of the current detection resistor RN1, and the other end of the resistor R23 is electrically connected to the non-inverting input terminal of the operational amplifier U4;

[0076] The output terminal of the operational amplifier U4 is respectively electrically connected to the other end of the resistor R24 and the inverting input terminal of the comparator U5;

[0077] The non-inverting input terminal of the comparator U5 is respectively electrically connected to one end of the resistor R19 and one end of the resistor R20, and the output terminal of the comparator U5 is electrically connected to the input terminal of the first delay sub-circuit;

[0078] The negative power supply terminal of the comparator U5, the negative power supply terminal of the operational amplifier U4, and the other end of the resistor R20 are all grounded, and the positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R19 are connected to a 3.3V voltage.

[0079] The second comparison sub-circuit includes an operational amplifier U1, a comparator U2, resistors R6, R7, R8, R3, R1, R2, and a capacitor C5, where:

[0080] One end of the resistor R6 is grounded, and the other end of the resistor R6 is respectively electrically connected to one end of the resistor R8 and the inverting input terminal of the operational amplifier U1;

[0081] One end of the resistor R7 is electrically connected to one end of the current detection resistor RN2, and the other end of the resistor R7 is electrically connected to the non-inverting input terminal of the operational amplifier U1;

[0082] The output terminal of the operational amplifier U1 is respectively electrically connected to the other end of the resistor R8 and one end of the resistor R3;

[0083] The other end of the resistor R3 is respectively electrically connected to one end of the capacitor C5 and the inverting input terminal of the comparator U2. The non-inverting input terminal of the comparator U2 is respectively electrically connected to one end of the resistor R1 and one end of the resistor R2. The output terminal of the comparator U2 is electrically connected to the input terminal of the second delay sub-circuit;

[0084] The negative power supply terminal of the operational amplifier U1, the negative power supply terminal of the comparator U2, the other end of the capacitor C5, and the other end of the resistor R2 are all grounded. The positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R1 are connected to a 3.3V voltage.

[0085] The first delay sub-circuit includes a resistor R21, a capacitor C15, and a diode D1, where:

[0086] The output terminal of the first comparator circuit is electrically connected to one end of the resistor R21 and the cathode of the diode D1 respectively. The other end of the resistor R21 is electrically connected to the anode of the diode D1, the first input terminal of the NAND gate sub-circuit, and one end of the capacitor C15 respectively. The other end of the capacitor C15 is grounded.

[0087] The second delay sub-circuit includes a resistor R5, a resistor R9, and a capacitor C7, where:

[0088] One end of the resistor R5 is electrically connected to the output terminal of the second comparator circuit. The other end of the resistor R5 is electrically connected to one end of the resistor R7. The other end of the resistor R7 is electrically connected to the second input terminal of the NAND gate sub-circuit and one end of the capacitor C7 respectively. The other end of the capacitor C7 is grounded.

[0089] The NAND gate sub-circuit includes a diode D4, a diode D5, a resistor R10, a resistor R11, and an NMOS transistor M3, where:

[0090] The cathode of the diode D4 is electrically connected to the output terminal of the second delay sub-circuit. The anode of the diode D4 is electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3 respectively.

[0091] The cathode of the diode D5 is electrically connected to the output terminal of the first delay sub-circuit. The anode of the diode D5 is electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3 respectively.

[0092] The drain of the NMOS transistor M3 is electrically connected to the input terminal of the first drive sub-circuit and the input terminal of the second drive sub-circuit respectively.

[0093] The other end of the resistor R10 is connected to a 3.3V voltage.

[0094] The source of the NMOS transistor M3 is grounded.

[0095] One end of the resistor R11 is electrically connected to an 11V power supply. The other end of the resistor R11 is electrically connected to the first input terminal of the first drive sub-circuit and the input terminal of the second drive sub-circuit respectively.

[0096] The second drive sub-circuit includes a resistor R15, an NMOS transistor M4, a NAND gate U3A, and a NAND gate U3B, where:

[0097] The gate of NMOS transistor M4 is electrically connected to the other end of resistor R11 and the output end of the NAND gate sub-circuit respectively. The drain of NMOS transistor M4 is electrically connected to the first input end of NAND gate U3A and one end of resistor R15 respectively. The other end of resistor R15 is connected to the 11V power supply. The second input end of NAND gate U3A is connected to the discharge protection signal. The output end of NAND gate U3A is electrically connected to the first input end and the second input end of NAND gate U3B respectively. The output end of NAND gate U3B outputs a drive voltage for driving the pre-discharge circuit.

[0098] The first drive sub-circuit includes NAND gates U3C and U3D, where:

[0099] The first input end of NAND gate U3C is electrically connected to the other end of resistor R11 and the output end of the NAND gate sub-circuit respectively. The second input end of NAND gate U3C is connected to the discharge protection signal. The output end of NAND gate U3C is electrically connected to the first input end and the second input end of NAND gate U3D respectively. The output end of NAND gate U3D outputs a drive voltage for driving the main discharge circuit.

[0100] The second delay sub-circuit further includes NMOS transistor M1, NMOS transistor M2, resistor R12, resistor R18, resistor R4, diode D3 and capacitor C14, where:

[0101] The drain of NMOS transistor M1 is electrically connected to the output end of the second comparison sub-circuit. The gate of NMOS transistor M1 is electrically connected to one end of resistor R12, the gate of NMOS transistor M2, one end of resistor R18, one end of resistor R4 and the cathode of diode D3 respectively. The source of NMOS transistor M1 is electrically connected to the other end of resistor R12 and the source of NMOS transistor M2 respectively. The drain of NMOS transistor M2 is electrically connected to the other end of resistor R5.

[0102] The other end of resistor R14 is electrically connected to one end of capacitor C14. The other end of capacitor C14 is electrically connected to the output end of the second drive sub-circuit.

[0103] The other end of resistor R4 and the anode of diode D3 are both grounded.

[0104] The first delay sub-circuit further includes resistor R14, resistor R13, diode D2, capacitor C1 and NMOS transistor M6, where:

[0105] The gate of NMOS transistor M6 is electrically connected to the other end of resistor R21, the cathode of diode D2, one end of resistor R14 and one end of resistor R13 respectively. The other end of resistor R13 is electrically connected to one end of capacitor C1. The other end of capacitor C1 is electrically connected to the output end of the first drive sub-circuit.

[0106] The source of the NMOS transistor M6, the positive electrode of the diode D2, and the other end of the resistor R14 are all grounded.

[0107] In the specific implementation process, when the battery is not installed, the currents in the main discharge circuit and the pre-discharge circuit are both 0A, and the voltages across the current detection resistors RN1 and RN2 are both 0V. The current detected by the main discharge circuit is amplified by the operational amplifier U4 and then compared with the positive input terminal of the comparator U5. The comparison result (VD) is at a high level; the current detected by the pre-discharge circuit is amplified by the operational amplifier U1 and then compared with the positive input terminal of the comparator U2. The comparison result (VC) is at a high level. Both VE and VD are at high levels. The level of VA is determined by the default state - pulled up to 3.3V by the resistor R10, the NMOS transistor M3 is turned on, and VF outputs a low level, which is divided into two parts: for driving the main discharge circuit, after passing through the NAND gate U3C, it outputs a high level, and then after passing through the NAND gate U3D, it outputs a low level in reverse; for driving the pre-discharge circuit: after VF inputs a low level, it is given to the NMOS transistor M4, the NMOS transistor M4 is turned off, the first input terminal of the NAND gate U3A is pulled up, after passing through the NAND gate U3A, it outputs a low level, and then after passing through the NAND gate U3B in reverse, it outputs a high level. Therefore, the driving signal given to the NMOS transistor of the main discharge circuit is at a low level, and the driving voltage given to the pre-discharge circuit is at a high level. At this time, the driving NMOS transistor of the main discharge circuit is turned off, and the driving NMOS transistor of the pre-discharge circuit is turned on. At this time, only a small current is allowed to pass through the pre-discharge current.

[0108] When the battery is being installed in the vehicle, after connecting the battery, a small current in the pre-discharge circuit charges the controller capacitor. There is current in the pre-discharge circuit. Since only the pre-discharge circuit is turned on at this time, due to the limitation of R26, the current will not cause the connection terminals to spark. After about 100mS of delay through the resistor R5 and the capacitor C7, VE drops below 1V, changes from a high level to a low level, VA is pulled down, the NMOS transistor M3 is turned off, and the VF pin is pulled up to 11V, which is divided into two parts: the first drive sub-circuit outputs a high level after passing through two NAND gates (U3C, U3D); for the second drive sub-circuit, due to the high level of VF, the NMOS transistor M4 will be turned on, outputs a low level to the first input terminal of U3A, and then after passing through two NAND gates (U3A, U3B), it outputs a low level. Finally, the driving voltage given to the MOS of the main discharge circuit is at a high level, and the driving voltage given to the MOS of the pre-discharge circuit is at a low level. The driving NMOS transistor of the main discharge circuit is turned on, and the driving NMOS transistor of the pre-discharge circuit is turned off, realizing the transition from a small current to a large current. A small current in the pre-discharge circuit charges the controller capacitor to near full charge.

[0109] When in the riding state, if there is a current greater than or equal to the judgment current of the main discharge circuit, it is in a stable state. The driving NMOS transistor of the main discharge circuit is turned on, and the driving NMOS transistor of the pre-discharge circuit is turned off.

[0110] When the battery is installed in the vehicle and the state changes from riding to stationary, the voltage across the current detection resistor RN1 drops below the judgment current of the main discharge circuit. The voltage detected by the main discharge circuit outputs a high level after passing through the comparator U5, charges the capacitor C5 through the resistor R21. After a delay, VD changes from low level to high level. The voltage detected by the pre-discharge circuit outputs a high level after passing through the comparator U2 (VC). The level of VA is determined by its default state - pulled up to 3.3V by the resistor R10, the NMOS transistor M3 conducts, and VF outputs a low level, which is divided into two parts: the first drive sub-circuit outputs a high level after passing through the NAND gate U3C and then outputs a low level after being inverted by the NAND gate U3D; the second drive sub-circuit, after VF inputs a low level, supplies it to the NMOS transistor M4, the NMOS transistor M4 is cut off, the first input terminal of the NAND gate U3A is pulled up, outputs a low level after passing through the NAND gates U3A and U3B, and then outputs a high level after being inverted by the NAND gate U3B. Therefore, the drive voltage supplied to the main discharge circuit is at a low level, and the drive voltage supplied to the pre-discharge circuit is at a high level, turning the drive NMOS transistor of the main discharge circuit off and the drive NMOS transistor of the pre-discharge circuit on. However, this state is unstable. After turning the main discharge MOS off and the pre-discharge MOS on, if it is detected that the current in the pre-discharge circuit is greater than the pre-discharge judgment current value, VE will flip to a low level, then the NMOS transistors M1 and M2 will conduct briefly, VA will immediately flip to a low level, and it will return to the state where the drive NMOS transistor of the main discharge circuit is on and the drive NMOS transistor of the pre-discharge circuit is off. This process repeats.

[0111] When on standby in the vehicle, the main discharge MOS is on for 10S and off for 1mS.

[0112] The pre-discharge judgment current is designed to be less than the standby current in the vehicle.

[0113] Then the functions of the M1 and M2 circuits are as follows: when changing from riding to standby in the vehicle and switching to the pre-discharge on state, if the current in the pre-discharge circuit is detected, it will switch back to the main discharge MOS on state after a delay of about 1mS, preventing power-off of the vehicle when changing from standby to riding during the standby process in the vehicle.

[0114] When the battery is removed from the vehicle, the currents in both discharge circuits are 0, and VA is at a high level. The pre-discharge MOS is turned on and the main discharge MOS is turned off.

[0115] Identical or similar reference numerals correspond to identical or similar components;

[0116] The terms describing the positional relationship in the drawings are for illustrative purposes only and should not be construed as a limitation of this patent;

[0117] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A battery non-switch anti-spark protection method, characterized in that, The protection method is applied to a battery non-switch anti-spark protection circuit. The protection circuit is electrically connected to the main discharge circuit and the pre-discharge circuit of the battery, and includes a current detection resistor RN1 for detecting the current of the main discharge circuit, a current detection resistor RN2 for detecting the current of the pre-discharge circuit, a first comparator sub-circuit, a second comparator sub-circuit, a first delay sub-circuit, a second delay sub-circuit, a NAND gate sub-circuit, a first driver sub-circuit, and a second driver sub-circuit, where: The input end of the first comparator sub-circuit is connected in parallel with the current detection resistor RN1, the output end of the first comparator sub-circuit is electrically connected to the input end of the first delay sub-circuit, and the output end of the first delay sub-circuit is electrically connected to the first input end of the NAND gate sub-circuit; The input end of the second comparator sub-circuit is connected in parallel with the current detection resistor RN2, the output end of the second comparator sub-circuit is electrically connected to the input end of the second delay sub-circuit, and the output end of the second delay sub-circuit is electrically connected to the second input end of the NAND gate sub-circuit; The output end of the NAND gate sub-circuit is electrically connected to the input end of the first driver sub-circuit and the input end of the second driver sub-circuit respectively; The output end of the first driver sub-circuit is electrically connected to the gate of the driving NMOS transistor in the main discharge circuit, and the output end of the second driver sub-circuit is electrically connected to the gate of the driving NMOS transistor in the pre-discharge circuit The protection method includes the following steps: Obtain the voltages of the main discharge circuit and the pre-discharge circuit of the battery; Preset a comparison voltage and a judgment current; When the battery is not installed, the voltages of the main discharge circuit and the pre-discharge circuit are both 0V, both lower than the comparison voltage. At this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit; When the battery is connected, when the voltage of the pre-discharge circuit increases to be greater than the comparison voltage, at this time, a high level is output to the main discharge circuit, and a low level is output to the pre-discharge circuit; When the battery is in the process of changing from riding to stationary after being installed on the vehicle, when there is no current in the main discharge circuit for a period of time, and the voltage of the main discharge circuit drops to be lower than the comparison voltage, at this time, a low level is output to the main discharge circuit, and a high level is output to the pre-discharge circuit. When there is no discharge current in the main discharge circuit for a period of time, and it is detected that the current of the pre-discharge circuit is greater than the judgment current, switch back to the main discharge circuit, output a high level to the main discharge circuit, and output a low level to the pre-discharge circuit, and so on.

2. The battery non-switch anti-spark protection method according to claim 1, characterized in that, The first comparator sub-circuit includes an operational amplifier U4, a comparator U5, a resistor R22, a resistor R23, a resistor R24, a resistor R19, and a resistor R20, where: One end of the resistor R22 is electrically connected to one end of the current detection resistor RN1, and the other end of the resistor R22 is electrically connected to one end of the resistor R24 and the inverting input end of the operational amplifier U4 respectively; One end of the resistor R23 is electrically connected to the other end of the current detection resistor RN1, and the other end of the resistor R23 is electrically connected to the non-inverting input end of the operational amplifier U4; The output end of the operational amplifier U4 is electrically connected to the other end of the resistor R24 and the inverting input end of the comparator U5 respectively; The non-inverting input terminal of the comparator U5 is electrically connected to one end of the resistor R19 and one end of the resistor R20 respectively, and the output terminal of the comparator U5 is electrically connected to the input terminal of the first delay sub-circuit; The negative power supply terminal of the comparator U5, the negative power supply terminal of the operational amplifier U4, and the other end of the resistor R20 are all grounded, and the positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R19 are connected to a 3.3V voltage.

3. The battery non-switch anti-spark protection method according to claim 2, characterized in that, The second comparison sub-circuit includes an operational amplifier U1, a comparator U2, a resistor R6, a resistor R7, a resistor R8, a resistor R3, a resistor R1, a resistor R2, and a capacitor C5, where: One end of the resistor R6 is grounded, and the other end of the resistor R6 is electrically connected to one end of the resistor R8 and the inverting input terminal of the operational amplifier U1 respectively; One end of the resistor R7 is electrically connected to one end of the current detection resistor RN2, and the other end of the resistor R7 is electrically connected to the non-inverting input terminal of the operational amplifier U1; The output terminal of the operational amplifier U1 is electrically connected to the other end of the resistor R8 and one end of the resistor R3 respectively; The other end of the resistor R3 is electrically connected to one end of the capacitor C5 and the inverting input terminal of the comparator U2 respectively. The non-inverting input terminal of the comparator U2 is electrically connected to one end of the resistor R1 and one end of the resistor R2 respectively. The output terminal of the comparator U2 is electrically connected to the input terminal of the second delay sub-circuit; The negative power supply terminal of the operational amplifier U1, the negative power supply terminal of the comparator U2, the other end of the capacitor C5, and the other end of the resistor R2 are all grounded. The positive power supply terminal of the comparator U5, the positive power supply terminal of the operational amplifier U4, and the other end of the resistor R1 are connected to a 3.3V voltage.

4. The battery non-switch anti-spark protection method according to claim 3, wherein The first delay sub-circuit includes a resistor R21, a capacitor C15, and a diode D1, where: The output terminal of the first comparison sub-circuit is electrically connected to one end of the resistor R21 and the cathode of the diode D1 respectively. The other end of the resistor R21 is electrically connected to the anode of the diode D1, the first input terminal of the NAND gate sub-circuit, and one end of the capacitor C15 respectively. The other end of the capacitor C15 is grounded.

5. The battery non-switch anti-spark protection method according to claim 4, wherein, The second delay sub-circuit includes a resistor R5, a resistor R9, and a capacitor C7, where: One end of the resistor R5 is electrically connected to the output terminal of the second comparison sub-circuit, the other end of the resistor R5 is electrically connected to one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the second input terminal of the NAND gate sub-circuit and one end of the capacitor C7 respectively. The other end of the capacitor C7 is grounded.

6. The battery non-switch anti-spark protection method according to claim 5, wherein The NAND gate sub-circuit includes a diode D4, a diode D5, a resistor R10, a resistor R11, and an NMOS transistor M3, where: The cathode of the diode D4 is electrically connected to the output terminal of the second delay sub-circuit, and the anode of the diode D4 is electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3 respectively; The cathode of the diode D5 is electrically connected to the output terminal of the first delay sub-circuit, and the anode of the diode D5 is electrically connected to one end of the resistor R10 and the gate of the NMOS transistor M3 respectively; The drain of NMOS transistor M3 is electrically connected to the input terminal of the first driving sub-circuit and the input terminal of the second driving sub-circuit respectively; The other end of resistor R10 is connected to a 3.3V voltage; The source of NMOS transistor M3 is grounded; One end of resistor R11 is electrically connected to an 11V power supply, and the other end of resistor R11 is electrically connected to the first input terminal of the first driving sub-circuit and the input terminal of the second driving sub-circuit respectively.

7. The battery non-switch anti-spark protection method according to claim 6, wherein The second driving sub-circuit includes resistor R15, NMOS transistor M4, NAND gate U3A and NAND gate U3B, where: The gate of NMOS transistor M4 is electrically connected to the other end of resistor R11 and the output terminal of the NAND gate sub-circuit respectively. The drain of NMOS transistor M4 is electrically connected to the first input terminal of NAND gate U3A and one end of resistor R15 respectively. The other end of resistor R15 is connected to an 11V power supply. The second input terminal of NAND gate U3A is connected to a discharge protection signal. The output terminal of NAND gate U3A is electrically connected to the first input terminal and the second input terminal of NAND gate U3B respectively. The output terminal of NAND gate U3B outputs a driving voltage for driving the pre-discharge circuit; The first driving sub-circuit includes NAND gate U3C and NAND gate U3D, where: The first input terminal of NAND gate U3C is electrically connected to the other end of resistor R11 and the output terminal of the NAND gate sub-circuit respectively. The second input terminal of NAND gate U3C is connected to a discharge protection signal. The output terminal of NAND gate U3C is electrically connected to the first input terminal and the second input terminal of NAND gate U3D respectively. The output terminal of NAND gate U3D outputs a driving voltage for driving the main discharge circuit.

8. The battery non-switch anti-spark protection method according to claim 7, wherein The second delay sub-circuit further includes NMOS transistor M1, NMOS transistor M2, resistor R12, resistor R18, resistor R4, diode D3 and capacitor C14, where: The drain of NMOS transistor M1 is electrically connected to the output terminal of the second comparison sub-circuit. The gate of NMOS transistor M1 is electrically connected to one end of resistor R12, the gate of NMOS transistor M2, one end of resistor R18, one end of resistor R4 and the cathode of diode D3 respectively. The source of NMOS transistor M1 is electrically connected to the other end of resistor R12 and the source of NMOS transistor M2 respectively. The drain of NMOS transistor M2 is electrically connected to the other end of resistor R5; The other end of resistor R14 is electrically connected to one end of capacitor C14, and the other end of capacitor C14 is electrically connected to the output terminal of the second driving sub-circuit; The other end of resistor R4 and the anode of diode D3 are both grounded.

9. The battery non-switch anti-spark protection method according to claim 8, characterized in that, The first delay sub-circuit further includes resistor R14, resistor R13, diode D2, capacitor C1 and NMOS transistor M6, where: The gate of NMOS transistor M6 is electrically connected to the other end of resistor R21, the cathode of diode D2, one end of resistor R14 and one end of resistor R13 respectively. The other end of resistor R13 is electrically connected to one end of capacitor C1, and the other end of capacitor C1 is electrically connected to the output terminal of the first driving sub-circuit; The source of NMOS transistor M6, the anode of diode D2 and the other end of resistor R14 are all grounded.

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