An ultra-low power supply voltage detection circuit

Abstract

The present disclosure relates to an ultra-low power supply voltage detection circuit, comprising: a reference voltage circuit, the reference voltage circuit being connected to a power supply voltage to be measured, the reference voltage circuit being used to output a reference voltage; wherein the reference voltage is independent of the power supply voltage to be measured and the temperature of the environment in which the ultra-low power supply voltage detection circuit is located; a voltage detection circuit, the voltage detection circuit comprising a pull-up voltage-controlled current source and a pull-down constant current source, the pull-up voltage-controlled current source being connected to the power supply voltage to be measured, the pull-down constant current source being connected to the reference voltage, the voltage detection circuit being used to detect the power supply voltage to be measured based on the reference voltage; wherein the output voltage of the voltage detection circuit is consistent with the power supply voltage to be measured when the power supply voltage to be measured rises to a preset value. Through the technical solution disclosed in the present disclosure, voltage value detection of an ultra-low power supply voltage is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of microelectronics technology, and in particular to an ultra-low power supply voltage detection circuit. Background Art

[0002] Ultra-low voltage power supply voltage detection circuits are extremely common in various scenarios that require low-voltage startup. Ultra-low voltage power supply voltage detection circuits are used to detect the power supply voltage status and assist subsequent circuits in completing startup.

[0003] Commonly used low-power supply voltage detection circuits often require a reference voltage source to provide a reference voltage. These circuits also require a low-voltage comparator, which in turn requires a reference current source to provide bias. However, when the power supply voltage is low, for example, below 0.4V, the reference voltage source and current source have difficulty operating, making it impossible to detect ultra-low power supply voltages. Therefore, developing a power supply voltage detection circuit capable of operating at ultra-low power supply voltages has become a pressing issue. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides an ultra-low power supply voltage detection circuit, which realizes the voltage value detection of the ultra-low power supply voltage.

[0005] The present disclosure provides an ultra-low power supply voltage detection circuit, comprising:

[0006] a reference voltage circuit, the reference voltage circuit being connected to the power supply voltage to be measured and configured to output a reference voltage; wherein the reference voltage is independent of the power supply voltage to be measured and the temperature of the environment in which the ultra-low power supply voltage detection circuit is located;

[0007] A voltage detection circuit, wherein the voltage detection circuit includes a pull-up voltage-controlled current source and a pull-down constant current source, the pull-up voltage-controlled current source is connected to the power supply voltage to be measured, and the pull-down constant current source is connected to the reference voltage, and the voltage detection circuit is used to detect the power supply voltage to be measured based on the reference voltage; wherein the output voltage of the voltage detection circuit is consistent with the power supply voltage to be measured when the power supply voltage to be measured rises to a preset value.

[0008] Optionally, the reference voltage circuit includes:

[0009] a voltage stabilizing circuit, a gate voltage generating circuit, a substrate voltage generating circuit, and a reference generating circuit, wherein the voltage stabilizing circuit is electrically connected to the gate voltage generating circuit, the substrate voltage generating circuit, and the reference generating circuit, respectively, and the reference generating circuit is electrically connected to the gate voltage generating circuit and the substrate voltage generating circuit, respectively;

[0010] The voltage stabilizing circuit is connected to the power supply voltage to be measured and is used to output an internal power supply voltage to the gate voltage generating circuit, the substrate voltage generating circuit and the reference generating circuit; wherein the internal power supply voltage is independent of the power supply voltage to be measured;

[0011] The reference generating circuit is used to output the reference voltage according to the gate voltage output by the gate voltage generating circuit and the substrate voltage output by the substrate voltage generating circuit.

[0012] Optionally, the voltage stabilizing circuit includes:

[0013] a first N-type transistor, wherein a gate of the first N-type transistor is electrically connected to a source of the first N-type transistor, a drain of the first N-type transistor is connected to the power supply voltage to be measured, and a substrate of the first N-type transistor is grounded;

[0014] a first P-type transistor, wherein the gate and drain of the first P-type transistor are grounded, and the source of the first P-type transistor is electrically connected to the substrate of the first P-type transistor and the source of the first N-type transistor and outputs the internal power supply voltage. Optionally, the gate voltage generating circuit includes:

[0015] a second P-type transistor, wherein a gate of the second P-type transistor is electrically connected to a drain of the second P-type transistor, and a substrate of the second P-type transistor is electrically connected to a source of the second P-type transistor and is connected to the internal power supply voltage;

[0016] A second N-type transistor, wherein the gate, source and substrate of the second N-type transistor are all grounded, and the drain of the second N-type transistor is electrically connected to the drain of the second P-type transistor and outputs the gate voltage.

[0017] Optionally, the liner voltage generating circuit includes:

[0018] a third P-type transistor, wherein a gate of the third P-type transistor is electrically connected to a drain of the third P-type transistor, and a substrate of the third P-type transistor is electrically connected to a source of the third P-type transistor and is connected to the internal power supply voltage;

[0019] A third N-type transistor, wherein the gate, source and substrate of the third N-type transistor are grounded, and the drain of the third N-type transistor is electrically connected to the drain of the third P-type transistor and outputs the substrate voltage.

[0020] Optionally, the reference generation circuit includes:

[0021] a fourth P-type transistor, wherein a gate of the fourth P-type transistor is connected to the gate voltage, a source of the fourth P-type transistor is connected to the internal power supply voltage, and a substrate of the fourth P-type transistor is connected to the substrate voltage;

[0022] A fourth N-type transistor, wherein the gate of the fourth N-type transistor, the drain of the fourth N-type transistor and the drain of the fourth P-type transistor are electrically connected and output the reference voltage, and the source of the fourth N-type transistor and the substrate of the fourth N-type transistor are grounded.

[0023] Optionally, the voltage detection circuit includes:

[0024] a fifth P-type transistor, wherein the gate of the fifth P-type transistor is grounded, and the source of the fifth P-type transistor is electrically connected to the substrate of the fifth P-type transistor and connected to the power supply voltage to be measured; wherein the fifth P-type transistor constitutes the pull-up voltage-controlled current source;

[0025] a fifth N-type transistor, wherein the gate of the fifth N-type transistor is connected to the reference voltage, the source of the fifth N-type transistor and the substrate of the fifth N-type transistor are grounded, and the drain of the fifth N-type transistor is electrically connected to the drain of the fifth P-type transistor and serves as the output end of the voltage detection circuit; wherein the fifth N-type transistor constitutes the pull-down constant current source.

[0026] Optionally, the relationship between the reference voltage and the temperature is related to the sizes of transistors in the gate voltage generating circuit and the reference generating circuit.

[0027] Optionally, the transistors included in the reference voltage circuit and the voltage detection circuit are both transistors using a standard CMOS process.

[0028] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0029] The disclosed embodiment provides an ultra-low power supply voltage detection circuit including a reference voltage circuit, the reference voltage circuit being connected to a power supply voltage to be tested, the reference voltage circuit being used to output a reference voltage; wherein the reference voltage is independent of the power supply voltage to be tested and the temperature of the environment in which the ultra-low power supply voltage detection circuit is located; and a voltage detection circuit, the voltage detection circuit including a pull-up voltage-controlled current source and a pull-down constant current source, the pull-up voltage-controlled current source being connected to the power supply voltage to be tested, the pull-down constant current source being connected to the reference voltage, the voltage detection circuit being used to detect the power supply voltage to be tested based on the reference voltage; wherein the output voltage of the voltage detection circuit is consistent with the power supply voltage to be tested when the power supply voltage to be tested rises to a preset value. Thus, the disclosed embodiment achieves detection of an ultra-low power supply voltage value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0031] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 A schematic diagram of the structure of an ultra-low power supply voltage detection circuit provided by an embodiment of the present disclosure;

[0033] Figure 2 A simulation diagram showing how the reference voltage and output voltage of an ultra-low power supply voltage detection circuit vary with the power supply voltage to be tested, provided in an embodiment of the present disclosure;

[0034] Figure 3 A schematic diagram of a specific circuit structure of an ultra-low power supply voltage detection circuit provided by an embodiment of the present disclosure;

[0035] Figure 4 A simulation diagram showing how the reference voltage of an ultra-low power supply voltage detection circuit varies with the power supply voltage to be measured, provided by an embodiment of the present disclosure;

[0036] Figure 5 This is a simulation diagram showing how the reference voltage of an ultra-low power supply voltage detection circuit varies with temperature, provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0039] Figure 1 This is a schematic diagram of the structure of an ultra-low power supply voltage detection circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the ultra-low power supply voltage detection circuit includes a reference voltage circuit 1, which is connected to the power supply voltage V to be tested. DD , the reference voltage circuit 1 is used to output the reference voltage V REF ; Among them, the reference voltage V REFand the power supply voltage V DD And it is independent of the temperature of the environment in which the ultra-low power supply voltage detection circuit is located.

[0040] Specifically, if Figure 1 As shown, the ultra-low power supply voltage detection circuit includes a reference voltage circuit 1, the reference voltage circuit 1 and the power supply voltage to be measured V DD The reference voltage V output by the reference voltage circuit 1 is electrically connected to REF Does not change with the power supply voltage V DD and the temperature of the environment in which the ultra-low power supply voltage detection circuit is located.

[0041] The ultra-low power supply voltage detection circuit also includes a voltage detection circuit 2, which includes a pull-up voltage-controlled current source 21 and a pull-down constant current source 22. The pull-up voltage-controlled current source 21 is connected to the power supply voltage V to be tested. DD , pull down constant current source 11 to access reference voltage V REF , the voltage detection circuit 2 is used to detect the reference voltage V REF Realize the power supply voltage V DD Detection; wherein the output voltage V of the voltage detection circuit 2 OUT At the power supply voltage V DD When it rises to the preset value, it is equal to the power supply voltage V DD consistent.

[0042] Specifically, if Figure 1 As shown, the temperature of the environment where the ultra-low power supply voltage detection circuit is located and the power supply voltage to be measured V DD Approximately unrelated reference voltage V REF The pull-down constant current source 22 inputted into the voltage detection circuit 2 enables it to realize the constant current source function. The pull-up voltage-controlled current source 21 can be regarded as a voltage source to be measured. DD The controlled voltage-controlled current source, the pull-up voltage-controlled current source 21 and the pull-down constant current source 22 can constitute a current comparator.

[0043] Figure 2 This is a simulation diagram showing how the reference voltage and output voltage of an ultra-low power supply voltage detection circuit provided by an embodiment of the present disclosure vary with the power supply voltage to be tested. Figure 2 The horizontal axis represents the power supply voltage V to be measured DD The size of the unit is V, the vertical axis represents the reference voltage V REF and the output voltage V OUT The size of is in V. Figure 2 As shown, at the beginning, the power supply voltage to be measured is V DD The pull-up capability of the pull-up voltage-controlled current source 21 is weaker than the pull-down capability of the pull-down constant current source 22. The output voltage V OUTThe output is low level. Corresponding to the coordinates of turning point A in the figure (250mV, 30.6661mV), when the power supply voltage V DD When gradually increasing to a preset value, the preset value can be, for example, Figure 2 As shown, the output voltage V of the voltage detection circuit 2 is equal to 250mV. OUT and the power supply voltage V DD Synchronous change, that is, the output voltage V of the voltage detection circuit 2 OUT Follow the power supply voltage to be measured V DD Change output high level.

[0044] Therefore, by reasonably setting the sizes of the transistors in the pull-up voltage-controlled current source 21 and the pull-down constant current source 22 so that they have different pull-down and pull-up capabilities, the required power supply voltage V to be tested can be set. DD Detection node to measure the power supply voltage V DD Pull down to realize the function of ultra-low power supply voltage detection, and because the output voltage V OUT At the power supply voltage V DD When it rises to the preset value, it is equal to the power supply voltage V DD Consistent, by the output voltage V OUT The detection of ultra-low power supply voltage V DD Detection function.

[0045] It should be noted that the preset value is set to the minimum voltage value that can be detected by the ultra-low power supply voltage detection circuit. Figure 2 The simulation results shown are only illustrated by taking 250mV as the preset value as an example. The preset value may also vary according to the specific detection circuit and simulation software, and the embodiments of the present disclosure are not limited to this.

[0046] The ultra-low power supply voltage detection circuit provided by the embodiment of the present disclosure includes a reference voltage circuit 1, the reference voltage circuit 1 is connected to the power supply voltage V to be tested. DD , the reference voltage circuit 1 is used to output the reference voltage V REF ; Among them, the reference voltage V REF and the power supply voltage V DD The ultra-low power supply voltage detection circuit is independent of the temperature T of the environment in which the ultra-low power supply voltage detection circuit is located; the ultra-low power supply voltage detection circuit also includes a voltage detection circuit 2, including a pull-up voltage-controlled current source 21 and a pull-down constant current source 22, the pull-up voltage-controlled current source 21 is connected to the power supply voltage to be tested V DD , pull down constant current source 11 to access reference voltage V REF , the voltage detection circuit 2 is used to detect the reference voltage V REF Realize the power supply voltage V DD Detection; wherein the output voltage V of the voltage detection circuit 2 OUTAt the power supply voltage V DD When it rises to the preset value, it is equal to the power supply voltage V DD Therefore, the embodiment of the present disclosure realizes the detection of the voltage value of the ultra-low power supply voltage circuit.

[0047] Alternatively, as Figure 1 As shown, the reference voltage circuit 1 includes: a voltage stabilizing circuit 101, a gate voltage generating circuit 102, a substrate voltage generating circuit 103 and a reference generating circuit 104. The voltage stabilizing circuit 101 is electrically connected to the gate voltage generating circuit 102, the substrate voltage generating circuit 103 and the reference generating circuit 104 respectively, and the reference generating circuit 104 is electrically connected to the gate voltage generating circuit 102 and the substrate voltage generating circuit 103 respectively; the voltage stabilizing circuit 101 is connected to the power supply voltage V to be measured DD And used to output the internal power supply voltage V DDI To the gate voltage generating circuit 102, the substrate voltage generating circuit 103 and the reference generating circuit 104; wherein the internal power supply voltage V DDI and the power supply voltage V DD The reference generating circuit 104 is used to generate the gate voltage V according to the gate voltage generating circuit 102 output G and the substrate voltage V output by the substrate voltage generating circuit 103 B Output reference voltage V REF .

[0048] Specifically, if Figure 1 As shown, the voltage stabilizing circuit 101 is able to maintain the output internal power supply voltage V when the input grid voltage fluctuates or the load changes. DDI The voltage stabilizing circuit 101 is electrically connected to the gate voltage generating circuit 102, the substrate voltage generating circuit 103 and the reference generating circuit 104 respectively. The reference generating circuit 104 is electrically connected to the gate voltage generating circuit 102 and the substrate voltage generating circuit 103 respectively. The voltage stabilizing circuit 101 is connected to the power supply voltage V DD And used to output the internal power supply voltage V DDI To the gate voltage generating circuit 102, the substrate voltage generating circuit 103 and the reference generating circuit 104, the internal power supply voltage V DDI Does not change with the power supply voltage V DD changes with the changes of .

[0049] The reference generation circuit 104 is used to generate a gate voltage V according to the gate voltage output by the gate voltage generation circuit 102. G and the substrate voltage V output by the substrate voltage generating circuit 103 B Output reference voltage V REF , where the gate voltage V G It is the working voltage required by the gate when the transistor is working. The gate is a mesh or spiral electrode composed of metal filaments. The substrate voltage V BThe voltage required for the electrodes drawn from the substrate to work is the working voltage. The substrate can be divided into P-type Si substrate and N-type Si substrate according to the different channels. Therefore, the output of the voltage regulator circuit 101 is used as the internal power supply V DDI Powering the reference ensures that the reference voltage V REF Does not change with the power supply voltage V DD Change and change.

[0050] Figure 3 This is a schematic diagram of a specific circuit structure of an ultra-low power supply voltage detection circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the voltage stabilizing circuit 101 includes: a first N-type transistor NM1, the gate of the first N-type transistor NM1 is electrically connected to the source of the first N-type transistor NM1, and the drain of the first N-type transistor NM1 is connected to the power supply voltage V to be measured. DD , the substrate of the first N-type transistor NM1 is grounded; the first P-type transistor PM1, the gate of the first P-type transistor PM1 and the drain of the first P-type transistor PM1 are grounded, the source of the first P-type transistor PM1 is electrically connected to the substrate of the first P-type transistor PM1 and the source of the first N-type transistor NM1 and outputs the internal power supply voltage V DDI .in addition, Figure 3 The upper end of the first N-type transistor NM1 is its drain, and the upper end of the first P-type transistor PM1 is its source.

[0051] Specifically, an N-type transistor is a transistor with an N-type metal oxide semiconductor structure, namely an NMOS (Negative channel-Metal-Oxide-Semiconductor) transistor. The transistor has three polarities, namely, a gate, a drain and a source. For example, a large number of holes are provided on a P-type silicon substrate with a low doping concentration, and two high-doping concentration N+ regions are made to provide an electron source of free electrons for the flow of current. Two electrodes are drawn out with metal aluminum as the drain and the source respectively, and then a very thin silicon dioxide insulating layer is covered on the surface of the semiconductor. An aluminum electrode is installed on the insulating layer between the drain and the source as the gate, and an electrode is also drawn out on the substrate to form an N-type transistor. Figure 3 As shown, the voltage stabilizing circuit 101 includes a first N-type transistor NM1, the gate of the first N-type transistor NM1 is electrically connected to the source of the first N-type transistor NM1, and the drain of the first N-type transistor NM1 is connected to the power supply voltage V to be measured. DD , an electrode extending from the substrate of the first N-type transistor NM1 is grounded.

[0052] The voltage stabilization circuit 101 also includes a first P-type transistor PM1. The P-type transistor is a transistor having a P-type metal oxide semiconductor structure, namely a PMOS (Positive channel-metal-oxide-semiconductor) transistor. For example, a large number of holes are provided on a low-doping N-type silicon substrate, and two high-doping P+ regions are formed to provide an electron source for free electrons for current flow. Two electrodes are drawn out of metal aluminum to serve as the drain and source, respectively. A very thin silicon dioxide insulating layer is then coated on the semiconductor surface. An aluminum electrode, serving as the gate, is installed on the insulating layer between the drain and source. An electrode is also drawn out on the substrate, thus forming a P-type transistor. The gate and drain of the first P-type transistor PM1 are grounded, and the source of the first P-type transistor PM1 is electrically connected to the substrate of the first P-type transistor PM1 and the source of the first N-type transistor NM1, and outputs the internal power supply voltage V DDI .

[0053] For example, the voltage stabilizing circuit 101 includes a first P-type transistor PM1 connected in series with a voltage regulator diode, and a voltage V between the source and the gate. GS The first N-type transistor NM1 is equal to 0, realizing the voltage stabilization function. The first P-type transistor PM1 connected in a Zener diode manner has a function similar to that of a Zener diode. It utilizes the reverse breakdown state of the PN junction. When the reverse voltage is greater than the breakdown voltage, the current flowing through the first P-type transistor PM1 can vary within a wide range while the voltage remains basically unchanged. When the source voltage of the first P-type transistor PM1 does not reach the turn-on voltage, the current of the first P-type transistor PM1 is zero and is in the cut-off state; when the source voltage of the first P-type transistor PM1 reaches the turn-on voltage, it works as a voltage stabilizing device with the conduction characteristics of a Zener diode, the first P-type transistor PM1 is broken down, and the source voltage of the first P-type transistor PM1 changes with the power supply voltage V to be measured. DD The internal power supply voltage V output by the voltage stabilizing circuit 101 is approximately unchanged. DDI Powering the reference voltage circuit 1 ensures that the reference voltage V output by the reference voltage circuit 1 is REF Does not change with the power supply voltage V DD Thus, the voltage stabilizing circuit 101 reduces the power supply voltage V DD For reference voltage V REF impact.

[0054] Figure 4 This is a simulation diagram showing how the reference voltage of an ultra-low power supply voltage detection circuit varies with the power supply voltage to be measured, provided by an embodiment of the present disclosure. Figure 4 The horizontal axis represents the power supply voltage V to be measured DDThe size of the unit is V, the vertical axis represents the reference voltage V REF The unit is mV. Figure 4 As shown, refer to Figure 4 The coordinates of point B and point C, under the condition of maintaining room temperature at 300K, the power supply voltage to be measured V DD In the process of changing from 250mV to 1.8V, the reference voltage V REF From 80.3952mV to 81.8155mV, the reference voltage V REF It changes by 1.42mV, and the rate of change is only 1.76%. It can be seen that the reference voltage V REF Basically not affected by the power supply voltage V DD changes with the changes of .

[0055] Alternatively, as Figure 3 As shown, the reference generation circuit 104 includes: a fourth P-type transistor PM4, the gate of the fourth P-type transistor PM4 is connected to the gate voltage V G , the source of the fourth P-type transistor PM4 is connected to the internal power supply voltage V DDI , the substrate of the fourth P-type transistor PM4 is connected to the substrate voltage V B A fourth N-type transistor NM4, a gate of the fourth N-type transistor NM4, a drain of the fourth N-type transistor NM4 and a drain of the fourth P-type transistor PM4 are electrically connected and output a reference voltage V REF , the source of the fourth N-type transistor NM4 and the substrate of the fourth N-type transistor NM4 are grounded. In addition, Figure 3 The upper end of the fourth N-type transistor NM4 is its drain, and the upper end of the fourth P-type transistor PM4 is its source.

[0056] Specifically, the reference generation circuit 104 needs to generate a temperature that is consistent with the temperature of the environment where the ultra-low power supply voltage detection circuit is located and the power supply voltage V to be measured. DD Unrelated reference voltage V REF By designing the temperature characteristics of the reference generation circuit 104, a reference voltage V that is approximately independent of temperature can be generated. REF .like Figure 3 As shown, the reference generation circuit 104 is composed of a fourth N-type transistor NM4 and a fourth P-type transistor PM4 connected in series. The fourth N-type transistor NM4 adopts a diode connection. The gate of the fourth P-type transistor PM4 is provided with a gate voltage V by the gate voltage generation circuit 102. G MOS transistor subthreshold saturation current I M Satisfies the following formula:

[0057]

[0058] Where k = μC OX ,m=1+(C d / C OX ), μ is the mobility of electrons in the MOS transistor substrate, C OX is the unit capacitance of the gate in the MOS transistor, C d is the depletion layer capacitance per unit area of ​​the MOS transistor, W is the width of the MOS transistor channel, L is the length of the MOS transistor channel, V T is the thermal voltage, V GS is the voltage between the gate and source of the MOS transistor, V TH is the threshold voltage of the MOS transistor.

[0059] Set the current of the fourth P-type transistor PM4 to I PM4 , the current of the fourth N-type transistor NM4 is I NM4 , the fourth N-type transistor NM4 and the fourth P-type transistor PM4 of the reference generation circuit 104 are connected in series, and the currents of the two are equal, that is, I PM4 =I NM4 , set I4 = I PM4 =I NM4 Satisfies the following formula:

[0060]

[0061] The meaning of each parameter can be referred to the above I M The explanation of the meaning of each parameter in the calculation formula is that the parameters in the second item of the I4 formula are the parameters corresponding to the fourth P-type transistor PM4, and the parameters in the third item of the I4 formula are the parameters corresponding to the fourth N-type transistor NM4, which will not be repeated here. In addition, V REF Represents the reference voltage, V DDI Represents the internal power supply voltage.

[0062] The above formula is transformed to obtain the reference voltage V output by the reference generation circuit 104: REF Satisfies the following formula:

[0063]

[0064] By designing the temperature characteristics of each term in the above formula, a reference voltage V that is approximately independent of temperature can be achieved. REF .

[0065] Alternatively, as Figure 3 As shown, the gate voltage generating circuit 102 includes: a second P-type transistor PM2, the gate of the second P-type transistor PM2 is electrically connected to the drain of the second P-type transistor PM2, the substrate of the second P-type transistor PM2 is electrically connected to the source of the second P-type transistor PM2 and is connected to the internal power supply voltage VDDI The second N-type transistor NM2, the gate of the second N-type transistor NM2, the source of the second N-type transistor NM2 and the substrate of the second N-type transistor NM2 are all grounded, the drain of the second N-type transistor NM2 is electrically connected to the drain of the second P-type transistor PM2 and outputs a gate voltage V G .in addition, Figure 3 The upper end of the second N-type transistor NM2 is its drain, and the upper end of the second P-type transistor PM2 is its source.

[0066] Specifically, if Figure 3 As shown, the second P-type transistor PM2 and the second N-type transistor NM2 in the gate voltage generating circuit 102 are connected in series, and the current of the second P-type transistor PM2 is set to I PM2 , the current of the second N-type transistor NM2 is I NM2 , the two currents are equal, that is, I PM2 =I NM2 , the gate voltage V is derived in the same way G Satisfy the following calculation formula:

[0067]

[0068] The meaning of each parameter can be referred to the above I M Explanation of the meaning of each parameter in the calculation formula, gate voltage V G The parameters with a subscript of P in the formula are the parameters corresponding to the second P-type transistor PM2, and the gate voltage V G The parameters with N in the formula are the parameters corresponding to the second N-type transistor NM2, which will not be described here. DDI Represents the internal power supply voltage.

[0069] The gate voltage V G V in the formula DDI After moving the term, we can get V REF Substitute the first term of the formula into V REF The calculation formula is as follows:

[0070]

[0071] V REF Taking the derivative of temperature T, we can get the following formula:

[0072]

[0073] The channel length and channel width of the fourth N-type transistor NM4 and the second N-type transistor NM2 can be set to be the same. In order to facilitate the analysis of the above formula, the threshold voltage and the threshold voltage variation of the fourth N-type transistor NM4 and the second N-type transistor NM2 can also be set to be equal. VREF The derivative formula for temperature T can be simplified to:

[0074]

[0075] Optionally, the reference voltage V REF The relationship with temperature T is related to the size of the transistors in the gate voltage generating circuit 102 and the reference generating circuit 104. That is, the size of the transistors in the gate voltage generating circuit 102 and the reference generating circuit 104 directly affects the reference voltage V REF Specifically, referring to the above derivation formula, the sizes of the second N-type transistor NM2, the second P-type transistor PM2, the fourth N-type transistor NM4, and the fourth P-type transistor PM4 can be designed so that V REF The derivative of temperature T is equal to zero, which can realize the reference voltage V REF It has nothing to do with the temperature T.

[0076] Figure 5 This is a simulation diagram showing how the reference voltage of an ultra-low power supply voltage detection circuit varies with temperature, provided by an embodiment of the present disclosure. Figure 5 The horizontal axis represents the temperature T of the environment where the ultra-low power supply voltage detection circuit is located, in °C, and the vertical axis represents the reference voltage V REF The unit is mV. For example, Figure 5 As shown, refer to Figure 5 The coordinates of points D and E in the middle are at the power supply voltage V DD When the reference voltage V is 250mV, the temperature T increases from 0℃ to 120℃. REF The maximum value is 82.18mV, the minimum value is 79.93mV, the maximum variation is only 2.25mV, and the temperature coefficient is 233.2ppm / ℃. It can be seen that the reference voltage V REF It hardly changes with the temperature T.

[0077] Alternatively, as Figure 3 As shown, the substrate voltage generating circuit 103 includes: a third P-type transistor PM3, the gate of the third P-type transistor PM3 is electrically connected to the drain of the third P-type transistor PM3, the substrate of the third P-type transistor PM3 is electrically connected to the source of the third P-type transistor PM3 and is connected to the internal power supply voltage V DDI A third N-type transistor NM3, a gate of the third N-type transistor NM3, a source of the third N-type transistor NM3, and a substrate of the third N-type transistor NM3 are grounded, and a drain of the third N-type transistor NM3 is electrically connected to a drain of the third P-type transistor PM3 and outputs a substrate voltage V B .in addition, Figure 3The upper end of the third N-type transistor NM3 is its drain, and the upper end of the third P-type transistor PM3 is its source.

[0078] Specifically, the substrate voltage generating circuit 103 generates a lower substrate bias voltage to the fourth P-type transistor PM4 in the reference generating circuit 104, and utilizes the substrate bias effect to reduce the threshold voltage V TH4P , thereby achieving characteristics similar to a low-threshold transistor. The substrate bias effect is the effect produced when an appropriate reverse voltage, i.e., the substrate bias voltage, is applied between the substrate and the source when the voltage difference between the substrate and the source is not zero. The influence of the substrate bias effect on the threshold voltage of the fourth P-type transistor PM4 satisfies the following calculation formula:

[0079]

[0080] Among them, V TH4P is the threshold voltage of the fourth P-type transistor PM4 when there is substrate bias effect, V TH4P0 is the threshold voltage of the fourth P-type transistor PM4 when there is no substrate bias effect, γ is the substrate bias effect coefficient, V SB is the voltage difference between the source and substrate of the fourth P-type transistor PM4, Φ F is the Fermi potential of the fourth P-type transistor PM4.

[0081] It can be seen from the above formula that when the substrate voltage VB of the fourth P-type transistor PM4 is low, the threshold voltage of the fourth P-type transistor PM4 can be lowered, and the circuit structure is used to achieve characteristics similar to those of a low-threshold transistor without using a real low-threshold transistor, thereby reducing the implementation cost of the ultra-low power supply voltage detection circuit.

[0082] Alternatively, as Figure 3 As shown, the voltage detection circuit 2 includes: a fifth P-type transistor PM5, the gate of the fifth P-type transistor PM5 is grounded, the source of the fifth P-type transistor PM5 is electrically connected to the substrate of the fifth P-type transistor PM5 and is connected to the power supply voltage to be measured V DD , the fifth P-type transistor PM5 constitutes a pull-up voltage-controlled current source 21; the fifth N-type transistor NM5, the gate of the fifth N-type transistor NM5 is connected to the reference voltage VREF, the source of the fifth N-type transistor NM5 and the substrate of the fifth N-type transistor NM5 are grounded, the drain of the fifth N-type transistor NM5 is electrically connected to the drain of the fifth P-type transistor PM5 and serves as the output end of the voltage detection circuit 2, and the fifth N-type transistor NM5 constitutes a pull-down constant current source 22.

[0083] Specifically, the temperature T of the environment where the ultra-low power supply voltage detection circuit is located and the power supply voltage V to be measured are DDUnrelated reference voltage V REF The output is sent to the gate of the fifth N-type transistor NM5 in the voltage detection circuit 2, so that the fifth N-type transistor NM5 forms a constant current source, that is, a pull-down constant current source 22. The fifth N-type transistor NM5 is connected in series with the fifth P-type transistor PM5, the gate of the fifth P-type transistor PM5 is grounded, and the source of the fifth P-type transistor PM5 is connected to the power supply voltage V to be measured. DD The fifth P-type transistor PM5 is used as the power supply voltage to be measured V DD The voltage-controlled current source controlled by the pull-up voltage-controlled current source 21, the pull-up voltage-controlled current source 21 and the pull-up voltage-controlled current source 21 constitute a current comparator, so that the output voltage V OUT At the power supply voltage V DD After reaching the preset value, the power supply voltage V DD Consistent, by detecting the output voltage V OUT It can realize the ultra-low power supply voltage V DD Detection.

[0084] Specifically, combined Figure 2 and Figure 3 , at the beginning the power supply voltage to be measured is V DD The pull-up capability of the pull-up voltage-controlled current source 21 is weaker than the pull-down capability of the pull-down constant current source 22. The output voltage V OUT The output is low level. When the power supply voltage V DD When gradually increasing to a preset value, the preset value can be, for example, Figure 2 As shown, the output voltage V of the voltage detection circuit 2 is equal to 250mV. OUT and the power supply voltage V DD Synchronous change, that is, the output voltage V of the voltage detection circuit 2 OUT Follow the power supply voltage to be measured V DD Change output high level.

[0085] Therefore, by reasonably setting the sizes of the transistors in the pull-up voltage-controlled current source 21 and the pull-down constant current source 22 so that they have different pull-down and pull-up capabilities, the required power supply voltage V to be tested can be set. DD Detection node to measure the power supply voltage V DD Pull down to realize the function of ultra-low power supply voltage detection, and because the output voltage V OUT At the power supply voltage V DD When it rises to the preset value, it is equal to the power supply voltage V DD Consistent, by the output voltage V OUT The detection of ultra-low power supply voltage V DDDetection function. Optionally, the transistors included in the reference voltage circuit 1 and the voltage detection circuit 2 are both transistors using a standard CMOS process. Preferably, the transistors included in the reference voltage circuit 1 and the voltage detection circuit 2 are both transistors using a 0.18 micron standard CMOS process.

[0086] Specifically, the CMOS (Complementary Metal Oxide Semiconductor) process combines the fabrication of N-type and P-type transistors. An inversion region is created on a silicon substrate, enabling both N-type and P-type transistors to be fabricated on the same silicon substrate. The transistors included in reference voltage circuit 1 and voltage detection circuit 2 are all fabricated using a standard 0.18-micron CMOS process, without the use of low-threshold MOS transistors or zero-threshold MOS transistors. This reduces the process cost of implementing the ultra-low power supply voltage detection circuit. Specifically, the structure of substrate voltage generation circuit 103 is utilized to achieve characteristics similar to those of a low-threshold transistor, without the need for actual low-threshold transistors, thereby reducing the process cost of implementing the ultra-low power supply voltage detection circuit.

[0087] Therefore, the ultra-low power supply voltage detection circuit and reference based on a standard CMOS process provided by the embodiments of the present disclosure can ensure the accuracy of power supply voltage detection when the process and temperature change, and can realize the detection of ultra-low power supply voltages, such as 250mV power supply voltages. Moreover, by reasonably setting the sizes of the transistors in the pull-up voltage-controlled current source 21 and the pull-down constant current source 22, the required power supply voltage VDD detection node to be tested can be set to pull down the power supply voltage VDD to realize the function of ultra-low power supply voltage detection. In addition, there is no need to use low-threshold transistors, and it can be implemented in a standard CMOS process without low-threshold transistors.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusions, such that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0089] The above are merely specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to these embodiments, but is to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. An ultra-low power supply voltage detection circuit, characterized in that: include: a reference voltage circuit, the reference voltage circuit being connected to the power supply voltage to be measured and configured to output a reference voltage; wherein the reference voltage is independent of the power supply voltage to be measured and the temperature of the environment in which the ultra-low power supply voltage detection circuit is located; The reference voltage circuit includes: a voltage stabilizing circuit, a gate voltage generating circuit, a substrate voltage generating circuit and a reference generating circuit, wherein the voltage stabilizing circuit is electrically connected to the gate voltage generating circuit, the substrate voltage generating circuit and the reference generating circuit respectively, and the reference generating circuit is electrically connected to the gate voltage generating circuit and the substrate voltage generating circuit respectively; The voltage stabilizing circuit is connected to the power supply voltage to be measured and is used to output an internal power supply voltage to the gate voltage generating circuit, the substrate voltage generating circuit and the reference generating circuit; wherein the internal power supply voltage is independent of the power supply voltage to be measured; The reference generating circuit is used to output the reference voltage according to the gate voltage output by the gate voltage generating circuit and the substrate voltage output by the substrate voltage generating circuit; The voltage stabilizing circuit comprises: a first N-type transistor, wherein a gate of the first N-type transistor is electrically connected to a source of the first N-type transistor, a drain of the first N-type transistor is connected to the power supply voltage to be measured, and a substrate of the first N-type transistor is grounded; a first P-type transistor, wherein a gate of the first P-type transistor and a drain of the first P-type transistor are grounded, a source of the first P-type transistor is electrically connected to a substrate of the first P-type transistor and a source of the first N-type transistor and outputs the internal power supply voltage; The gate voltage generating circuit comprises: a second P-type transistor, wherein a gate of the second P-type transistor is electrically connected to a drain of the second P-type transistor, and a substrate of the second P-type transistor is electrically connected to a source of the second P-type transistor and is connected to the internal power supply voltage; a second N-type transistor, wherein a gate of the second N-type transistor, a source of the second N-type transistor, and a substrate of the second N-type transistor are all grounded, and a drain of the second N-type transistor is electrically connected to a drain of the second P-type transistor and outputs the gate voltage; The liner voltage generating circuit includes: a third P-type transistor, wherein a gate of the third P-type transistor is electrically connected to a drain of the third P-type transistor, and a substrate of the third P-type transistor is electrically connected to a source of the third P-type transistor and is connected to the internal power supply voltage; a third N-type transistor, wherein a gate of the third N-type transistor, a source of the third N-type transistor, and a substrate of the third N-type transistor are grounded, and a drain of the third N-type transistor is electrically connected to the drain of the third P-type transistor and outputs the substrate voltage; The reference generation circuit comprises: a fourth P-type transistor, wherein a gate of the fourth P-type transistor is connected to the gate voltage, a source of the fourth P-type transistor is connected to the internal power supply voltage, and a substrate of the fourth P-type transistor is connected to the substrate voltage; a fourth N-type transistor, wherein a gate of the fourth N-type transistor, a drain of the fourth N-type transistor, and a drain of the fourth P-type transistor are electrically connected and output the reference voltage, and a source of the fourth N-type transistor and a substrate of the fourth N-type transistor are grounded; The voltage stabilizing circuit utilizes the substrate bias effect to reduce the threshold voltage of the fourth P-type transistor; under the influence of the substrate bias effect, the threshold voltage V TH4P for: Among them, V TH4P0 is the threshold voltage of the fourth P-type transistor when there is no substrate bias effect, γ is the substrate bias effect coefficient, V SB is the voltage difference between the source and substrate of the fourth P-type transistor, Φ F is the Fermi potential of the fourth P-type transistor; The fourth P-type transistor with a lowered threshold voltage and the fourth N-type transistor are connected in series to generate the reference voltage that is independent of temperature; The calculation formula of the reference voltage is: Among them, V REF is the reference voltage, k=μC OX ,m=1+(C d / C OX ), μ is the mobility of electrons in the MOS transistor substrate, C OX is the unit capacitance of the gate in the MOS transistor, C d is the depletion layer capacitance per unit area of ​​the MOS transistor, W is the width of the MOS transistor channel, L is the length of the MOS transistor channel, V T is the thermal voltage, V GS is the voltage between the gate and source of the MOS transistor, V TH is the threshold voltage of the MOS transistor; the parameters with subscripts 4 and P in the calculation formula of the reference voltage are parameters corresponding to the fourth P-type transistor, and the parameters with subscripts 4 and N in the calculation formula of the reference voltage are parameters corresponding to the fourth N-type transistor; the parameters with subscripts 2 and P in the calculation formula of the reference voltage are parameters corresponding to the second P-type transistor, and the parameters with subscripts 2 and N in the calculation formula of the reference voltage are parameters corresponding to the second N-type transistor; A voltage detection circuit, the voltage detection circuit comprising a pull-up voltage-controlled current source and a pull-down constant current source, the pull-up voltage-controlled current source being connected to the power supply voltage to be measured, the pull-down constant current source being connected to the reference voltage, the voltage detection circuit being configured to detect the power supply voltage to be measured based on the reference voltage; wherein the output voltage of the voltage detection circuit is consistent with the power supply voltage to be measured when the power supply voltage to be measured rises to a preset value; The power supply voltage to be measured is an ultra-low power supply voltage; the reference voltage circuit does not include a low-threshold transistor; and the transistors included in the reference voltage circuit and the voltage detection circuit are both transistors made in a standard CMOS process.

2. The ultra-low power supply voltage detection circuit according to claim 1, wherein: The voltage detection circuit comprises: a fifth P-type transistor, wherein the gate of the fifth P-type transistor is grounded, and the source of the fifth P-type transistor is electrically connected to the substrate of the fifth P-type transistor and connected to the power supply voltage to be measured; wherein the fifth P-type transistor constitutes the pull-up voltage-controlled current source; a fifth N-type transistor, wherein the gate of the fifth N-type transistor is connected to the reference voltage, the source of the fifth N-type transistor and the substrate of the fifth N-type transistor are grounded, and the drain of the fifth N-type transistor is electrically connected to the drain of the fifth P-type transistor and serves as the output end of the voltage detection circuit; wherein the fifth N-type transistor constitutes the pull-down constant current source.

3. The ultra-low power supply voltage detection circuit according to claim 1, wherein: The relationship between the reference voltage and the temperature is related to the gate voltage generating circuit and the sizes of transistors in the reference generating circuit.

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