A power cycling test circuit and test method for a power semiconductor device

Abstract

The present invention discloses a power cycle test circuit and a test method for a power semiconductor device, including at least one test branch and a gate power supply module, and the structure of each test branch is the same; the output end of the heating current source is connected to the current bypass module, the positive output of the current bypass module is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the negative electrode of the current bypass module after passing through the semiconductor device under test; the gate power supply module is connected to the gate of the semiconductor device under test; the negative electrode of the test current source is connected to one end of the semiconductor device under test, and the positive electrode is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the other end of the semiconductor device under test. By adding a diode, the present invention can prevent current shunting, and can cooperate with the current bypass module to realize the switching of the heating current and the test current without adding switching devices, thereby avoiding the problem of insufficient switching speed caused by the turning on and off of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device testing, and particularly to a power cycle test circuit and a test method for power semiconductor devices. Background Art

[0002] Power cycle test equipment can not only perform reliability tests on an increasing number of power electronic devices in automotive and transportation industry applications including hybrid electric vehicles, electric vehicles, and trains, but also perform reliability tests on an increasing number of power electronic devices in renewable energy applications such as power generation and frequency converters, and wind turbines. It is used for power cycle testing and thermal characteristic testing of power electronic devices to simulate and measure the performance of power electronic devices during their lifetime. During power cycling, the test device is actively heated to the highest target temperature by the current flowing through the semiconductor, and then the heating current is turned off. The device under test is actively cooled to the lowest temperature. During the test, parameters such as the forward voltage, junction temperature, case temperature, thermal resistance, transient thermal impedance, and gate leakage current of the device under test are monitored and calculated to "instantly" discover the cause of failure.

[0003] The Chinese patent application with the publication number CN108646163A discloses a power cycle test system for semiconductor devices. The power cycle test system provided by this application can effectively utilize the cooling time of one tested branch to heat the devices of other tested branches. The number of semiconductor devices to be tested is relatively large, which can greatly improve the test efficiency of the power cycle test system. At the same time, the provided power cycle test system is provided with multiple parallel test branches. Therefore, users can switch between multiple test functions according to actual needs, and can perform comparative tests on devices of different manufacturers or models under the same test conditions.

[0004] However, the above-mentioned invention patent test cannot achieve independent control between each test branch by means of alternating switching work of two test branches. No diode is added for the switching between the DC power supply and the measurement power supply, which will result in current shunting and inaccurate testing. Each test branch is connected in parallel through a high-power IGBT (Insulated Gate Bipolar Transistor Chip) module, which requires adding a drive circuit as well as costs, dimensions, etc. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: to solve the situation that current shunting occurs during the switching between the DC power supply and the measurement power supply in the test circuit, resulting in inaccurate testing.

[0006] To solve the above technical problem, the present invention provides the following technical solutions:

[0007] A power cycle test circuit for power semiconductor devices includes at least one test branch and a gate power supply module, and the structure of each test branch is the same;

[0008] Each test branch includes a heating current source, a current bypass module, a diode, a test current source, a diode, and multiple semiconductor devices under test connected in series;

[0009] The output terminal of the heating current source is connected to the current bypass module, the positive output of the current bypass module is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the negative electrode of the current bypass module after passing through the semiconductor device under test; the gate power supply module is connected to the gate of the semiconductor device under test;

[0010] The negative electrode of the test current source is connected to one end of the semiconductor device under test, the positive electrode is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the other end of the semiconductor device under test.

[0011] Advantages: By adding a diode in the first test branch, the present invention utilizes the unidirectional conductivity characteristic of the diode to prevent current shunting, and can, without adding switching devices, cooperate with the current bypass module to achieve the switching of the heating current and the test current, thereby avoiding the problem of insufficient switching speed caused by the turning on and off of power devices.

[0012] Preferably, the current bypass module includes a plurality of field effect transistors connected in parallel, and one end of the parallel-connected field effect transistors is connected to the positive output of the heating current source, and the other end is connected to the negative output of the heating current source.

[0013] Preferably, the semiconductor device under test includes a plurality of DUTs connected in series.

[0014] Preferably, it further includes a data acquisition module, and the data acquisition module is arranged on the branch where the semiconductor device under test is located.

[0015] Preferably, the data acquisition module has multi-channel high-speed and high-precision differential signal acquisition ports.

[0016] Preferably, the gate power supply module has multiple independent adjustable positive and negative voltages, which are respectively connected to the gates of multiple semiconductor devices under test.

[0017] Preferably, there are three test branches, specifically the first test branch, the second test branch, and the third test branch.

[0018] Preferably, the first test branch, the second test branch, and the third test branch all adopt independent heating current sources.

[0019] A test method for a power cycle test circuit of a power semiconductor device. When each test branch starts a power cycle test, the heating current source outputs a preset current to apply a load current to multiple semiconductor devices under test through a diode. At this time, the data acquisition module monitors in real time the conduction voltage of multiple semiconductor devices under test and the current value output by the heating current source;

[0020] When the preset junction temperature, case temperature or heating time is reached, by starting the current bypass module, the current output by the heating current source will flow through the current bypass module, and the current flowing through the object under test is quickly turned off. During the time when the current of the object under test is turned off, the junction temperature and case temperature of the object under test decrease, and the data acquisition module monitors the conduction voltage during the turn-off of the heating current of the object under test in real time to obtain the junction temperature and thermal resistance.

[0021] Preferably, during the test, multiple semiconductor devices under test can be tested individually or in series. The gate power supply module turns on the corresponding selected semiconductor device under test and outputs a preset driving voltage to the semiconductor device under test, and the gate of the semiconductor device under test is continuously powered to maintain a continuously forward conduction state.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] (1) By adding an anti-reverse diode in the main circuit, the present invention utilizes the unidirectional conductivity of the diode to prevent shunting, and can, without adding switching devices, cooperate with the auxiliary test module to realize the switching of the heating current and the test current, thereby avoiding the problem of insufficient switching speed caused by the turning on and off of power devices.

[0024] (2) By using multiple parallel field effect transistors to replace the IGBT module as the auxiliary test circuit, the present invention achieves the test objectives of high precision, high speed and high reliability, and reduces losses, structural dimensions and costs.

[0025] (3) The present invention adopts a multi-branch test structure, which can expand the test capacity and improve the test efficiency and flexibility. Description of the Drawings

[0026] Figure 1 is a schematic diagram of the main circuit of the embodiment of the present invention;

[0027] Figure 2 is a circuit diagram of the first test branch of the embodiment of the present invention;

[0028] Figure 3 is a test timing diagram of a single test branch of the embodiment of the present invention. Detailed Embodiments

[0029] To facilitate the understanding of the technical solution of the present invention by those skilled in the art, the technical solution of the present invention will be further described below in conjunction with the accompanying drawings of the specification.

[0030] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more, unless otherwise specifically defined.

[0031] Referring to Figure 1 , this embodiment discloses a power cycle test circuit for a power semiconductor device, which includes three test branches, namely a first test branch 1, a second test branch 2, and a third test branch 3; the first test branch 1, the second test branch 2, and the third test branch 3 all adopt the same circuit structure. Therefore, this embodiment mainly describes the first test branch 1 in detail.

[0032] The first test branch 1 includes a heating current source P1, a current bypass module U1, a diode D1, a test current source P4, a diode D4, and a semiconductor device under test. The semiconductor device under test in the first test branch 1 is specifically four series-connected DUT1 (test equipment, which is a semiconductor device in this embodiment), DUT2, DUT3, and DUT4.

[0033] The output terminal of the heating current source P1 is connected to the current bypass module U1. The positive output of the current bypass module U1 is connected to the positive electrode of the diode D1. The negative electrode of the diode D1 is connected to the negative electrode of the current bypass module U1 after passing through the semiconductor device under test. Therefore, the heating current source P1 can output current that passes through the diode D1 and then successively passes through DUT1, DUT2, DUT3, and DUT4 and then returns to the heating current source P1.

[0034] The current bypass module U1 includes a plurality of parallel-connected field effect transistors Q1,..., Qn (n≥2). One end of the parallel-connected field effect transistors Q1,..., Qn is connected to the positive output of the heating current source P1, and the other end is connected to the negative output of the heating current source P1; when the current bypass module U1 is turned on, the current output by the heating current source P1 will flow back through the current bypass module U1, thereby quickly turning off the current flowing to the semiconductor device under test.

[0035] In this embodiment, by using a plurality of parallel-connected field effect transistors Q1,..., Qn to replace the IGBT module in the prior art as an auxiliary test circuit, the test objectives of high precision, high speed, and high reliability can be achieved, and the loss, structural size, and cost can be reduced.

[0036] At the same time, the method of paralleling multiple field effect transistors has the advantages of low conduction loss and fast switching speed compared with the IGBT module as an auxiliary test current.

[0037] The negative terminal of the test current source P4 is connected to one end of the semiconductor device under test, the positive terminal is connected to the positive terminal of the diode D4, and the negative terminal of the diode D4 is connected to the other end of the semiconductor device under test; thus, the test current source P4 can output a constant small current that passes through the diode D4 and then sequentially passes through DUT1, DUT2, DUT3, and DUT4 before returning to the test current source P4.

[0038] The gate power supply module U4 is connected to the gate of the semiconductor device under test. The gate power supply module U4 has 12 independent adjustable positive and negative voltages and can respectively control the on-off states of 12 semiconductor devices under test. Therefore, the gate power supply module U4 outputs four independent gate voltages to control the on-off states of DUT1, DUT2, DUT3, and DUT4.

[0039] The data acquisition module U5 has multi-channel high-speed and high-precision differential signal acquisition ports and can monitor in real time the conduction voltages of the devices under test DUT1, DUT2, DUT3, and DUT4 and the current value output by the heating current source P1.

[0040] During the test, the devices under test DUT1, DUT2, DUT3, and DUT4 can be flexibly selected and can be tested individually or in series. The gate power supply module U4 turns on the corresponding selected devices under test and outputs a preset driving voltage to the devices under test, and the gates of the devices under test are continuously powered to maintain a continuous forward conduction state. Subsequently, a load current is applied to the devices under test, and the magnitude of the load current is determined according to the application conditions of the devices under test. The on and off times (cycle periods) should be controlled by monitoring the housing temperature Tc, the constant junction temperature change (the housing temperature is approximately unchanged), and the fixed time setting. The test timing is as Figure 3 shown.

[0041] When the first test branch 1 starts the power cycle test, the heating current source P1 outputs a preset current that flows through the diode D1 to apply a load current to DUT1, DUT2, DUT3, and DUT4. At this time, the data acquisition module U5 monitors in real time the conduction voltages of DUT1, DUT2, DUT3, and DUT4 and the current value output by the heating current source P1.

[0042] When the preset junction temperature or housing temperature or heating time is reached, by starting the current bypass module U1, the current output by the heating current source P1 will flow through the current bypass module U1, and the current flowing through the object under test will be quickly turned off. During the time when the current of the object under test is turned off, the junction temperature and housing temperature of the object under test will decrease, and the data acquisition module U5 monitors in real time the conduction voltage during the turn-off period of the heating current of the object under test to obtain the junction temperature and thermal resistance.

[0043] During this process, due to the diode D1 provided in the first test branch 1, by utilizing the unidirectional conduction characteristic of the diode, the switching between the heating current and the test current can be achieved in cooperation with the current bypass module U1 without adding switching devices, thereby avoiding the problem of insufficient switching speed caused by the turning on and off of the power devices.

[0044] That is, when the current bypass module U1 is started, by utilizing the characteristic that the current bypass module U1 is cut off because its voltage is lower than the forward conduction voltage of the diode D1, the heating current of the semiconductor device under test is turned off, and the test current source P4 outputs to the object under test through the diode D4, thereby realizing the switching between the heating current and the test current.

[0045] Similarly, in the second test branch 2, the heating current source P2 applies load current to the four semiconductor devices DUT5, DUT6, DUT7, and DUT8 through the current bypass module U2 and the diode D2, and the test current source P5 is connected to these four semiconductor devices through the diode D5; the four independent gate voltages of the gate power module U4 control the on and off of these four semiconductor devices; the data acquisition module U5 monitors the current of the second test branch 2 and the conduction voltage drops of the four semiconductor devices.

[0046] In the third test branch 3, the heating current source P3 applies load current to the four semiconductor devices DUT9, DUT10, DUT11, and DUT12 through the current bypass module U3 and the diode D3, and the test current source P6 is connected to these four semiconductor devices through the diode D6; the four independent gate voltages of the gate power module U4 control the on and off of these four semiconductor devices; the data acquisition module U5 monitors the current of the third test branch 3 and the conduction voltage drops of these four semiconductor devices.

[0047] Since each test circuit is provided with a heating current source, the three test branches of this embodiment work independently and can support the power cycle test of up to 12 power semiconductor devices of three package specifications simultaneously. The test efficiency and test flexibility are improved.

[0048] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention, and any reference signs in the claims should not be regarded as limiting the claimed rights.

[0049] The above-described embodiments merely represent the implementation manners of the invention. The protection scope of the present invention is not limited to the above embodiments. For those skilled in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all fall within the protection scope of the present invention.

Claims

1. A test method using a power cycle test circuit for power semiconductor devices, characterized in that: It includes at least one test branch, a gate power supply module and a data acquisition module, and the structure of each test branch is the same; Each test branch includes a heating current source, a current bypass module, a diode D1, a test current source, a diode D4, and multiple series-connected semiconductor devices under test. The data acquisition module is arranged on the branch where the semiconductor devices under test are located; The output end of the heating current source is connected to the current bypass module, the positive output of the current bypass module is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the negative electrode of the current bypass module after passing through the semiconductor device under test; the gate power supply module is connected to the gate of the semiconductor device under test; The negative electrode of the test current source is connected to one end of the semiconductor device under test, the positive electrode is connected to the positive electrode of the diode D4, and the negative electrode of the diode D4 is connected to the other end of the semiconductor device under test; The test method of the power semiconductor device power cycle test circuit is as follows: when the power cycle test starts for each test branch, the heating current source outputs a preset current to flow through the diode D1 to apply a load current to multiple semiconductor devices under test. At this time, the data acquisition module monitors the conduction voltage of multiple semiconductor devices under test and the current value output by the heating current source in real time; When the preset junction temperature or case temperature or heating time is reached, by starting the current bypass module, the current output by the heating current source will flow through the current bypass module, and the current flowing through the object under test will be quickly turned off. During the time when the current of the object under test is turned off, the junction temperature and case temperature of the object under test will drop. The data acquisition module monitors the conduction voltage during the turn-off of the heating current of the object under test in real time to obtain the junction temperature and thermal resistance.

2. The test method of a power cycle test circuit using a power semiconductor device according to claim 1, characterized in that: The current bypass module includes several parallel field effect transistors, and one end of the parallel field effect transistors is connected to the positive output of the heating current source, and the other end is connected to the negative output of the heating current source.

3. The test method using the power cycle test circuit of the power semiconductor device according to claim 1, characterized in that: The semiconductor device under test includes several series-connected DUTs.

4. The testing method using a power cycling test circuit of a power semiconductor device according to claim 1, characterized in that: The data acquisition module has a multi-channel high-speed and high-precision differential signal acquisition port.

5. The testing method of a power cycling test circuit using a power semiconductor device according to claim 1, characterized in that: The gate power supply module has multiple independent adjustable positive and negative voltages, which are respectively connected to the gates of multiple semiconductor devices under test.

6. The test method using a power cycling test circuit of a power semiconductor device according to claim 1, characterized in that: There are three test branches, specifically the first test branch (1), the second test branch (2), and the third test branch (3).

7. A test method using a power cycle test circuit of a power semiconductor device according to claim 6, characterized in that: The first test branch, the second test branch, and the third test branch all adopt independent heating current sources.

8. The test method of a power cycle test circuit using a power semiconductor device according to claim 1, characterized in that: During the test, multiple semiconductor devices under test can be tested in series one by one or in multiple numbers. The gate power supply module turns on the corresponding selected semiconductor device under test and outputs a preset driving voltage to the semiconductor device under test, and the gate of the semiconductor device under test is continuously powered to maintain a continuous forward conduction state.

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