A method for processing in-core kernel floating-point exceptions

Abstract

The application discloses a processing method of in-core kernel floating-point exception, and the processing method comprises the following steps: monitoring first exception information which does not satisfy a shielding condition in a running process of a chip, wherein the first exception information comprises an abnormal floating point; determining an input floating-point register which causes the abnormal floating point in the first exception information; and processing the floating-point register of the input abnormal floating point, and correcting the input floating-point register to a legal value. Through the correction of the floating-point register of the input abnormal floating point, the processing method of the abnormal floating point is analyzed and optimized, and the processing speed of the abnormal floating point under the in-core kernel is improved. Unlike the processing method of calling a soft floating-point simulation program in the prior art, the method directly analyzes operation instructions, finds the value of an operation number, corrects the value, and exits and returns to the original processing flow, so that the processing speed is improved.

Description

Technical Field

[0001] This invention belongs to the field of computer verification technology, specifically, it relates to a method for handling floating-point exceptions in chip cores. Background Technology

[0002] With the development of domestically produced processors, more and more domestically produced processors based on the MIPS architecture are being used in industrial production. Industrial production typically uses RTOS operating systems, which, compared to general-purpose operating systems, require fast and concise system responses. However, unlike x86 architecture and POWERPC architecture, MIPS floating-point exception handling relies on software. Traditional methods require calling software floating-point programs, resulting in lengthy processing times, consuming CPU resources, and impacting the response speed of interrupt exceptions in the RTOS environment. This presents a series of problems for the application of domestically produced chip core architecture CPUs in industrial settings.

[0003] In view of this, the present invention is proposed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a method for handling floating-point exceptions in chip cores, thereby solving the problem of slow processing speed of floating-point exceptions in chip cores.

[0005] To solve the above-mentioned technical problems, the basic concept of the technical solution adopted by the present invention is as follows:

[0006] A method for handling floating-point exceptions in a chip core, the method comprising:

[0007] The monitoring chip does not meet the shielding conditions during operation. The first abnormal information includes abnormal floating point.

[0008] Determine the input floating-point register that caused the abnormal floating-point in the first abnormal information;

[0009] The floating-point register of the input abnormal floating-point value is processed to correct the input floating-point register to a valid value.

[0010] Furthermore, the method also includes: during the chip initialization process, monitoring second abnormal information in the chip that meets the masking conditions; the second abnormal information includes multiple types of MIPS abnormalities;

[0011] The second abnormal information is masked.

[0012] Furthermore, during the monitoring process, floating-point registers and general-purpose registers need to be pushed onto the stack.

[0013] Furthermore, after the floating-point register and general-purpose register are pushed onto the stack, the processor executes floating-point instructions. During execution, abnormal floating-point instructions that do not meet the masking conditions are stored in the floating-point exception register, thereby determining the floating-point register that received the abnormal floating-point instruction.

[0014] Furthermore, during chip monitoring, the shielding conditions are as follows: the chip core needs to be initialized, the FS field in the floating-point register is set to 1, the RM field is set to 0, and all Enables fields are set to 0.

[0015] Furthermore, for abnormal floating-point events that do not meet the masking conditions, the instruction currently pointed to by the epc is retrieved and filled into the instruction cache to be processed. It is then determined whether the abnormal floating-point event is in the MIPS branch delay slot. If so, the next instruction pointed to by the epc is filled into the instruction cache to be processed.

[0016] Furthermore, if the abnormal floating point is not in the MIPS branch delay slot, the current instruction is parsed to find the floating point register into which the current instruction is input.

[0017] Furthermore, the abnormal floating point in the floating-point exception register is located. The abnormal floating point corresponds to the value in the input floating-point register in the check stack, and it is corrected to a normalized number.

[0018] Furthermore, the exception handling process ends, the stack is popped to restore the register context, and the process jumps to the EPC return address.

[0019] Furthermore, during operation, the monitoring chip receives rounding mode signals from the core, and the computing core performs rounding operations on the preliminary calculation results.

[0020] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0021] 1. By correcting the floating-point registers of input abnormal floating-point values ​​and analyzing and optimizing the abnormal floating-point handling method, the processing speed of abnormal floating-point values ​​under the chip core is improved. Unlike the traditional method of calling a soft floating-point simulation program, this method directly parses the operation instructions, finds the values ​​of the operands, corrects them, and then exits to return to the original processing flow, thus improving processing speed.

[0022] 2. For second-order exceptions that can be masked out, they are handled automatically by the hardware without generating exceptions, thus improving program execution speed.

[0023] The specific embodiments of the present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings, as part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention, but do not constitute an undue limitation of the invention. Obviously, the drawings described below are merely some embodiments, and those skilled in the art can obtain other drawings based on these drawings without creative effort. In the drawings:

[0025] Figure 1 This is a schematic diagram of the chip core floating-point exception handling method in an embodiment of the present invention.

[0026] It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art by referring to specific embodiments. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0028] In the description of this invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] like Figure 1 As shown in the embodiment of the present invention, a method for handling floating-point anomalies in a chip core is introduced. The method includes: monitoring first anomaly information that the chip does not meet the shielding conditions during operation, wherein the first anomaly information includes an abnormal floating-point.

[0031] Determine the input floating-point register that caused the abnormal floating-point in the first abnormal information;

[0032] The floating-point register of the input abnormal floating-point value is processed to correct the input floating-point register to a valid value.

[0033] By processing the input floating-point register that caused the abnormal floating-point, and correcting the input floating-point register to a valid value, the processor's processing speed for abnormal floating-point events can be improved.

[0034] First, during the initialization of the chip's core processor system, the following masking conditions are set: the FS field in the floating-point register is set to 1, the RM field is set to 0, and all entries in the Enables area are set to 0. Setting FS to 1 ensures that the floating-point module will clear the output denormalized numbers, setting the RM field to 0 ensures automatic rounding, and the Enables area masks most interrupts. Setting these masking conditions can initially mask most exceptions, thereby reducing the processor's processing time for other exceptions and improving processing speed.

[0035] In the prior art, the process of handling abnormal floating-point events involves calling a floating-point simulation program. Compared with the prior art, this application reduces the floating-point exception handling time and improves the response speed of the chip kernel to interrupt exceptions in the RTOS operating system.

[0036] The floating-point register is used to control whether to enable or disable the simulation of the floating-point register stack using the floating-point register file. At the same time, the floating-point register also stores floating-point data values.

[0037] If the stack enable bit in the floating-point register is set, 8 registers out of 32 floating-point registers are selected. If the stack enable bit in the floating-point register is set to 1, it is used in the operation, indicating that the floating-point register stack simulated by the register exists. Then, all registers with numbers less than 8 used in floating-point operation instructions are used as stack registers of the floating-point register stack, thereby simulating the kernel's floating-point register stack.

[0038] A decoder is used to distinguish the instruction set mode during the instruction decoding process, and output the given-point arithmetic unit or floating-point arithmetic unit after decoding the instruction according to the distinguished instruction set mode.

[0039] The fixed-point arithmetic unit is used to process the fixed-point instructions of the instruction set based on the output of the decoder and output the execution result. The floating-point arithmetic unit is used to process the floating-point instructions of the instruction set based on the output of the decoder and output the execution result.

[0040] In other embodiments, in the MIPS architecture, the floating-point register number given by some floating-point instructions is a relative value. It must be added to the top pointer (TOP) of the floating-point circular stack in the floating-point status word to obtain the actual floating-point register number. To solve this problem, this invention sets a TOP pointer register in the decoder and maintains a stack enable signal in the floating-point control register in the floating-point physical register file. This signal determines whether to select 8 floating-point registers to simulate a floating-point stack. If the stack enable bit is set, during the corresponding floating-point instruction operation, registers with register numbers less than 8 modify their source or destination logical register numbers according to the value of TOP during decoding, and modify the TOP value according to the instruction content; then the result is sent to the processor. If the stack enable bit is cleared, the operation is considered as if the register-simulated stack does not exist, and the existing operating steps proceed normally.

[0041] It maintains a stack enable bit. When the enable bit is set to 1, it means that the processor will simulate the processor's floating-point register stack operation; when the enable bit is set to 0, it means that the processor will not simulate the processor's floating-point register stack operation and the processor will perform the operation according to the normal process.

[0042] In this embodiment of the invention, the floating-point register includes a floating-point register stack, which consists of eight stack registers that can directly perform floating-point operations, numbered sequentially from 0 to 7. This register is called a floating-point register stack because the x86 processor uses them as a single stack. The floating-point register stack is a downward-expanding circular stack, and the processor uses three bits in another register to mark the position of the stack top; these three bits are called the TOP pointer.

[0043] When data needs to be loaded into the stack register, i.e., pushed onto the stack, the value of the TOP pointer is decremented by 1, and then the data is stored in the floating-point register pointed to by the TOP pointer. When the value of the TOP pointer is 0, the next push will push the data into stack register number 7, and the value of the TOP pointer will be set to 7.

[0044] When it is necessary to save data in the stack to memory, i.e., popping from the stack, a pop operation is performed. The pop operation is similar to the push operation. The TOP pointer is incremented by 1. If the TOP pointer value is 7 at this time, the TOP pointer value is set to 0 after popping from the stack.

[0045] The TOP pointer register is used to maintain a TOP pointer, which is also the stack operation pointer, and stores the value of the TOP pointer. This TOP pointer can be read, written, incremented by 1, decremented by 1, etc.

[0046] In this embodiment of the invention, during the monitoring process, it is necessary to push the floating-point register and the general-purpose register onto the stack, that is, to push the values ​​of the input floating-point register and the general-purpose register onto the stack.

[0047] After floating-point registers and general-purpose registers are pushed onto the stack, the processor executes floating-point instructions. During execution, any abnormal floating-point instructions that do not meet the masking conditions are stored in the floating-point exception register, thus determining the floating-point register of the input abnormal floating-point instruction. During the monitoring process, there will be multiple floating-point registers for input floating-point instructions, several of which will not meet the masking conditions and will become abnormal floating-point instructions. These abnormal floating-point instructions will be stored in the floating-point exception register, and the floating-point register of the output abnormal instruction will be determined by using the abnormal floating-point instructions in the floating-point exception register.

[0048] In this embodiment of the invention, during chip monitoring, the masking conditions are as follows: during chip core initialization, the FS field in the floating-point register is set to 1, the RM field is set to 0, and all Enables fields are set to 0. By utilizing hardware characteristics to set FS to 1 and RM to 0, all maskable exceptions can be masked. Exceptions such as overflow and underflow, which can be handled by hardware, are handled by hardware and corrected to approximate values ​​to meet the needs of RTOS operating system users. This also reduces the load on exception handling programs and improves efficiency.

[0049] In this embodiment of the invention, the method further includes: during the chip initialization process, monitoring second abnormal information in the chip that meets the masking conditions; the second abnormal information includes various types of MIPS abnormalities; and masking the second abnormal information. Through the above settings, during chip monitoring, the second type of abnormal information that can be masked is also simply processed, thereby further improving the chip's processing speed.

[0050] In this embodiment of the invention, in the method for handling floating-point exceptions in the chip core, during chip detection, maskable exceptions are automatically handled by hardware without generating exceptions, which can improve program execution speed.

[0051] In this invention, the floating-point interrupt control circuit is replaced by a rewritable microprogram RAM. The floating-point interrupt control circuit is a microprogram RAM with a simple structure, which can be programmed to control the triggering method of abnormal interrupts.

[0052] In this embodiment of the invention, the triggering reasons for non-maskable floating-point anomalies can be divided into three points: the first point is a denormalized operand, the second point is an illegal operand error, and the third point is a denormalized number or underflow, where the underflow or inaccuracy enable signal is set while the FS bit is not set.

[0053] Because of the third reason, FS was previously set to 1 and all maskable exceptions were masked, so they were handled automatically by the hardware and would not be triggered. The remaining possible reasons are only the first and second reasons. In the MIPS architecture, the FPU guarantees not to produce denormalized results, and illegal operands have been masked. Therefore, for the first and second reasons, only the source operands need to be corrected.

[0054] Meanwhile, for exceptions that cannot be masked, the processing flow is simplified by directly correcting the source operands without calling the soft floating-point simulation program, which further reduces the processing steps and improves the processing speed.

[0055] By separately correcting abnormal floating-point events and simplifying other exceptions for non-maskable abnormal floating-point events, the floating-point exception handling time is reduced, thereby improving the RTOS operating system's response speed to interrupt exceptions under the chip kernel.

[0056] After the exception floating-point handling is completed, the stack is popped to restore the context of the floating-point registers, and the system jumps to the original EPC address.

[0057] In this embodiment of the invention, for abnormal floating-points that do not meet the masking conditions, the instruction pointed to by the current epc is retrieved and filled into the instruction cache to be processed. It is then determined whether the abnormal floating-point is in the MIPS branch delay slot. If so, the next instruction pointed to by epc is filled into the instruction cache to be processed. At the same time, the current instruction is parsed to find the floating-point register into which the current instruction is input.

[0058] By employing different handling procedures depending on whether the current exception is a floating-point exception, the processor's processing speed is ultimately improved.

[0059] In this embodiment of the invention, if an abnormal floating-point instruction is not in the MIPS branch delay slot, the current instruction is directly parsed to find the floating-point register into which the current instruction is input. Regardless of whether a branch occurs, it is always executed, and instructions located in the branch delay slot are committed before branch instructions.

[0060] The abnormal floating point in the floating-point exception register is identified. The abnormal floating point corresponds to the value in the input floating-point register in the check stack. It is then corrected to a normalized number. Finally, the processor exits and returns to the original processing flow after correcting the abnormal floating point, which improves the processing speed.

[0061] In this embodiment of the invention, whether handling abnormal floating-point events or various types of MIPS exceptions, at the end of the exception handling process, the stack is popped to restore the register context, and the process jumps to the epe return address.

[0062] The following describes in detail the chip core floating-point exception handling method in this embodiment of the invention. The method mainly includes the following steps:

[0063] 1. Push the floating-point registers and general-purpose registers onto the stack;

[0064] 2. Determine if the current exception is a floating-point exception. If so, continue to step 3; otherwise, proceed to step 7.

[0065] 3. Retrieve the instruction pointed to by the current EPC (the PC pointer when an exception occurs) and fill it into the instruction buffer to be processed. Further determine whether the exception floating point is in the MIPS branch delay slot; if so, proceed to step 4; otherwise, proceed to step 5.

[0066] 4. Fill the instruction pointed to by epe into the instruction buffer to be processed, and proceed to step 5;

[0067] 5. Parse the current instruction and locate the floating-point register where the instruction is input; check the value in the input floating-point register on the stack, and if it is abnormal, correct it to a normalized number or a valid value, then proceed to step 6;

[0068] 6. The exception handling process ends, the stack is popped to restore the register context, and the process jumps to the original EPC address;

[0069] 7. Other exception handling procedures: After processing is complete, return to step 6.

[0070] In this embodiment of the invention, the FPU is connected to the processor core. As a hardware accelerator, the communication between the FPU and the processor core should be as direct as possible, and the FPU's response to the processor core's control signals should be as rapid as possible; only in this way can higher computational efficiency be achieved. In the control method of this invention, the two operands of the FPU are directly connected to the top and second-to-bottom of the stack; the start signal, operator, and rounding mode all come directly from the decoder. When a floating-point instruction is executed, the decoder can send the control signal to the FPU immediately; the calculation result is directly returned to the top data input register of the processor core stack, and the top of the stack can obtain the calculation result immediately.

[0071] Define local instructions, or control microcode, specifically for controlling the FPU. These control microcodes should be able to control the FPU to complete the entire process from reading parameters to returning the calculation result. Therefore, this invention defines two types of control microcodes: the first type controls the FPU to read parameters (including operands, operators, and rounding methods) and start the calculation, while the second type controls the FPU to return the calculation result to the top of the stack.

[0072] The system performs basic arithmetic operations based on the corresponding algorithm. This includes arithmetic operations on the exponent and mantissa. In addition, it needs to round the preliminary calculation result according to the rounding mode value. The monitoring chip receives the rounding mode signal from the core during operation. The calculation core performs the rounding operation on the preliminary calculation result. When the rounding mode value is "00", the nearest rounding method is used; when it is "01", it is rounded to zero; when it is "10", it is rounded up; and when it is "11", it is rounded down.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. The implementation schemes in the above embodiments can be further combined or replaced. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for handling floating-point exceptions in a chip core, characterized in that, The processing method includes: monitoring the chip during operation for a first abnormality that does not meet the shielding conditions, the first abnormality including an abnormal floating point; determining the input floating point register that caused the abnormal floating point in the first abnormality; processing the input floating point register to correct it to a valid value; During the monitoring process, floating-point registers and general-purpose registers need to be pushed onto the stack; During chip monitoring, the shielding conditions are as follows: the chip core needs to be initialized, the FS field in the floating-point register is set to 1, the RM field is set to 0, and all fields in the Enables area are set to 0.

2. The method for handling floating-point exceptions in a chip core according to claim 1, characterized in that: The method further includes: during the chip initialization process, monitoring second abnormal information in the chip that meets the masking conditions; the second abnormal information includes various types of MIPS abnormalities; and masking the second abnormal information.

3. A method for handling floating-point exceptions in a chip core according to claim 1 or 2, characterized in that: After the floating-point register and general-purpose registers are pushed onto the stack, the processor executes floating-point instructions. During execution, abnormal floating-point instructions that do not meet the masking conditions are stored in the floating-point exception register, thereby determining the floating-point register that received the abnormal floating-point instruction.

4. The method for handling floating-point exceptions in a chip core according to claim 3, characterized in that: For abnormal floating-point events that do not meet the masking conditions, the instruction pointed to by the current epc is retrieved and filled into the instruction buffer to be processed. It is then determined whether the abnormal floating-point event is in the MIPS branch delay slot. If so, the next instruction pointed to by the epc is filled into the instruction buffer to be processed. At the same time, the current instruction is parsed to find the floating-point register into which the current instruction is input.

5. The method for handling floating-point exceptions in a chip core according to claim 4, characterized in that: If the abnormal floating point is not in the MIPS branch delay slot, the current instruction is directly parsed to find the floating point register into which the current instruction is input.

6. The method for handling floating-point exceptions in a chip core according to claim 1, characterized in that: Identify the abnormal floating-point value in the floating-point exception register. The abnormal floating-point value corresponds to the value in the input floating-point register in the check stack, and correct it to a normalized number.

7. A method for handling floating-point exceptions in a chip core according to claim 1 or 2, characterized in that: The exception handling process ends, the stack is popped to restore the register context, and the process jumps to the EPC return address.

8. The method for handling floating-point exceptions in a chip core according to claim 1, characterized in that: During operation, the monitoring chip receives a rounding mode signal from the core, and the computing core performs rounding operations on the preliminary calculation results.

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