Data processing method, FPGA acceleration card and computer readable storage medium

Abstract

The present invention provides a data processing method, which is applied to an FPGA acceleration card, comprising: a data packet processing module unpacks a first data packet sent by a data sending end to obtain data to be processed, and sends the data to be processed to a kernel module; the kernel module performs computational processing on the data to be processed to obtain processed data, and sends the processed data to the data packet processing module; the data packet processing module performs packet processing on the processed data to obtain a second data packet, and sends the second data packet to a data receiving end; the present invention sets a direct data path between the data packet processing module and the kernel module, which can ensure that the FPGA acceleration card can directly and actively process and send data, and can avoid the efficiency loss of multiple acceleration card acceleration tasks caused by repeatedly reading and writing low-speed cache, thereby improving the overall acceleration performance of multiple acceleration cards. The present invention also provides an FPGA acceleration card and a computer-readable storage medium, which have the above-mentioned beneficial effects.

Description

Technical Field

[0001] The present invention relates to the field of FPGA, and in particular to a data processing method, an FPGA acceleration card and a computer-readable storage medium. Background Art

[0002] In order to improve the parallel computing capability of the computing system, FPGA acceleration cards are usually used to share the CPU computing pressure to improve the performance of the entire computing system. In related technologies, the FPGA acceleration card needs to send the original data to the low-speed cache area for storage before data processing, and then read the data from the cache for processing according to the needs of the kernel; after the processing is completed, the processed data needs to be cached to the above-mentioned low-speed cache area, and then read the data from the cache for sending according to the needs. In the acceleration task involving multiple acceleration cards, the above-mentioned read and write low-speed cache operations will consume a lot of time, which will reduce the overall acceleration performance of multiple acceleration cards. Summary of the invention

[0003] The purpose of the present invention is to provide a data processing method, an FPGA acceleration card and a computer-readable storage medium, which can set a direct data path between the data packet processing module and the kernel module to ensure that the FPGA acceleration card can directly process and send data, avoid the efficiency loss of multiple acceleration card acceleration tasks caused by repeatedly reading and writing low-speed cache, and improve the overall acceleration performance of multiple acceleration cards.

[0004] In order to solve the above technical problems, the present invention provides a data processing method, which is applied to an FPGA acceleration card, comprising:

[0005] The data packet processing module unpacks the first data packet sent by the data sending end to obtain data to be processed, and sends the data to be processed to the kernel module;

[0006] The kernel module performs computation on the data to be processed to obtain processed data, and sends the processed data to the data packet processing module;

[0007] The data packet processing module performs packet processing on the processed data to obtain a second data packet, and sends the second data packet to a data receiving end.

[0008] Optionally, sending the data to be processed to a kernel module includes:

[0009] The data packet processing module sends the data to be processed to the first clock module;

[0010] The first clock module performs clock conversion on the data to be processed, and sends the converted data to be processed to the kernel module;

[0011] Accordingly, sending the processed data to the data packet processing module includes:

[0012] The core module sends the processed data to the second clock module;

[0013] The second clock module performs the clock conversion on the processed data and caches the converted processed data, so that the data packet processing module obtains the converted processed data from the second clock module.

[0014] Optionally, the first clock module includes a cache queue and a first clock conversion queue, and the first clock module performs clock conversion on the data to be processed and sends the converted data to be processed to the kernel module, including:

[0015] The cache queue caches the data to be processed;

[0016] The first clock conversion queue performs the clock conversion on the to-be-processed data obtained from the cache queue, and sends the converted to-be-processed data to the kernel module.

[0017] Optionally, it also includes:

[0018] The data packet processing module obtains the remaining space information of the cache queue, and performs the encapsulation process on the remaining space information to obtain a response data packet;

[0019] The response data packet is sent to the data sending end, so that the data sending end uses the remaining space information to adjust the flow of sending the first data packet.

[0020] Optionally, the second clock module includes a RAM and a second clock conversion queue, and the second clock module performs the clock conversion on the processed data and caches the converted processed data, including:

[0021] The second clock conversion queue performs the clock conversion on the processed data, and caches the converted processed data into the RAM;

[0022] Correspondingly, the data packet processing module obtains the converted processed data from the second clock module, including:

[0023] The data packet processing module obtains the converted processed data from the RAM.

[0024] Optionally, the data packet processing module unpacks the first data packet sent by the data sending end to obtain data to be processed, including:

[0025] The data packet processing module obtains the first data packet through a communication controller; the communication controller includes a MAC controller or a PCIe controller;

[0026] Unpacking the first data packet to obtain data to be processed;

[0027] Correspondingly, the sending of the second data packet to the data receiving end includes:

[0028] The data packet processing module sends the second data packet to the data receiving end through the communication controller.

[0029] Optionally, before sending the to-be-processed data to the kernel module, the method further includes:

[0030] The data packet processing module sends the data to be processed to the data selection module;

[0031] The data selection module sends the to-be-processed data to the kernel module or the storage module according to preset configuration information;

[0032] Correspondingly, it also includes:

[0033] The data selection module obtains the processed data from the kernel module or the storage module according to the preset configuration information, and sends the processed data to the data packet processing module.

[0034] The present invention also provides an FPGA acceleration card, comprising: a data packet processing module and a kernel module, wherein:

[0035] The data packet processing module is used to unpack a first data packet sent by a data sending end to obtain data to be processed, and send the data to be processed to the kernel module; to pack the processed data sent by the kernel module to obtain a second data packet, and send the second data packet to the data receiving end;

[0036] The kernel module is used to perform operation processing on the data to be processed to obtain the processed data, and send the processed data to the data packet processing module.

[0037] Optionally, it further includes: a first clock module, wherein:

[0038] The data packet processing module is further used to send the data to be processed to the first clock module;

[0039] The first clock module is used to perform clock conversion on the data to be processed, and send the converted data to be processed to the kernel module;

[0040] Correspondingly, it also includes: a second clock module, wherein:

[0041] The core module is further used to send the processed module to the second clock module;

[0042] The second clock module is used to perform the clock conversion on the processed data and cache the converted processed data, so that the data packet processing module obtains the converted processed data from the second clock module.

[0043] The present invention also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are loaded and executed by a processor, the data processing method as described above is implemented.

[0044] The present invention provides a data processing method, which is applied to an FPGA acceleration card, comprising: a data packet processing module unpacks a first data packet sent by a data sending end to obtain data to be processed, and sends the data to be processed to a kernel module; the kernel module performs operation processing on the data to be processed to obtain processed data, and sends the processed data to the data packet processing module; the data packet processing module performs packet processing on the processed data to obtain a second data packet, and sends the second data packet to a data receiving end.

[0045] It can be seen that in the present invention, after the data packet processing module completes the unpacking processing of the first data packet sent by the data sending end, it will directly send the obtained data to be processed to the kernel module for calculation processing, and will not write the data into the low-speed cache, which can avoid the low-speed cache read and write operations between data reception and data processing; in addition, after completing the calculation processing, the kernel module will directly send the processed data to the data packet processing module for packet processing and sending, and will not write the data into the low-speed cache, which can avoid the low-speed cache read and write operations from data processing to data sending. In other words, the present invention sets a direct data path between the data packet processing module and the kernel module, which can ensure that the FPGA acceleration card does not need to perform low-speed cache read and write operations before and after data processing, and can effectively avoid the efficiency loss of repeated cache read and write operations on the acceleration tasks of multiple acceleration cards, thereby improving the overall acceleration performance of multiple acceleration cards. The present invention also provides an FPGA acceleration card and a computer-readable storage medium, which have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0047] Figure 1 A flowchart of a data processing method provided by an embodiment of the present invention;

[0048] Figure 2 This is a structural block diagram of the first FPGA acceleration card provided by an embodiment of the present invention;

[0049] Figure 3a A structural block diagram of a second FPGA acceleration card provided by an embodiment of the present invention;

[0050] Figure 3b A structural block diagram of a third FPGA acceleration card provided by an embodiment of the present invention;

[0051] Figure 3c A structural block diagram of a first clock conversion queue provided by an embodiment of the present invention;

[0052] Figure 3d A structural block diagram of a second clock conversion queue provided by an embodiment of the present invention;

[0053] Figure 3e This is a structural block diagram of a fourth FPGA acceleration card provided by an embodiment of the present invention;

[0054] Figure 3f This is a structural block diagram of the fifth FPGA acceleration card provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In order to improve the parallel computing capability of the computing system, an FPGA acceleration card is usually used to share the CPU computing pressure to improve the performance of the entire computing system. In the related art, the FPGA acceleration card needs to send the original data to the low-speed cache area for storage before data processing, and then read the data from the cache for processing according to the needs of the kernel; after the processing is completed, the processed data needs to be cached to the above-mentioned low-speed cache area, and then read the data from the cache for sending according to the needs. In the acceleration task involving multiple acceleration cards, the above-mentioned reading and writing operations of the low-speed cache will consume a lot of time, thereby reducing the overall acceleration performance of the multiple acceleration cards. In view of this, the present invention provides a data processing method, which can set a direct data path between the data packet processing module and the kernel module to ensure that the FPGA acceleration card can directly process and send data, which can avoid the efficiency loss of the acceleration task of multiple acceleration cards caused by repeated reading and writing of the low-speed cache, thereby improving the overall acceleration performance of multiple acceleration cards. Please refer to Figure 1 , Figure 1 A flowchart of a data processing method provided by an embodiment of the present invention, which is applied to an FPGA accelerator card, may include:

[0057] S101. A data packet processing module unpacks a first data packet sent by a data sending end to obtain data to be processed, and sends the data to be processed to a kernel module.

[0058] In the related art, after the FPGA accelerator card completes the unpacking operation of the first data packet sent by the data transmitter, it does not directly send the obtained data to be processed to the kernel for processing, but writes it to the low-speed cache area, such as writing it to the host cache area (host cache area) through DMA (Direct Memory Access) technology, or writing it to the internal DDR cache area, and then taking it out of the cache area and processing it according to the needs of the kernel module (Kernel). In other words, in the related art, the kernel module needs to repeatedly perform the read operation on the low-speed cache to obtain the data to be processed, rather than directly receiving the data to be processed. It is understandable that the bandwidth of the host cache area and the DDR cache area is small, and the read and write delay is large. In a multi-accelerator card task, if the kernel of each accelerator card needs to perform the above-mentioned read operation on the slow cache, it will take a lot of time and reduce processing efficiency. In an embodiment of the present invention, a direct data path is set between the data packet processing module and the kernel module. The data packet processing module does not need to send the data to be processed to the cache module, and the kernel module does not need to perform a cache read operation. It only needs to receive the data to be processed and process it, which can save the time consumed by the cache read operation and improve the processing efficiency of multiple acceleration cards.

[0059] It should be noted that the embodiments of the present invention do not limit the specific form of the data path from the packet processing module to the kernel module. If the packet processing module and the kernel module use the same clock domain for data transmission, a simple data link can be used as the above data path; if the packet processing module and the kernel module use different clock domains for data transmission, the above data path can also be a clock module, and the clock module converts the data to be processed from the clock domain of the packet processing module to the clock domain of the kernel module. Considering that in general FPGA acceleration cards, the packet processing module and the kernel module usually use different clock domains for data transmission, in order to ensure that the two modules can correctly transmit data, it is usually necessary to set clock isolation between them. Therefore, the data path from the packet processing module to the kernel module can be a clock module.

[0060] In one possible scenario, sending the data to be processed to the kernel module may include:

[0061] Step 11: The data packet processing module sends the data to be processed to the first clock module;

[0062] Step 12: The first clock module performs clock conversion on the data to be processed, and sends the converted data to be processed to the kernel module.

[0063] It should be noted that the embodiment of the present invention does not limit the specific process of clock conversion, and reference may be made to the relevant technology of clock conversion. Further, in order to facilitate the first clock module to receive and process the data to be processed in an orderly manner, a cache queue may be set inside it for orderly receiving the data to be processed, and the clock processing part may also set a clock conversion queue for orderly converting the data to be processed.

[0064] In a possible scenario, the first clock module includes a cache queue and a first clock conversion queue, and the first clock module performs clock conversion on the data to be processed and sends the converted data to be processed to the kernel module, including:

[0065] Step 21: The cache queue caches the data to be processed;

[0066] Step 22: The first clock conversion queue performs clock conversion on the to-be-processed data obtained from the cache queue, and sends the converted to-be-processed data to the kernel module.

[0067] It should be clear that after the first clock conversion queue completes the clock conversion of the data to be processed, it actively sends the data to the kernel module, and the kernel module does not need to read from the first clock conversion queue. It should be noted that the embodiment of the present invention does not limit the amount of data that the cache queue and the first clock conversion queue can accommodate (i.e., the depth of the two queues), which can be set according to actual application requirements.

[0068] Further, it should be noted that the embodiments of the present invention do not limit the specific data sending end, for example, it can be a host machine that schedules the FPGA acceleration card to work. Of course, in a multi-acceleration card task, the data sending end can also be other FPGA acceleration cards. The way of transmitting data between the data sending end and the FPGA acceleration card can be, for example, transmitted through the network form, or transmitted through the PCIe form, where PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, which can be selected according to actual application requirements. It can be understood that in order to receive the first data packet, a corresponding communication controller needs to be set in the FPGA acceleration card. According to the above description, the communication controller can be either a MAC controller or a PCIe controller, which can be selected according to actual application requirements.

[0069] In a possible scenario, the data packet processing module unpacks the first data packet sent by the data sending end to obtain data to be processed, including:

[0070] Step 31: The data packet processing module obtains a first data packet through a communication controller; the communication controller includes a MAC controller or a PCIe controller;

[0071] Step 32: unpacking the first data packet to obtain data to be processed;

[0072] Furthermore, the embodiment of the present invention does not limit the unpacking process of the first data packet, and reference may be made to related technologies of data packaging and unpacking.

[0073] S102: The kernel module performs computation on the data to be processed to obtain processed data, and sends the processed data to the data packet processing module.

[0074] Similar to the way the FPGA accelerator card processes the data to be processed, in the related art, after the kernel module completes the computational processing of the data to be processed, it does not directly send it to the data packet processing module for packet processing and sending, but writes it to the cache area, such as the host cache or DDR cache, and then takes out the relevant data from the cache for packetization and sending according to the needs of the host machine that controls the FPGA accelerator card. Similarly, in a multi-accelerator card task, if each accelerator card needs to repeatedly perform the above-mentioned read operation on the slow cache when sending the processed data, it will take up a lot of time and reduce the processing efficiency. In an embodiment of the present invention, a direct data path is set between the data packet processing module and the kernel module. After the complete computational processing, the kernel module can directly send the obtained processed data to the data packet processing module for packetization and sending operations, which can avoid the data packet processing module from repeatedly memorizing the read and write operations of the low-speed cache, thereby saving the time consumed by the low-speed cache read operation and improving the processing efficiency of multiple accelerator cards.

[0075] It should be noted that the data path from the kernel module to the data packet processing module in the embodiment of the present invention is similar to the data path from the data packet processing module to the kernel module, and will not be repeated here. Similarly, similar to the process of sending the data to be processed from the data packet processing module to the kernel module, when the kernel module sends the processed data to the data packet processing module, clock conversion is also required, so the data path from the kernel module to the data packet processing module can also be a clock module.

[0076] In one possible scenario, sending the processed data to the data packet processing module may include:

[0077] Step 41: The core module sends the processed data to the second clock module;

[0078] Step 42: The second clock module performs clock conversion on the processed data, and caches the converted processed data, so that the data packet processing module obtains the converted processed data from the second clock module.

[0079] Similarly, in order to perform orderly clock conversion on the processed data, in an embodiment of the present invention, the second clock module may also include a clock conversion queue for orderly clock conversion on the processed data. Furthermore, in order to facilitate the data packet processing module to assemble packets and retransmit packets in the event of packet loss or error, a cache may be set in the second clock module. In order to improve the cache read and write efficiency, the cache may be a RAM inside the FPGA accelerator card, wherein the RAM (Random Access Memory), also called main memory, is an internal memory that directly exchanges data with the kernel module. It is understandable that the read and write speed of the RAM is much faster than the read and write speed of the host host cache area and the DDR cache, which can effectively reduce the efficiency loss caused by cache read and write.

[0080] In a possible scenario, the second clock module includes a RAM and a second clock conversion queue, and the second clock module performs clock conversion on the processed data and caches the converted processed data, which may include:

[0081] Step 51: the second clock conversion queue performs clock conversion on the processed data, and caches the converted processed data into the RAM;

[0082] Correspondingly, the data packet processing module obtains the converted processed data from the second clock module, including:

[0083] Step 61: The data packet processing module obtains the converted processed data from the RAM.

[0084] S103: The data packet processing module performs packet processing on the processed data to obtain a second data packet, and sends the second data packet to the data receiving end.

[0085] It is understandable that the data packet processing module can also send the second data packet to the data receiving end through the communication controller.

[0086] In a possible case, sending the second data packet to the data receiving end may include:

[0087] Step 71: The data packet processing module sends the second data packet to the data receiving end through the communication controller.

[0088] It should be noted that the limited description of the communication controller can refer to the above embodiment, which will not be repeated here; the embodiment of the present invention does not limit the packet processing process of the first data packet, and the relevant technologies of data packetization and unpacking can be referred to; the embodiment of the present invention does not limit the specific data receiving end, and the limited description of the data receiving end is consistent with the limited description of the data sending end, which will not be repeated here. It should be noted that in a multi-acceleration card task, each FPGA acceleration card is usually uniformly scheduled by the host machine. In other words, the data receiving end information corresponding to the FPGA acceleration card is uniformly scheduled and sent by the host machine. The above scheduling process is not limited here, and the relevant technologies of the multi-acceleration card task can be referred to.

[0089] Based on the above embodiments, in the present invention, after the data packet processing module completes the unpacking process of the first data packet sent by the data sending end, it will directly send the obtained data to be processed to the kernel module for calculation processing, and will not write the data into the low-speed cache, which can avoid the low-speed cache read and write operations between data reception and data processing; in addition, after the kernel module completes the calculation processing, it will directly send the processed data to the data packet processing module for packet processing and sending, and will not write the data into the low-speed cache, which can avoid the low-speed cache read and write operations from data processing to data sending. In other words, the present invention sets a direct data path between the data packet processing module and the kernel module, which can ensure that the FPGA acceleration card does not need to perform low-speed cache read and write operations before and after data processing, and can effectively avoid the efficiency loss of repeated cache read and write operations on the acceleration tasks of multiple acceleration cards, thereby improving the overall acceleration performance of multiple acceleration cards.

[0090] Based on the above embodiment, considering that the communication status between the host machine and the FPGA accelerator card, and between the FPGA accelerator cards may fluctuate, and the processing efficiency of each accelerator card may also fluctuate, in order to avoid the problem of being unable to process or data loss caused by the upstream device sending a large amount of data to be processed to a certain FPGA accelerator card when a bottleneck occurs, in an embodiment of the present invention, the FPGA accelerator card can also collect the remaining space of the cache queue and inform the data sending end so that the data sending end can make timely adjustments. In one possible situation, the data processing method can also include:

[0091] S201. The data packet processing module obtains the remaining space information of the cache queue, and encapsulates the remaining space information to obtain a response data packet.

[0092] An acknowledgment packet (ACK) is usually feedback information sent by one end of the communication when receiving data from the other end. In an embodiment of the present invention, in order to prevent the data sending end from sending a large amount of data that cannot be processed by this card, the data packet processing module will actively collect the remaining space information of the cache queue, and encapsulate the information into a response data packet and return it to the data sending end. In this way, after obtaining the remaining space information, the data sending end can understand the processing status of this FPGA acceleration card, and then adjust the flow of sending the first data packet. It should be noted that the embodiment of the present invention does not limit the specific form of the response data packet, and may refer to the relevant technology of network communication, as long as the response data packet can contain the remaining space information.

[0093] S202: Send the response data packet to the data sending end, so that the data sending end adjusts the flow of sending the first data packet by using the remaining space information.

[0094] Based on the above embodiments, the data packet processing module in the present invention can also collect the remaining space of the cache queue and inform the data sending end so that the data sending end can make timely adjustments, thereby avoiding the problem of being unable to process or data loss caused by the upstream device sending a large amount of data to be processed to a certain FPGA acceleration card when a bottleneck occurs.

[0095] Based on the above embodiment, in order to improve the compatibility of the FPGA acceleration card and facilitate its compatibility with the existing slow cache read and write mechanism when processing single-card tasks, in an embodiment of the present invention, a data selection module may also be set in the FPGA acceleration card to be compatible with the required data read and write mode according to actual needs. In a possible case, before sending the data to be processed to the kernel module, it may also include:

[0096] S301, the data packet processing module sends the data to be processed to the data selection module;

[0097] S302: The data selection module sends the data to be processed to the kernel module or the storage module according to preset configuration information.

[0098] The data selection module (MUX, Multiplexer) usually functions as a signal switch, and a corresponding register is provided inside it, and the corresponding data path can be selected according to the register configuration. The embodiment of the present invention can realize the read and write mechanism of the FPGA acceleration card to the existing slow cache by setting the data selection module. When the FPGA acceleration card needs to process data in the DMA working mode, or needs to cache data to the DDR cache, the data selection module can be configured so that the data packet processing module writes the data to be processed to the host host cache or DDR cache after completing the unpacking of the first data packet; of course, if it is necessary to improve the working efficiency of multiple acceleration cards, the data selector can also be configured so that the data packet processing module can directly send the data to be processed to the kernel module for processing after completing the unpacking of the first data packet. It should be noted that the embodiment of the present invention does not limit the specific preset configuration information of the data selection module register configuration, and can be set according to actual application requirements.

[0099] Similarly, for the data path from the kernel module to the data packet processing module, the above-mentioned data selection module can also be set to achieve the effect of improving the compatibility of the FPGA acceleration card.

[0100] Accordingly, it may also include:

[0101] S401. The data selection module obtains processed data from the kernel module or the storage module according to preset configuration information, and sends the processed data to the data packet processing module.

[0102] Based on the above embodiments, the present invention may also set a data selection module in the FPGA acceleration card to be compatible with the required data reading and writing modes according to actual needs, thereby improving the compatibility of the FPGA acceleration card and facilitating its compatibility with the existing slow cache reading and writing mechanism when processing single-card tasks.

[0103] The following is an introduction to the above data processing method based on the specific FPGA structure diagram. Figure 2 , Figure 2 This is a structural block diagram of the first FPGA acceleration card provided in an embodiment of the present invention.

[0104] 1. In the sending and receiving channels, add a clock conversion queue (clock conversion FIFO, FirstIn FirstOut) with cross-clock domain isolation to solve the asynchronous clock problem between the kernel module and the protocol packet processing module;

[0105] 2. After the kernel module processes the data, it is temporarily stored in the FPGA internal RAM after passing through the clock conversion queue for caching and packet assembly, as well as retransmission of lost or erroneous packets;

[0106] 3. In the receiving channel (i.e., the path between the receiving module and the kernel module, the receiving module is connected to the data packet processing module, and the data packet processing module is not drawn), a cache queue (cache FIFO) is added to temporarily store the parsed streaming acceleration data; at the same time, as the receiving end, the remaining depth of the cache queue will be used as the window value of the network flow control and fed back to the sending end in the form of a reply data packet (ACK packet);

[0107] 4. In the sending channel (i.e., the path between the sending module and the kernel module), add a data selection module (MUX module) to select the source of the data packet of the sending processing module, and switch the streaming data mode and the traditional DDR mode through register configuration; similarly, in the receiving channel, add a data selection module to select whether to store the valid data after receiving and parsing in the board DDR or in the internal RAM of the streaming mode.

[0108] An FPGA acceleration card and a computer-readable storage medium provided in an embodiment of the present invention are introduced below. The FPGA acceleration card and the computer-readable storage medium described below can be referenced to each other with the data processing method described above.

[0109] Please refer to Figure 3a , Figure 3a This is a structural block diagram of a second FPGA acceleration card provided by an embodiment of the present invention. The FPGA acceleration card may include: a data packet processing module 302 and a kernel module 301, wherein:

[0110] The data packet processing module 302 is used to unpack the first data packet sent by the data sending end to obtain data to be processed, and send the data to be processed to the kernel module 301; to pack the processed data sent by the kernel module 301 to obtain a second data packet, and send the second data packet to the data receiving end;

[0111] The kernel module 301 is used to perform operations on the data to be processed to obtain processed data, and send the processed data to the data packet processing module 302 .

[0112] Optionally, refer to Figure 3b , Figure 3b This is a structural block diagram of a third FPGA acceleration card provided by an embodiment of the present invention. The FPGA acceleration card may further include: a first clock module 303, wherein:

[0113] The data packet processing module 302 is also used to send the data to be processed to the first clock module 303;

[0114] The first clock module 303 is used to perform clock conversion on the data to be processed and send the converted data to be processed to the core module 301;

[0115] Accordingly, it also includes: a second clock module 304, wherein:

[0116] The kernel module 301 is also used to send the processed module to the second clock module 304;

[0117] The second clock module 304 is used to perform clock conversion on the processed data and cache the converted processed data, so that the data packet processing module 302 obtains the converted processed data from the second clock module 304 .

[0118] Optionally, refer to Figure 3c , Figure 3c The first clock conversion queue provided in the embodiment of the present invention is a structural block diagram. The first clock module 303 may include a cache queue 3031 and a first clock conversion queue 3032, wherein:

[0119] Cache queue 3031, used to cache data to be processed;

[0120] The first clock conversion queue 3032 is used to perform clock conversion on the to-be-processed data obtained from the cache queue 3031 , and send the converted to-be-processed data to the kernel module 301 .

[0121] Optionally,

[0122] The data packet processing module 302 can also obtain the remaining space information of the cache queue 3031, and encapsulate the remaining space information to obtain a response data packet; and send the response data packet to the data sending end so that the data sending end uses the remaining space information to adjust the flow of sending the first data packet.

[0123] Optionally, refer to Figure 3d , Figure 3d The second clock conversion queue provided in the embodiment of the present invention is a structural block diagram. The second clock module 304 may include a RAM 3042 and a second clock conversion queue 3041, wherein:

[0124] The second clock conversion queue 3041 is used to perform clock conversion on the processed data and cache the converted processed data into the RAM 3042;

[0125] Accordingly,

[0126] The data packet processing module 302 is further configured to obtain the converted processed data from the RAM 3042 .

[0127] Optionally, refer to Figure 3e , Figure 3eThis is a structural block diagram of a fourth FPGA acceleration card provided by an embodiment of the present invention. The FPGA acceleration card may further include: a communication controller 305, wherein the communication controller 305 includes a MAC controller or a PCIe controller, wherein:

[0128] The data packet processing module 302 can also be used to obtain a first data packet through the communication controller 305; unpack the first data packet to obtain data to be processed; and send a second data packet to a data receiving end through the communication controller 305.

[0129] Optionally, refer to Figure 3f , Figure 3f This is a structural block diagram of a fifth FPGA acceleration card provided by an embodiment of the present invention. The FPGA acceleration card may further include: a data selection module 306 and a storage module 307, wherein:

[0130] The data packet processing module 302 is used to send the data to be processed to the data selection module 306;

[0131] The data selection module 306 is used to send the data to be processed to the kernel module 301 or the storage module 307 according to the preset configuration information;

[0132] Accordingly,

[0133] The data selection module 306 is further configured to obtain processed data from the kernel module 301 or the storage module 307 according to preset configuration information, and send the processed data to the data packet processing module 302 .

[0134] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data processing method of any of the above embodiments are implemented.

[0135] Since the embodiments of the computer-readable storage medium part correspond to the embodiments of the data processing method part, please refer to the description of the embodiments of the data processing method part for the embodiments of the computer-readable storage medium part, which will not be repeated here.

[0136] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0137] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0138] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0139] The above is a detailed introduction to a data processing method, FPGA acceleration card and computer-readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A data processing method, characterized in that: Applied to FPGA accelerator cards, including: The data packet processing module unpacks the first data packet sent by the data sending end to obtain data to be processed, and sends the data to be processed to the first clock module; The first clock module performs clock conversion on the data to be processed in an orderly manner, and sends the converted data to be processed to the kernel module; The core module performs operation processing on the data to be processed to obtain processed data, and sends the processed data to the second clock module; The second clock module performs the clock conversion on the processed data and caches the converted processed data; wherein the second clock module includes a RAM, and the RAM is used to cache the processed data; The data packet processing module obtains the converted processed data from the second clock module, performs packet processing on the processed data to obtain a second data packet, and sends the second data packet to a data receiving end.

2. The data processing method according to claim 1, characterized in that: The first clock module includes a cache queue and a first clock conversion queue, and the first clock module performs clock conversion on the data to be processed and sends the converted data to be processed to the kernel module, including: The cache queue caches the data to be processed; The first clock conversion queue performs the clock conversion on the to-be-processed data obtained from the cache queue, and sends the converted to-be-processed data to the kernel module.

3. The data processing method according to claim 2, characterized in that: Also includes: The data packet processing module obtains the remaining space information of the cache queue, and performs the packet processing on the remaining space information to obtain a response data packet; The response data packet is sent to the data sending end, so that the data sending end uses the remaining space information to adjust the flow of sending the first data packet.

4. The data processing method according to claim 1, characterized in that: The second clock module includes a RAM and a second clock conversion queue, and the second clock module performs the clock conversion on the processed data and caches the converted processed data, including: The second clock conversion queue performs the clock conversion on the processed data, and caches the converted processed data into the RAM; Correspondingly, the data packet processing module obtains the converted processed data from the second clock module, including: The data packet processing module obtains the converted processed data from the RAM.

5. The data processing method according to claim 1, characterized in that: The data packet processing module unpacks the first data packet sent by the data sending end to obtain data to be processed, including: The data packet processing module obtains the first data packet through a communication controller; the communication controller includes a MAC controller or a PCIe controller; Unpacking the first data packet to obtain data to be processed; Correspondingly, the sending of the second data packet to the data receiving end includes: The data packet processing module sends the second data packet to the data receiving end through the communication controller.

6. The data processing method according to any one of claims 1 to 5, characterized in that: Before sending the data to be processed to the kernel module, the method further includes: The data packet processing module sends the data to be processed to the data selection module; The data selection module sends the to-be-processed data to the kernel module or the storage module according to preset configuration information; Accordingly, it also includes: The data selection module obtains the processed data from the kernel module or the storage module according to the preset configuration information, and sends the processed data to the data packet processing module.

7. An FPGA accelerator card, characterized in that: include: A data packet processing module, a kernel module, a first clock module, and a second clock module, wherein: The data packet processing module is used to unpack a first data packet sent by a data sending end to obtain data to be processed, and send the data to be processed to the kernel module; to pack the processed data sent by the kernel module to obtain a second data packet, and send the second data packet to the data receiving end; The kernel module is used to perform operation processing on the data to be processed to obtain the processed data, and send the processed data to the data packet processing module; It also includes: a first clock module, wherein: The data packet processing module is further used to send the data to be processed to the first clock module; The first clock module is used to perform clock conversion on the data to be processed in an orderly manner, and send the converted data to be processed to the kernel module; Correspondingly, it also includes: a second clock module, wherein: The kernel module is further used to send the processed data to the second clock module; The second clock module is used to perform the clock conversion on the processed data and cache the converted processed data, so that the data packet processing module obtains the converted processed data from the second clock module.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, the data processing method according to any one of claims 1 to 6 is implemented.

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