Overlay alignment method and system for direct writing photoetching
By selecting the first and second alignment marks in photolithography for preliminary alignment and correction, identifying the failure area of the correction model and splitting the layout, the overlay problem on distorted wafers is solved, improving photolithography accuracy and device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-16
- Publication Date
- 2026-04-14
AI Technical Summary
Existing photolithography technology cannot achieve effective overlay on distorted wafers, affecting the overall photolithography accuracy and device performance.
By selecting M of the N alignment marks as the first alignment marks, preliminary alignment is performed based on them, and the calibration coordinates and calibration error of the second alignment mark are calculated. The iteration stop condition is determined. If it is not met, the layout is split into sub-layouts, and alignment and correction are performed one by one until the optimal accuracy is achieved.
It significantly improves the overlay accuracy of distorted wafers, ensures device performance, and avoids efficiency loss by controlling the splitting depth, thus achieving a balance between accuracy, efficiency and robustness.
Smart Images
Figure CN121857255A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device manufacturing technology, specifically relating to an overlay alignment method and system for direct-write lithography. Background Technology
[0002] Photolithography is a core process in semiconductor device manufacturing, and one of its key objectives is to achieve precise overlay between multi-layer patterns. Ideally, overlay alignment is achieved by measuring pre-made alignment marks on the wafer, establishing a linear transformation model (usually including parameters such as translation, rotation, and scaling) between the layout design coordinate system and the wafer's physical coordinate system, and using this model to perform global correction on the exposed pattern, thus achieving high-precision pattern overlay across the entire wafer.
[0003] However, in many advanced manufacturing scenarios, wafers are prone to global warping and local nonlinear deformation due to high-temperature processes and heterogeneous material integration. Such distortions cause the global correction model based on a few alignment marks to fail, making it impossible for existing alignment methods to achieve effective overlay in the distorted area, thus affecting the overall lithography accuracy and device performance.
[0004] Therefore, there is an urgent need for a high-precision overlay alignment method that can effectively address wafer distortion. Summary of the Invention
[0005] In order to solve the above-mentioned problems in the prior art, the present invention provides an overlay alignment method and system for direct-write lithography.
[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides an overlay alignment method for direct-write lithography, comprising: S1. Obtain a wafer with alignment marks and a layout for photolithography; determine the target area to be photolithographically performed on the wafer based on the layout; S2. Select N alignment marks in the current target area, and take M of the N alignment marks as the first alignment marks, and the remaining alignment marks as the second alignment marks; N > M ≥ 3, M and N are both integers; the M first alignment marks are not on a straight line; S3. Perform preliminary alignment of the current target area based on the first alignment mark, and obtain the calibration coordinates of each second alignment mark after preliminary alignment, and calculate the calibration error of each second alignment mark; S4. Determine whether the iteration stop condition is met; the iteration stop condition includes: the calibration error of each second alignment mark is less than a preset accuracy threshold, or the number of alignment marks in the current target area is less than 2N; if the iteration stop condition is met, then align the current target area according to the first alignment mark and the second alignment mark in the current target area to expose the current target area; if the condition is not met, then execute step S5; S5. Under the premise of ensuring that it can be split, the current layout is split into multiple sub-layouts, the target area corresponding to each sub-layout is determined, and steps S2 to S5 are executed for each target area respectively; the premise of being split is that the number of alignment marks in the target area corresponding to each sub-layout after splitting is greater than or equal to N.
[0007] Optionally, 10 ≥ N ≥ 4.
[0008] Optionally, M=3, N=4.
[0009] Optionally, calculating the calibration error for each of the second alignment marks includes: Calculate the distance between the calibration coordinates and the corresponding actual coordinates of each second alignment mark, and use this distance as the calibration error of the second alignment mark.
[0010] Optionally, the step of dividing the current map into multiple sub-maps while ensuring divisibility specifically involves: While ensuring that the current territory can be split, split the current territory into two sub-territories.
[0011] Optionally, in step S5, the precondition for splitting further includes: the first alignment mark and the second alignment mark within the current target area are located within the target areas corresponding to different sub-plots after splitting.
[0012] Optionally, the method further includes: between step S1 and step S2, coating the wafer with photoresist.
[0013] In a second aspect, the present invention provides a direct-write lithography system, comprising: Support unit, used to hold a wafer with alignment marks; A photoresist coating unit is used to form a photoresist layer on the wafer; The data processing and control unit is used to execute the above-described overlay alignment method for direct-write lithography and generate instructions; An exposure unit is used to expose the photoresist layer according to the instructions.
[0014] This invention provides an overlay alignment method for direct-write lithography. It involves initial alignment using a first alignment mark, establishing a correction model, and calculating the calibration coordinates of a second alignment mark. The effectiveness of the correction model is verified using the second alignment mark. If the correction model fails (i.e., the error of the second alignment mark cannot meet the preset accuracy requirements), the current layout is divided into multiple sub-layouts. The alignment, verification, and decision-making process is then recursively executed on each sub-layout until all sub-layouts achieve optimal alignment accuracy. This invention uses the second alignment mark to identify the region where the current correction model fails and performs layout division. This transforms the complex global nonlinear correction problem into an approximately linear correction problem within a series of sub-layouts that can be accurately described by a simple model. Therefore, it significantly improves the overall overlay accuracy of the distorted wafer in principle, ensuring device performance.
[0015] Furthermore, this invention controls the partitioning depth by setting a preset iteration stopping condition (accuracy meets the standard or insufficient marking resources), avoiding the efficiency loss caused by infinite splitting. Thus, a controllable increase in computational load is used to achieve a decisive improvement in overlay yield. The overall process has a high cost-performance ratio and achieves a balance between accuracy, efficiency and robustness.
[0016] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0017] Figure 1 This is a flowchart of an overlay alignment method for direct-write lithography provided in an embodiment of the present invention. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0019] To address the problem that existing alignment methods cannot achieve effective overlay in distorted regions, thus affecting overall lithography accuracy and device performance, this invention provides an overlay alignment method and system for direct-write lithography.
[0020] First, a detailed description of an overlay alignment method for direct-write lithography provided by an embodiment of the present invention will be given. See also... Figure 1 The alignment method includes the following steps: S1. Obtain a wafer with alignment marks and a layout for photolithography; determine the target area to be photolithographically performed on the wafer based on the layout.
[0021] Specifically, a semiconductor wafer, such as a Si wafer, SiC wafer, or GaN wafer, that has already undergone front-end processes (e.g., photolithography, etching, implantation) is acquired. This wafer bears alignment marks for the underlying pattern. Simultaneously, the layout design of the layer to be photolithographically lithographically patterned is obtained, including the theoretical design coordinates of the photolithographic pattern and alignment marks. Then, based on the process plan, the area on the wafer to be exposed in this photolithography operation is determined, i.e., the target area. Initially, this target area typically corresponds to the area to be exposed on the entire wafer.
[0022] Next, photoresist is coated onto the wafer. Here, the wafer is sequentially cleaned and dried, bonded, coated with photoresist, and soft-baked to provide a clean, stable, and uniformly thick photoresist layer for subsequent exposure.
[0023] S2. Select N alignment marks in the current target area, and take M of the N alignment marks as the first alignment marks, and the remaining alignment marks as the second alignment marks; N > M ≥ 3, M and N are both integers; the M first alignment marks are not on a straight line.
[0024] Specifically, for example, the optical alignment sensor integrated into the direct-write device can identify available alignment marks within the current target area, and select N alignment marks for this alignment calculation. These N alignment marks are divided into two groups: M first alignment marks and NM second alignment marks. Here, the theoretical design coordinates of the selected M first alignment marks on the layout are not on the same straight line. The selection strategy can be random selection or selection based on the uniformity of the alignment mark distribution.
[0025] In one implementation, 10 ≥ N ≥ 4 to ensure there are enough sampling points.
[0026] In a preferred implementation, M=3 and N=4. That is, three first alignment marks and one second alignment mark are selected. M=3 represents the minimum requirement for establishing a correction model (i.e., a coordinate transformation model) and aligning the target region, while N=4 ensures that at least one alignment mark can be used to verify the validity of the correction model. This parameter combination minimizes the requirement for the number of alignment marks, greatly improving its applicability in regions with sparse or severely distorted alignment marks. Simultaneously, it minimizes computational burden, providing an efficient basis for recursive iteration and exhibiting high overall robustness.
[0027] S3. Perform preliminary alignment of the current target area based on the first alignment mark, and obtain the calibration coordinates of each second alignment mark after preliminary alignment, and calculate the calibration error of each second alignment mark.
[0028] Here, initial alignment is performed based on M first alignment marks. Specifically, the theoretical design coordinates of the M first alignment marks are obtained, and the actual coordinates of the first alignment marks on the wafer are measured using an optical alignment sensor. Then, a correction model between the theoretical design coordinates and the actual coordinates is solved using methods such as least squares and maximum likelihood estimation. Based on this correction model, the calibration coordinates of each second alignment mark are calculated, while simultaneously measuring the actual coordinates of each second alignment mark on the wafer. Based on the calibration coordinates and actual coordinates of each second alignment mark, the calibration error of each second alignment mark is calculated.
[0029] In one implementation, the calibration error for each second alignment mark is calculated, including: Calculate the distance between the calibration coordinates and the corresponding actual coordinates of each second alignment mark, and use this distance as the calibration error of that second alignment mark. That is: ; in, Indicates the index of the second alignment mark. Indicates the first The calibration coordinates of the second alignment mark, Indicates the first The actual coordinates of the second alignment mark Indicates the first The calibration error of the second alignment mark.
[0030] Here, the specific methods and steps for performing preliminary alignment based on the first alignment mark and calculating the calibration coordinates and calibration error of the second alignment mark can be referred to the relevant technologies of existing photolithography alignment methods, and will not be repeated in this invention.
[0031] S4. Determine whether the iteration stop condition is met. The iteration stop condition includes: the calibration error of each second alignment mark is less than the preset accuracy threshold, or the number of alignment marks in the current target area is less than 2N. If the iteration stop condition is met, the current target area is aligned according to the first and second alignment marks in the current target area to expose the current target area. If the condition is not met, proceed to step S5.
[0032] Specifically, if any stopping condition is met, it indicates that the current target area no longer needs further subdivision. Specifically, if the calibration error of each second alignment mark is less than a preset accuracy threshold, it means the current correction model is effective and meets the preset accuracy requirements. If the number of alignment marks in the current target area is less than 2N, it means the number of alignment marks in the current target area is insufficient and further subdivision is not supported. At this point, the system will re-align using the first and second alignment marks in the current target area to calculate an optimal, final correction model. The exposure module then exposes all graphics within the current target area based on this final correction model.
[0033] If no iteration stopping condition is met, it indicates that the current calibration model fails in a part of the current target region. Step S5 needs to be executed to split the region in order to determine a more accurate calibration model in the sub-region.
[0034] S5. Under the premise of ensuring that it can be split, split the current layout into multiple sub-layouts, determine the target area corresponding to each sub-layout, and perform steps S2 to S5 for each target area respectively; the premise of being split is that the number of alignment marks in the target area corresponding to each sub-layout after splitting is greater than or equal to N.
[0035] Specifically, the current layout is divided into multiple sub-layouts, ensuring that the number of alignment marks within the target area of each sub-layout is greater than or equal to N. This ensures that each sub-region still has enough alignment marks for the next round of alignment calculations. After the division, the target area of the wafer corresponding to each sub-layout is determined. Subsequently, steps S2 to S5 are recursively and independently repeated for each sub-layout and its target area. Each sub-region (i.e., the target area corresponding to the sub-layout) will independently undergo alignment mark selection, model building, error verification, and decision-making until the sub-region meets the iteration stopping condition in step S4 and finally completes the exposure. After all sub-regions have been exposed, the overall high-precision overlay exposure of the original target area is completed.
[0036] In a preferred implementation, the current layout is divided into multiple sub-layouts while ensuring that it is divisible, specifically: the current layout is divided into 2 sub-layouts while ensuring that it is divisible.
[0037] Preferably, the precondition for splitting further includes: the first alignment mark and the second alignment mark within the current target area are located within the target areas corresponding to different sub-plots after splitting. That is, the second alignment mark with a larger calibration error is grouped with the first alignment mark group into different sub-plots as much as possible. For example, a straight line passing through the vicinity of one or more second alignment marks with excessive errors and capable of achieving the above-mentioned group separation can be selected as the splitting boundary. It is understood that by physically isolating the second alignment mark area with verified large errors from the first alignment mark area used for initial alignment, each split sub-plot can be freed from the constraints of the original erroneous model, providing a foundation for establishing a new, more locally deformable correction model (i.e., a coordinate transformation model). This avoids invalid splitting in principle, ensuring the convergence and efficiency of subsequent iterative corrections.
[0038] Understandably, in the context of distorted wafers, this step separates regions with significant nonlinear deformation from the overall target region, with the deformation within each sub-region approaching linearity. This allows for extremely high local overlay accuracy using only the alignment marks within each sub-region as a simple local correction model. This step transforms the unsolvable global nonlinearity problem into a series of precisely controllable local linear correction problems, improving the overlay accuracy within each distorted region of the wafer.
[0039] Corresponding to the above-described overlay alignment method for direct-write lithography, this embodiment of the invention also provides a direct-write lithography system for performing the aforementioned overlay alignment method. The system may include: The carrier unit is used to hold the wafer with alignment marks.
[0040] Specifically, the support unit is typically a wafer stage with precise temperature control and vacuum adsorption capabilities. The support unit is used to fix and support the wafer with alignment marks, and can perform translation and rotation with nanometer-level precision under the command of the data processing and control unit.
[0041] The photoresist coating unit is used to form a photoresist layer on the wafer.
[0042] In this embodiment of the invention, the coating unit may be a separate spin coater or a processing module integrated with the carrier unit. The coating unit is used to perform adhesion enhancement, spin coating of photoresist and soft baking processes on the wafer surface to form a photoresist film that meets the requirements.
[0043] The data processing and control unit executes the aforementioned overlay alignment method for direct-write lithography and generates instructions. Specifically, the data processing and control unit receives alignment mark coordinate data from the sensor, runs the aforementioned overlay alignment method (including all logical steps such as mark selection, model building, error calculation, iterative judgment, and layout splitting), and finally generates control instructions containing the corrected pattern path and exposure parameters.
[0044] An exposure unit is used to expose the photoresist layer according to instructions.
[0045] During system operation, the carrier unit holds the wafer in place, and the photoresist coating unit applies the photoresist. Subsequently, the data processing and control unit dominates the entire overlay alignment process: it first acquires marking information using sensors integrated into the alignment sensing unit (typically part of the exposure unit or a separate module), and then executes the overlay alignment method of this invention. At each step of the algorithm decision, it dynamically controls the carrier unit to move to the target area and ultimately drives the exposure unit to sequentially expose patterns for each sub-region determined to meet the accuracy requirements. All units work collaboratively under a unified clock and coordinate reference to achieve high-precision overlay patterning.
[0046] This invention provides an overlay alignment method for direct-write lithography. It involves initial alignment using a first alignment mark, establishing a correction model, and calculating the calibration coordinates of a second alignment mark. The effectiveness of the correction model is verified using the second alignment mark. If the correction model fails (i.e., the error of the second alignment mark cannot meet the preset accuracy requirements), the current layout is divided into multiple sub-layouts. The alignment, verification, and decision-making process is then recursively executed on each sub-layout until all sub-layouts achieve optimal alignment accuracy. This invention uses the second alignment mark to identify the region where the current correction model fails and performs layout division. This transforms the complex global nonlinear correction problem into an approximately linear correction problem within a series of sub-layouts that can be accurately described by a simple model. Therefore, it significantly improves the overall overlay accuracy of the distorted wafer in principle, ensuring device performance.
[0047] Furthermore, this invention controls the partitioning depth by setting a preset iteration stopping condition (accuracy meets the standard or insufficient marking resources), avoiding the efficiency loss caused by infinite splitting. Thus, a controllable increase in computational load is used to achieve a decisive improvement in overlay yield. The overall process has a high cost-performance ratio and achieves a balance between accuracy, efficiency and robustness.
[0048] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0050] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0051] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for overlay alignment in direct-write lithography, characterized in that, include: S1. Obtain a wafer with alignment marks and a layout for photolithography; determine the target area to be photolithographically performed on the wafer based on the layout; S2. Select N alignment marks in the current target area, and take M of the N alignment marks as the first alignment marks, and the remaining alignment marks as the second alignment marks; N > M ≥ 3, M and N are both integers; the M first alignment marks are not on a straight line; S3. Perform preliminary alignment of the current target area based on the first alignment mark, and obtain the calibration coordinates of each second alignment mark after preliminary alignment, and calculate the calibration error of each second alignment mark; S4. Determine whether the iteration stopping condition is met; The iteration stop conditions include: the calibration error of each second alignment mark is less than a preset accuracy threshold, or the number of alignment marks in the current target area is less than 2N; if the iteration stop conditions are met, the current target area is aligned according to the first and second alignment marks in the current target area to expose the current target area; if the conditions are not met, step S5 is executed. S5. Under the premise of ensuring that it can be split, the current layout is split into multiple sub-layouts, the target area corresponding to each sub-layout is determined, and steps S2 to S5 are executed for each target area respectively; the premise of being split is that the number of alignment marks in the target area corresponding to each sub-layout after splitting is greater than or equal to N.
2. The overlay alignment method for direct-write lithography according to claim 1, characterized in that, 10≥N≥4。 3. The overlay alignment method for direct-write lithography according to claim 1, characterized in that, M=3, N=4.
4. The overlay alignment method for direct-write lithography according to claim 1, characterized in that, The calculation of the calibration error for each of the second alignment marks includes: Calculate the distance between the calibration coordinates and the corresponding actual coordinates of each second alignment mark, and use this distance as the calibration error of the second alignment mark.
5. The overlay alignment method for direct-write lithography according to claim 1, characterized in that, The process of dividing the current map into multiple sub-maps while ensuring its divisibility is specifically as follows: While ensuring that the current territory can be split, split the current territory into two sub-territories.
6. The overlay alignment method for direct-write lithography according to claim 5, characterized in that, In step S5, the precondition for splitting further includes: the first alignment mark and the second alignment mark within the current target area are located within the target areas corresponding to different sub-plots after splitting.
7. The overlay alignment method for direct-write lithography according to claim 1, characterized in that, The method further includes: between step S1 and step S2, coating the wafer with photoresist.
8. A direct-write lithography system, characterized in that, include: Support unit, used to hold a wafer with alignment marks; A photoresist coating unit is used to form a photoresist layer on the wafer; A data processing and control unit is used to execute the overlay alignment method for direct-write lithography as described in any one of claims 1 to 7, and to generate instructions; An exposure unit is used to expose the photoresist layer according to the instructions.