Apparatus and method for programming memory cells using coded TLC-fine

Abstract

The present invention is entitled "Programming Memory Cells Using Encoded TLC-Fine". The present invention discloses a memory device, which includes a control circuit, which is communicatively coupled to a non-volatile memory, configured to receive parity bits that have been stored using a data structure, and receive a first subset of host data including block data associated with a group of memory cells. The control circuit can be configured to perform a read operation to identify a second subset of host data including additional block data associated with the group of memory cells. The control circuit can be configured to decode the second subset of host data using the parity bits. The control circuit can be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the group of memory cells.

Description

Background Art

[0001] The present technology relates to the operation of memory devices.

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. In an EEPROM or flash NAND array architecture, the memory cells can be arranged in a matrix of rows and columns so that the gate of each memory cell is coupled to a word line through a row. The memory cells can be arranged together in strings so that the memory cells in a given string are coupled together in series from source to drain between a common source line and a common bit line. Summary of the invention

[0003] One aspect of the present invention relates to a storage device including a control circuit communicatively coupled to a non-volatile memory. The control circuit may be configured to receive a parity bit that has been stored using a data structure and to receive a first subset of host data including block data associated with a group of memory cells. The control circuit may be configured to perform a read operation to identify a second subset of host data including additional block data associated with the group of memory cells. The control circuit may be configured to decode the second subset of host data using the parity bit. The control circuit may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the group of memory cells.

[0004] Another aspect of the present invention relates to a method of performing a programming operation to program a group of memory cells, the method comprising receiving parity bits that have been stored using a data structure. The method also comprises receiving a first subset of host data including block data associated with the group of memory cells. The method also comprises performing a read operation to identify a second subset of host data including additional block data associated with the group of memory cells. The method also comprises decoding the second subset of host data using the parity bits. The method also comprises performing a write operation to write the block data to at least one or more memory cells that are part of the group of memory cells.

[0005] Another aspect of the present invention relates to a storage device including a non-volatile memory and a control circuit. The control circuit is communicatively coupled to the non-volatile memory. The control circuit can be used to program a group of memory cells. The control circuit can be configured to receive a parity bit that has been stored using a data structure. The control circuit can be further configured to receive a first subset of host data including block data for a top page, wherein the block data is associated with the group of memory cells. The control circuit can be further configured to perform a read operation to identify a second subset of the host data, the second subset of the host data including three other pages of additional block data associated with the group of memory cells. The control circuit can be further configured to decode the second subset of the host data using the parity bit. The control circuit can be further configured to perform a write operation to write the top page of the block data and the three other pages of the decoded additional block data to at least one or more memory cells that are part of the group of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of the present invention and, together with the description, serve to explain its principles. Where convenient, the same reference numerals will be used throughout the drawings to refer to the same or similar elements.

[0007] Figure 1A A block diagram of an exemplary memory device is shown.

[0008] Figure 1B A block diagram of an exemplary control circuit including a programming circuit, a counting circuit, and a determination circuit is shown.

[0009] Figure 2 Shown is a schematic diagram of a three memory string architecture in accordance with the principles of the present disclosure.

[0010] Figure 3 A block of memory cells in an exemplary two-dimensional configuration of the memory array of FIG. 1 is shown.

[0011] Figure 4A A cross-sectional view of an exemplary floating gate memory cell in a NAND string is shown.

[0012] Figure 4B A view taken along line 429 is shown. Figure 4A A cross-sectional view of the structure.

[0013] Figure 5A A cross-sectional view of an exemplary charge trapping memory cell in a NAND string is shown.

[0014] Figure 5B A view taken along line 429 is shown. Figure 5A A cross-sectional view of the structure.

[0015] Fig. 6A An exemplary block diagram of the sensing block SB1 of FIG. 1 is shown.

[0016] Figure 6B Another exemplary block diagram of the sensing block SB1 of FIG. 1 is shown.

[0017] Fig. 7A A perspective view of a group of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 is shown.

[0018] Figure 7B Shows Fig. 7A An exemplary cross-sectional view of a portion of one of the blocks.

[0019] Figure 7C Shows Figure 7B A graph of the memory hole diameters in a stack of FIG.

[0020] Fig.7D Shows Figure 7B A close up view of region 622 of the stack.

[0021] Fig. 8A Shows Figure 6B Top view of an exemplary word line layer WLL0 of the stack.

[0022] Figure 8B Shows Figure 7B Top view of an exemplary top dielectric layer DL19 of the stack.

[0023] Fig.9A Shows Fig. 8A Exemplary NAND strings in sub-block SBa to sub-block SBd.

[0024] Fig. 9B Another exemplary view of NAND strings in a sub-block is shown.

[0025] Fig.10 Vth distributions of memory cells in an exemplary programming operation with at least four data states are shown.

[0026] Fig.11 The application of a programming operation according to the principles of the present disclosure is schematically illustrated.

[0027] Fig.12 A set of threshold voltage distributions (Vth) for a 3-bit memory cell at various stages of a programming operation in accordance with the principles of the present disclosure is graphically illustrated.

[0028] Fig.13 is a flow chart illustrating an exemplary method for programming a group of memory cells. DETAILED DESCRIPTION

[0029] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used as limiting the scope of the present disclosure, including the claims. In addition, it will be appreciated by those skilled in the art that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of the present disclosure (including the claims) is limited to that embodiment.

[0030] A program-verify operation for a group of memory cells typically involves applying a series of programming voltages to the memory cells after providing the memory cells in an erased data state. Each programming voltage is provided in a programming loop (also referred to as a program-verify iteration). For example, the programming voltage may be applied to a word line that is connected to the control gate of the memory cell. In one method, incremental step pulse programming is performed, wherein the programming voltage increases the step size in each programming loop. A verification operation may be performed after each programming voltage to determine whether the memory cell has completed programming. When programming of a memory cell is completed, the memory cell may be locked from further programming while continuing to program other memory cells in subsequent programming loops. The program-verify operation may be a multi-step program-verify operation, a complete sequence or a one-step program-verify operation, or another type of program-verify operation.

[0031] Each memory cell may be associated with a data state according to the write data in the program command. The memory cell may be in an erased data state (referred to herein as the erased data state), or may be programmed to a programmed data state (referred to herein as the programmed data state) that is different from the erased data state. For example, in a memory device with two bits per cell, there are four data states, including an erased data state and three programmed data states, which are referred to as the A data state, the B data state, and the C data state (see FIG. 9 ). In a memory device with three bits per cell, there are eight data states, including an erased data state and seven programmed data states, which are referred to as the A data state, the B data state, the C data state, the D data state, the E data state, the F data state, and the G data state (see Fig.10). In a four-bit per cell memory device, there are sixteen data states, including an erased data state and fifteen programmed data states, which are referred to as Er data state, A data state, B data state, C data state, D data state, E data state, F data state, G data state, H data state, I data state, J data state, K data state, L data state, M data state, N data state, and O data state. These may also be numerically referred to as data state 0, data state 1, data state 2, data state 3, data state 4, data state 5, data state 6, data state 7, data state 8, data state 9, data state 10, data state 11, data state 12, data state 13, data state 14, and data state 15, respectively.

[0032] When a program command is issued, the write data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each programming data state is associated with a verification voltage, so that when a read (sensing) operation determines that its threshold voltage (Vth) is higher than the associated verification voltage, the memory cell with a given data state is considered to have completed programming. The read (sensing) operation can determine whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, so that the Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, so that the Vth is higher than the control gate voltage.

[0033] In some cases, such as when NAND flash memory is programmed, dedicated write methods have been applied to reduce program disturbance. In these cases, write data is written to the NAND memory through a multi-step programming operation that includes transferring the same write data to the NAND memory multiple times.

[0034] One conventional solution involves using a single-level cell (SLC) memory cache to store four pages of block data, and transferring the four pages of block data four times individually between various NAND components. For example, a conventional solution may involve transferring a first set of write data for multiple pages to a NAND memory, and writing the first set of write data to a first logical page (e.g., a memory cell may have four logical pages). Additionally, the conventional solution may be repeated for other logical pages. In this case, the first set of write data for the other pages is again transferred to the NAND memory, and the first set of write data is written to the other pages. However, implementing a programming operation utilizing this multiple transfer increases bus traffic and significantly degrades system performance.

[0035] Another conventional method does not require the use of an SLC cache to store and transfer four pages of block data. In this method, two pages of block data are written to the MLC cache during the first phase of the operation. During the second phase, these two pages are read back and the other two pages will be used for the fine part of the operation. Therefore, no SLC cache is required, and the four pages of block data are provided to the NAND memory only once in the two phases. However, this method requires a large internal data load (IDL) read margin and has a small final threshold voltage distribution (Vth) margin (relative to the first conventional programming operation described above) based on the large Vth difference between the first phase and the second phase.

[0036] Another conventional method involves transferring four pages of block data to a NAND memory during a first phase, generating parity bits capable of distinguishing between odd data states and even data states during the first phase, and using an SLC cache to store the parity bits. During a second phase, four pages of block data (i.e., fuzzy data) are read (e.g., without having to store the data in an SLC cache), and the data is decoded using parity bits. However, the method requires that data state n and data state n+2 do not have overlapping bits in order to read the data without error. This may be particularly difficult to achieve after a data retention (DR) process has been implemented on an open block memory cell. In yet another conventional method, three pages of block data are written during a first phase. During a second phase, three pages of block data are read back, and the fourth page is used for a fine part of the operation. However, the method requires a specific encoding scheme (e.g., a 1-2-6-6 encoding scheme, a 1-2-4-8 encoding scheme, etc.) with a large number of unbalanced data states on a page, thereby causing a large imbalance in the failure bit count (FBC) on the page.

[0037] Some embodiments described herein may include systems and / or methods for programming a group of memory cells using a TCL-fine programming operation. For example, during the first phase of the programming operation, three pages of block data are written to the memory cells to program the memory cells to eight data states (e.g., out of the sixteen available data states present in QLC). In parallel with the first phase, parity bits are generated and made accessible to control circuitry associated with the NAND memory structure. The parity bits may be stored using an SLC cache. During the second phase, the control circuitry (e.g., using a decoder) may have the data states read back from the first phase, and the data states may be decoded by using parity bits to distinguish between odd data states and even data states (sometimes referred to as n and n+1 data states). By decoding the three pages of block data, the three pages of block data may be combined with the top page of the block pages and written to the memory cells as part of the second phase of the programming operation.

[0038] In this manner, systems and / or methods for effectively and / or efficiently programming the group of memory cells are described. By programming the group of memory cells in the manner described above, the systems and / or methods reduce the number of SLC cache blocks required to store data and minimize data transfer within a memory device and / or between a memory device and a host device (e.g., relative to one or more conventional methods, such as fuzzy-fine programming operations). In addition, the systems and / or methods cause a small Vth shift between the first phase and the second phase (e.g., relative to the methods described above, such as MLC-fine programming operations), thereby improving programming performance and reducing neighbor word line interference (NWI) relative to the method.

[0039] Figure 1A 1 is a block diagram of an exemplary memory device. The memory device 100 may include one or more memory dies 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, sense blocks SB2, ... or, SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120, and between the controller and the one or more memory dies 108 via a line 118.

[0040] The memory structure may be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, the one or more memory cell arrays including a 3D array. The memory structure may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, without an intervening substrate. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of a memory cell array having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0041] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations.

[0042] The storage area 113 may, for example, be provided for programming parameters. The programming parameters may include a programming voltage, a programming voltage bias, a location parameter indicating the location of a memory cell, a contact wire connector thickness parameter, a verification voltage, etc. The location parameter may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. The contact wire connector thickness parameter may indicate the thickness of the contact wire connector, the substrate or material constituting the contact wire connector, etc.

[0043] An on-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. A power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module may include drivers for the word lines, SGS transistors, and SGD transistors and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0044] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit that is configured to perform the actions described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoder 114 / 132, the power control module 116, the sense block SBb, the sense block SB2, ... or the sense block SBp, the read / write circuit 128, the controller 122, etc., or a combination thereof.

[0045] The control circuit may include a programming circuit configured to perform a programming operation on a group of memory cells, wherein the group of memory cells includes memory cells assigned to represent one data state of multiple data states, and memory cells assigned to represent another data state of multiple data states; the programming operation includes multiple program-verify iterations; and in each program-verify iteration, the programming circuit performs programming on one word line, after which the programming circuit applies a verification signal to the one word line. The control circuit may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuit may also include a determination circuit configured to determine a specific program-verify iteration of the multiple program-verify iterations based on an amount by which the count exceeds a threshold, in which a verification test is performed on the other data state of the memory cells assigned to represent the other data state.

[0046] For example, Figure 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151 , a counting circuit 152 , and a determination circuit 153 .

[0047] The off-chip controller 122 may include a processor 122c, a storage device (memory) such as a ROM 122a and a RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, there may be uncorrectable errors in some cases. The technology provided herein reduces the possibility of uncorrectable errors.

[0048] The storage device includes code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein.Alternatively or additionally, the processor may access code from the storage device 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0049] For example, the controller can use code to access the memory structure, such as for programming operations, read operations and erase operations. The code may include startup code and control code (e.g., a set of instructions). Boot code is software that initializes the controller and enables the controller to access the memory structure during the boot or startup process. The controller can use code to control one or more memory structures. When powered on, the processor 122c takes out the boot code from ROM 122a or storage device 126a for execution, and the boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes a driver that performs basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0050] Generally speaking, the control code may include instructions to perform the functions described herein, including the steps of the flow charts discussed further below, and provide voltage waveforms, including those discussed further below.

[0051] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable storage devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0052] In addition to NAND memory, other types of non-volatile memory may be used.

[0053] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a non-volatile memory device may be configured in a NAND configuration or a NOR configuration.

[0054] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and non-volatile memory device components, which in some embodiments include components including charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0055] Multiple memory elements may be configured so that they are connected in series or so that each element can be accessed individually. By way of non-limiting example, a non-volatile memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0056] A NAND memory array can be configured so that the array consists of multiple memory strings, where the string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0057] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of the memory elements are formed, or it may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0058] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0059] The three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in x, y and z directions, wherein the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0060] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), wherein each column has a plurality of memory cells. The columns may be arranged in a two-dimensional configuration, such as in an xy plane, resulting in a three-dimensional arrangement of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0061] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0062] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between the memory device levels.

[0063] The two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0064] Figure 2 Schematic diagrams of exemplary BiCS memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 shows a schematic diagram of an exemplary BiCS 4 memory architecture, reference numeral 203 shows a schematic diagram of an exemplary BiCS 5 memory architecture, and reference numeral 205 shows a schematic diagram of an exemplary BiCS 6 memory architecture. In some embodiments, as shown, a BiCS memory architecture can include an array of interleaved NAND strings.

[0065] Referring to the memory architecture 201, the memory strings are shown in rows 207-0 to 207-7 in the string architecture 201. The memory string may include a group of memory cells (e.g., the group of memory cells corresponds to a group of memory holes). Each row is shown as having four ends of the memory string. The memory string may be connected to an adjacent string at the end (not visible below this view). The first group of rows 207-0 to 207-3 shown on the left side of the virtual row 208. The second group of rows 207-4 to 207-7 shown on the right side of the virtual row 208. The virtual row 208 separates the two groups of rows in eight staggered rows. The source line 209 is positioned at the edge of the first group and away from the virtual row 208. The source line 210 is positioned at the edge of the second group and away from the virtual row 208 and the source line 209.

[0066] Memory architecture 203 and memory architecture 205 may be similar to the memory architecture of string architecture 201, except that additional groups are added. String architecture 203 may be twice the size of architecture 201, and may include sixteen rows of strings, where each group of four rows is separated by a dummy row. String architecture 205 may be larger than both memory architecture 201 and memory architecture 203. String architecture 205 may include twenty rows of strings, where each group of four rows is separated by a dummy row 208.

[0067] In some embodiments, memory architecture 201, memory architecture 203, and / or memory architecture 205 may include a chip below the array structure. For example, memory architecture 201, memory architecture 203, and / or memory architecture 205 may include a chip below the array structure, whereby the control circuitry is below the memory array including the set of memory strings. With a chip below the array structure, the memory strings may include direct strap contacts for source lines for read and erase operations.

[0068] In some embodiments, the memory architecture 205 can be a BiCS 6 memory architecture. For example, in a BiCS 6 memory architecture, there can be five NAND string groups. NAND string group 212-1, NAND string group 212-2, NAND string group 212-3, NAND string group 212-3, and NAND string group 212-4). NAND string group 212-0 and NAND string group 212-4 can be referred to as external NAND string groups. NAND string group 212-1, NAND string group 212-2, and NAND string group 212-3 can be collectively referred to as internal NAND string groups. NAND string group 212-2 can be referred to as the innermost NAND string group.

[0069] In some embodiments, the BiCS 6 memory architecture can be a 3-D memory architecture that includes one or more 3-D blocks. In this case, the 3-D block can be logically segmented into multiple sub-blocks corresponding to the NAND string groups. The 3-D block can also be segmented into multiple planes. Additional block descriptions are also provided herein.

[0070] Although one or more embodiments relate to a BiCS memory architecture, it should be understood that this is provided by way of example. In practice, the techniques described herein may be implemented on any number of different memory architectures, such as a tubular BiCS (P-BiCS), a vertical recessed array transistor (VRAT) architecture, and / or any other type of EEPROM or flash memory architecture.

[0071] Figure 3 Blocks of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array may include many blocks. Each exemplary block 300, exemplary block 310 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1, ... or shared between blocks. Each NAND string is connected to a drain select gate (SGD) at one end, and the control gate of the drain select gate is connected via a common SGD line. The NAND strings are connected to a source select gate at their other end, which is then connected to a common source line 320. Sixteen word lines, such as WL0 to WL15, extend between the source select gate and the drain select gate. In some cases, a dummy word line that does not contain user data may also be used in a memory array adjacent to a select gate transistor. Such a dummy word line can shield edge data word lines from certain edge effects.

[0072] One type of nonvolatile memory that can be provided in a memory array is floating gate memory. Figure 4A and Figure 4BOther types of nonvolatile memory may also be used. For example, a charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. See Figure 5A and Figure 5B . A triple layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, in which a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0073] In another approach, an NROM cell is used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0074] Figure 4A A cross-sectional view of an exemplary floating gate memory cell in a NAND string is shown. The bit line or NAND string direction goes into the page, and the word line direction is from left to right. For example, word line 424 extends across a NAND string that includes a corresponding channel region 406, a channel region 416, and a channel region 426. Memory cell 400 includes a control gate 402, a floating gate 404, a tunnel oxide layer 405, and a channel region 406. Memory cell 410 includes a control gate 412, a floating gate 414, a tunnel oxide layer 415, and a channel region 416. Memory cell 420 includes a control gate 422, a floating gate 421, a tunnel oxide layer 425, and a channel region 426. Each memory cell is in a different corresponding NAND string. An inter-polysilicon dielectric (IPD) layer 428 is also shown. The control gate is part of the word line. Figure 4B A cross-sectional view along the contact line connector 429 is provided in FIG.

[0075] The control gate is wrapped around the floating gate, thereby increasing the surface contact area between the control gate and the floating gate. This causes a higher IPD capacitance, which results in a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices are scaled down, the spacing between adjacent cells becomes smaller, so there is little room for the control gate and IPD between two adjacent floating gates.

[0076] As another option, Figure 5A and Figure 5B As shown, a flat or planar memory cell has been developed in which the control gate is flat or planar; that is, it does not wrap around the floating gate, and its only contact with the charge storage layer is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is much thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic electron transfer, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0077] Figure 5B The contact line connector 529 is shown Figure 5A 5. A cross-sectional view of the structure of NAND string 530 includes SGS transistor 531, exemplary memory cell 500, exemplary memory cell 533, exemplary memory cell 534, and exemplary memory cell 535, and SGD transistor 536. As an example of each memory cell, memory cell 400 includes control gate 402, IPD layer 428, floating gate 404, and tunnel oxide layer 505, which is similar to Figure 5A The channel in the IPD layer in the SGS transistor and the SGD transistor allows the control gate layer and the floating gate layer to communicate. For example, the control gate layer and the floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0078] The NAND string may be formed on a substrate including a p-type substrate region 555, an n-type well 556, and a p-type well 557. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be directly applied to the channel region of the substrate.

[0079] Fig. 6AAn exemplary block diagram of the sense block SB1 of FIG. 1 is shown. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuit 650a, exemplary sense circuit 651a, exemplary sense circuit 652a, and exemplary sense circuit 553a are associated with data latch 650b, data latch 551b, data latch 652b, and data latch 653b, respectively. In one approach, different corresponding sense blocks may be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and processed by the corresponding processors in each sense block. For example, a sense circuit controller 660 in SB1 may communicate with the group of sense circuits and latches. The sense circuit controller may include a precharge circuit 661 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, the voltage is provided, for example, via a data bus 603 and a local bus such as Figure 6B LBUS1 or LBUS2 in is independently provided to each sensing circuit. In another possible method, for example, via Figure 6B The contact line 605 in the sense circuit provides a common voltage to each sense circuit at the same time. The sense circuit controller may also include a memory 662 and a processor 663. The memory 662 may store code that can be executed by the processor to perform the functions described herein. These functions may include reading a latch associated with the sense circuit, setting a bit value in the latch, and providing a voltage for setting a precharge level in a sense node of the sense circuit. Further example details of the sense circuit controller and the sense circuit 650a and the sense circuit 651a are provided below.

[0080] For example, the sense circuit controller may communicate with the different sense circuits in a time multiplexed manner, for example.In one approach, the contact wire 605 may be connected to a voltage clamp in each sense circuit.

[0081] The sensing circuit 651a includes a latch 651b, which includes a trip latch 646, an offset verification latch 647, and a data state latch 648. The voltage clamp 641 can be used to set a precharge voltage at the sensing node 642. The sensing node to bit line (BL) switch 643 selectively allows the sensing node to communicate with the bit line 645, and the voltage clamp 644 can set a voltage on the bit line. The bit line 645 is connected to one or more memory cells, such as memory cell MC2. The local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 651b and the voltage clamp. In order to communicate with the sensing circuit 651a, the sensing circuit controller provides a voltage to the transistor 606 via the contact line 601 to connect LBUS2 to DBUS.

[0082] Sense circuit 650a may be a first sense circuit including first trip latch 626 , and sense circuit 651a may be a second sense circuit including second trip latch 646 .

[0083] Sense circuit 650A is an example of a first sense circuit including a first sense node 622, wherein the first sense circuit is associated with a first memory cell MC1 and a first bit line 625. Sense circuit 651A is an example of a second sense circuit including a second sense node 642, wherein the second sense circuit is associated with a second memory cell MC2 and a second bit line 645.

[0084] Figure 6B 1 shows another exemplary block diagram of the sensing block SB1. The sensing circuit controller 660 communicates with a plurality of sensing circuits including an exemplary sensing circuit 650a and an exemplary sensing circuit 651a, such as Fig. 6A As shown. The sensing circuit 650a includes a latch 650b, which includes a trip latch 626, an offset verification latch 627, and a data state latch 628. The sensing circuit also includes a voltage clamp 621, such as a transistor, which sets a precharge voltage at a sensing node 622. A sensing node to bit line (BL) switch 623 selectively allows the sensing node to communicate with a bit line 625, for example, the sensing node is electrically connected to the bit line so that the sensing node voltage can decay. The bit line 625 is connected to one or more memory cells, such as memory cell MC1. The voltage clamp 624 can set the voltage on the bit line, such as during a sensing operation or during a programming voltage. The local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as in some cases communicating with the latch 650b and the voltage clamp. In order to communicate with the sensing circuit 650a, the sensing circuit controller provides a voltage to the transistor 604 via the contact line 602 to connect LBUS1 to the data bus DBUS 603. Communication may include sending data to the sensing circuit and / or receiving data from the sensing circuit.

[0085] Fig. 7A1 is a perspective view of a group of blocks 700 in an exemplary three-dimensional configuration of the memory array 126 of FIG. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements), and a peripheral region 704 with circuits for use with the blocks. For example, the circuit may include a voltage driver 705 that can be connected to the control gate layer of the block. In one approach, the control gate layers at a common height in the block are driven together. The substrate 701 can also carry the circuit below the block together with one or more lower metal layers, which are patterned in a conductive path to carry the signal of the circuit. These blocks are formed in the middle region 702 of the memory device. In the upper region 703 of the memory device, one or more upper metal layers are patterned in a conductive path to carry the signal of the circuit. Each block includes a stacked region of memory cells, wherein the stacked alternating layers represent word lines. In one possible approach, each block has an opposite layered side, and a vertical contact extends upward from the layered side to the upper metal layer to form a connection with the conductive path. Although four blocks are shown as an example, two or more blocks extending in the x-direction and / or the y-direction may be used.

[0086] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device.

[0087] Figure 7B Shows Fig. 7A An exemplary cross-sectional view of a portion of one of the blocks. The block includes a stack 710 of alternating conductive layers and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to data word line layers (word lines) WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. In addition, a region of a stack including NAND string NS1 and NAND string NS2 is shown. Each NAND string includes a memory hole 718 or a memory hole 719 filled with material that forms a memory cell adjacent to the word line. In Fig.7D Region 722 of the stack is shown in more detail in FIG.

[0088] The stack includes a substrate 711, an insulating film 712 on the substrate, and a portion of a source line SL. NS1 has a source terminal 713 at the bottom 714 of the stack and a drain terminal 715 at the top 716 of the stack. Contact line connectors (e.g., slits, such as metal-filled slits) 717 and contact line connectors 720 can be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a specific contact line above the stack. The contact line connectors can be used during the formation of the word lines and subsequently filled with metal. A portion of the bit line BL0 is also shown. A conductive via 721 connects the drain terminal 715 to BL0.

[0089] Figure 7C Shows Figure 7B The vertical axis is plotted against Figure 7B The stack is aligned and the width (wMH), eg, diameter, of memory hole 718 and memory hole 719 are shown. Fig. 7A The word line layer WLL0 to the word line layer WLL10 of the stack are repeated as an example and are at corresponding heights z0 to z10 in the stack. In such memory devices, the memory hole etched through the stack has a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory hole may have a circular cross-section. Due to the etching process, the memory hole width may vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, so that the diameter of the memory hole widens slightly before taper from its top to its bottom.

[0090] Due to the width of the memory hole, the programming speed (including programming slope and erase speed) of the memory cell can vary based on the position of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For smaller diameter memory holes, the electric field across the tunnel oxide is relatively strong, so that the programming and erase speeds are relatively high. One approach is to define groups of adjacent word lines with similar memory hole diameters (e.g., within a defined diameter range) and apply an optimized verification scheme for each word line in the group. Different groups can have different optimized verification schemes.

[0091] Fig.7D Shows Figure 7B722 of the stack of memory cells. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 780 and SGD transistors 781 are provided above dummy memory cells 782 and 783 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of the memory hole 730 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., a column formed by the material within the memory hole) may include a charge trapping layer or film 763 (such as SiN or other nitrides), a tunnel layer 664, a polysilicon body or channel 765, and a dielectric core 766. The word line layer may include a blocking oxide / block high-k material 760, a metal barrier layer 761, and a conductive metal 762 (such as tungsten) as a control gate. For example, control gates 790, 791, 792, 793, and 794 are provided. In this example, all layers except the metal are provided in the memory hole. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form a pillar-shaped active area (AA) of the NAND string.

[0092] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0093] Each of the memory holes may be filled with a plurality of annular layers, the annular layers including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and a word line in each of the memory holes.

[0094] The NAND string can be considered to have a floating channel because the length of the channel is not formed on the substrate. In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0095] Fig. 8A Shows Figure 7B00143] A top view of an exemplary word line layer WLL0 of a stack of. As mentioned, a 3D memory device may include a stack of alternating conductive layers and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layers for SG transistors are SG layers, and the layers for memory cells are word line layers. In addition, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. The source line is connected to the NAND string below the stack and the bit line is connected to the NAND string above the stack.

[0096] The block BLK in the 3D memory device can be divided into sub-blocks, each of which includes a NAND string group with a common SGD control line. For example, refer to the SGD line / control gate SGD0, SGD line / control gate SGD1, SGD line / control gate SGD2 and SGD line / control gate SGD3 in sub-block SBa, sub-block SBb, sub-block SBc and sub-block SBd, respectively. In addition, the word line layer in the block can be divided into regions. Each region is in a corresponding sub-block and can extend between contact line connectors (e.g., slits), which are periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The processing may include replacing the sacrificial material of the word line layer with metal. In general, the distance between the contact line connectors should be relatively small to take into account the limitation of the distance that the etchant can travel laterally to remove the sacrificial material, and the metal can travel to fill the gap created by removing the sacrificial material. For example, the distance between the contact line connectors can allow several rows of memory holes to exist between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider the limit on the number of bit lines that can be extended across the area when each bit line is connected to a different memory cell.After processing the word line layer, the contact line connectors can optionally be filled with metal to provide interconnection through the stack.

[0097] In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into region WLL0a, region WLL0b, region WLL0c, and region WLL0d, each of which is connected by a connector 813. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 813 is then connected to a voltage driver for the word line layer. Region WLL0a has exemplary memory holes 810 and exemplary memory holes 811 along contact line 812. Region WLL0b has exemplary memory holes 814 and exemplary memory holes 815. Region WLL0c has exemplary memory holes 816 and exemplary memory holes 817. Region WLL0d has exemplary memory holes 818 and exemplary memory holes 819. Memory holes are also Figure 8B Each memory hole can be part of a corresponding NAND string. For example, memory hole 810, memory hole 814, memory hole 816, and memory hole 818 can be part of NAND string NS0_SBa, NAND string NS1_SBb, NAND string NS2_SBc, NAND string NS3_SBd, and NAND string NS4_SBe, respectively.

[0098] Each circle represents a cross section of a memory hole at a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cell 820 and memory cell 821 are in WLL0a, memory cell 824 and memory cell 825 are in WLL0b, memory cell 826 and memory cell 827 are in WLL0c, and memory cell 828 and memory cell 829 are in WLL0d. These memory cells are at a common height in the stack.

[0099] Contact line connectors (e.g., slots, such as metal-filled slots) 801, 802, 803, and 804 may be located between and adjacent to the edges of regions WLL0a-WLL0d. The contact line connectors provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device. See also Fig.9A In order to understand Fig. 8A Further details of sub-blocks SBa to SBd.

[0100] Figure 8B Shows Figure 7B1. A top view of an exemplary top dielectric layer DL19 of a stack of . The dielectric layer is divided into region DL19a, region DL19b, region DL19c, and region DL19d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in one region of the word line layer to be programmed simultaneously, where each memory cell is in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or prohibit programming during each programming voltage.

[0101] Region DL19a has an exemplary memory hole 810 and an exemplary memory hole 811 along a contact line 812a that coincides with bit line BL0. Many bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 is connected to a group of memory holes, which includes memory hole 811, memory hole 815, memory hole 817, and memory hole 819. Another exemplary bit line BL1 is connected to a group of memory holes, which includes memory hole 810, memory hole 814, memory hole 816, and memory hole 818. Also shown is Fig. 8A 801, 802, 803, and 804 as they extend vertically through the stack. The bit lines may be numbered in the order BL0 to BL23 across the DL19 layer in the x-direction.

[0102] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in an adjacent row of cells adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in an adjacent row of memory cells adjacent to the first row at the left hand edge.

[0103] Fig.9A Shows Fig. 8A The exemplary NAND strings in the sub-block SBa to the sub-block SBe. Figure 7BThe conductive layers in the stack are shown for reference on the left hand side. Each sub-block includes multiple NAND strings, of which one exemplary NAND string is shown. For example, SBa includes an exemplary NAND string NS0, SBb includes an exemplary NAND string NS1, SBc includes an exemplary NAND string NS2, SBd includes an exemplary NAND string NS3, and SBe includes an exemplary NAND string NS4.

[0104] In addition, NS0_SBa includes SGS transistors 900 and 901, dummy memory cells 902 and 903, data memory cells 904, data memory cells 905, data memory cells 906, data memory cells 907, data memory cells 908, data memory cells 909, data memory cells 910, data memory cells 911, data memory cells 912, data memory cells 913 and 914, dummy memory cells 915 and 916, and SGD transistors 917 and 918.

[0105] NS1_SBb includes SGS transistors 920 and 921, dummy memory cells 922 and 923, data memory cells 924, data memory cells 925, data memory cells 926, data memory cells 927, data memory cells 928, data memory cells 929, data memory cells 930, data memory cells 931, data memory cells 932, data memory cells 933 and 934, dummy memory cells 935 and 936, and SGD transistors 937 and 938.

[0106] NS2_SBc includes SGS transistors 940 and 941, dummy memory cells 942 and 843, data memory cells 944, data memory cells 945, data memory cells 946, data memory cells 947, data memory cells 948, data memory cells 949, data memory cells 950, data memory cells 951, data memory cells 952, data memory cells 953 and data memory cells 954, dummy memory cells 955 and 956, and SGD transistors 957 and 958.

[0107] NS3_SBd includes SGS transistors 960 and 961, dummy memory cells 962 and 963, data memory cells 964, data memory cells 965, data memory cells 966, data memory cells 967, data memory cells 968, data memory cells 969, data memory cells 970, data memory cells 971, data memory cells 972, data memory cells 973 and 974, dummy memory cells 975 and 976, and SGD transistors 977 and 978.

[0108] NS4_SBe includes SGS transistors 980 and 981, dummy memory cells 982 and 983, data memory cells 984, data memory cells 985, data memory cells 986, data memory cells 987, data memory cells 988, data memory cells 989, data memory cells 980, data memory cells 981, data memory cells 982, data memory cells 983 and data memory cells 984, dummy memory cells 985 and 986, and SGD transistors 987 and 988.

[0109] At a given height in the block, the memory cells in each sub-block are at a common height. For example, a group of memory cells (including memory cell 904) are in a plurality of memory cells formed along a tapered memory hole in a stack of alternating conductive layers and dielectric layers. A group of memory cells is at a specific height z0 in the stack. Another group of memory cells (including memory cell 924) connected to one word line (WLL0) is also at a specific height. In another approach, another group of memory cells (e.g., including memory cell 912) connected to another word line (e.g., WLL8) is at another height (z8) in the stack.

[0110] Fig. 9BAnother exemplary view of a NAND string in a sub-block is shown. The NAND string includes NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe with 48 word lines (e.g., WL0 to WL47). Each sub-block includes a NAND string group that extends in the x direction and has a common SGD line, such as SGD0, SGD1, SGD2, SGD3, or SGD4. In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. NAND string NS0_SBa, NAND string NS1_SBb, NAND string NS2_SBc, NAND string NS3_SBd, and NAND string NS4_SBe are in sub-block SBa, sub-block SBb, sub-block SBc, sub-block SBd, and sub-block SBe, respectively. In addition, an exemplary group of word line G0, word line G1, and word line G2 is shown.

[0111] Fig.10 Waveforms for an exemplary programming operation are shown. The horizontal axis shows the programming cycle number, and the vertical axis shows the programming voltage value and the programming verification value. The programming voltage (Vpgm) may include a word line voltage (WLVpgm) and / or a bit line voltage (BLVpgm). In general, a programming operation may involve applying a pulse train to a selected word line, where the pulse train includes a plurality of program-verify (PV) iterations. The programming portion of a PV iteration includes a programming voltage, and the verification portion of a PV iteration includes one or more verification voltages.

[0112] For each programming voltage, a square wave is shown for simplicity, but other shapes are possible, such as a multi-level shape or a ramp shape. In addition, incremental step pulse programming (ISPP) is used in this example, in which the programming voltage is incremented in each consecutive programming cycle. This example uses ISPP in a single programming step in which programming is completed. It is also possible to use ISPP in each programming step of a multi-step operation.

[0113] The pulse train typically includes programming voltages that are gradually increased in magnitude using a voltage bias (dVpgm) in each programming-verification iteration. The voltage bias may be, for example, a word line voltage bias. A new pulse train may be applied in each programming step of a multi-step programming-verification operation, starting with an initial programming voltage (e.g., initial Vpgm) and ending with a final programming voltage (e.g., final Vpgm) that does not exceed a threshold voltage Vth (e.g., a maximum allowed value). The initial programming voltage may be the same or different in different programming steps. The final programming voltage may also be the same or different in different programming steps. The voltage bias may be the same or different in different programming steps. In some cases, a smaller voltage bias is used in the final programming step to reduce the Vth distribution width.

[0114] Pulse train 1000 includes a series of programming voltages 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, and 1015 applied to a word line selected for programming and an associated group of non-volatile memory cells. In the example shown, for example, one verification voltage, two verification voltages, or three verification voltages are provided after each programming voltage based on the number of target data states being verified. The number of target data states being verified can, for example, correspond to the number of memory cells associated with the word line. The programming voltage and the corresponding verification voltage can be separated by applying 0V to the selected word line between the programming voltage and the verification voltage.

[0115] In the example shown, the A-state verification voltage VvA (e.g., waveform or programming signal 1016) may be applied after each of the first programming voltage 1001, the second programming voltage 1002, and the third programming voltage 1003, respectively. The A-state verification voltage VvA and the B-state verification voltage VvB (e.g., programming signal 1017) may be applied after each of the fourth programming voltage 1004, the fifth programming voltage 1005, and the sixth programming voltage 1006, respectively. The A-state verification voltage VvA, the B-state verification voltage VvB, and the C-state verification voltage VvC (e.g., programming signal 1018) may be applied after each of the seventh programming voltage 1007 and the eighth programming voltage 1008, respectively. The B-state verification voltage VvB and the C-state verification voltage VvC (e.g., programming signal 1019) may be applied after each of the ninth programming voltage 1009, the tenth programming voltage 1010, and the eleventh programming voltage 1011, respectively. Finally, the C-state verification voltage VvC (eg, program signal 1020 ) may be applied after each of the twelfth, thirteenth, fourteenth, and fifteenth program voltages 1012 , 1013 , 1014 , and 1015 , respectively.

[0116] In some embodiments, the memory device 100 (e.g., using the state machine 112 of the control circuit 110, the controller 122, and / or the control circuit 150) can use different programming voltages and / or different programming voltage biases to perform programming operations. In some embodiments, the programming voltage and the programming voltage bias used to perform the programming operation can include a word line voltage and a word line voltage bias, respectively. In addition or alternatively, the programming voltage and the programming voltage bias used to perform the programming operation can include a bit line voltage and a bit line voltage bias, respectively.

[0117] In some embodiments, a programming voltage and / or programming voltage bias to be applied to a line (e.g., a bit line, a word line, etc.) connected to a memory cell can be identified based on the location of the memory cell within the memory architecture. The location of the memory cell can indicate that the memory cell is included in a particular NAND string group, indicate that the memory cell is included on a particular plane of the memory architecture, etc. Additionally or alternatively, a programming voltage bias can be identified based on the thickness of a contact wire connector that segments or separates a particular NAND string group (e.g., the particular NAND string group in which the memory cell is included) from other NAND string groups.

[0118] Fig.11 An exemplary application 1100 for improving programming operations for programming a memory cell is schematically shown. The memory cell may be supported by a memory device such as the memory device 100. The memory device may include a memory such as a NAND memory, a controller for communicating with a host device and the NAND memory, and a bus for sending communications to the host device and the NAND memory and / or receiving communications between the host device and the NAND memory. The controller may include a frequency modulator (FM), an encoder (e.g., a low-density parity check (LDPC) encoder), a decoder (e.g., an LDPC decoder), etc. The NAND memory may include a cache (e.g., an SLC cache), a control circuit, a read / write circuit (not shown), and a main memory structure supporting the memory cell. The memory cell may include QLC, TLC, SLC, etc. The control circuit of the NAND memory may communicate with the frequency modulator (FM) device via a bus or other communication interface.

[0119] Although one or more embodiments refer to NAND memory, it should be understood that this is provided by way of example. In practice, one or more embodiments may be implemented on any number of different types of non-volatile memories. In addition, although one or more embodiments are described as being implemented by a controller, it should be understood that this is provided by way of example, and in practice, one or more embodiments may be implemented by a control circuit. In addition, although one or more embodiments are described as being implemented by a control circuit, it should be understood that this is provided by way of example, and in practice, one or more embodiments may be implemented by a controller.

[0120] As shown at reference numeral 1102, the controller may receive host data from the host device. For example, the controller may receive host data from the host device (e.g., using an encoder, such as a low-density parity check (LDPC) encoder). For example, when running an application under a file system or operating system, the host device may provide the host data to the controller.

[0121] In some embodiments, the memory cells may be TLC and may be programmed using a complete sequence. In this case, one word line may be fully programmed before moving to programming another word line.

[0122] In some embodiments, the host data may include a page of block data to be used when programming the memory cells. A page may include block data associated with a group of memory cells (usually along word lines or bit lines) that will be programmed together as a whole. The block data of a page may include user data, header data associated with error correction codes (ECC) and / or flags, etc. For example, the block data may include a binary string of digits that address data in units of logical sectors, where, for example, each sector may contain 512 bytes of data. The block data may, for example, identify the storage location of a specific block where the memory cell is located. The addressing data may be referred to as a logical address. In some embodiments, the block data may include a binary number that addresses data in units of logical clusters, each logical cluster consisting of one or more logical sectors.

[0123] In some embodiments, four pages of block data may be used, such as an upper page, a middle page, a lower page, and a top page. The naming conventions of these four pages may vary, but ultimately refer to the same four logical pages. For example, in some cases, the top page may be referred to as the fourth page or the last page.

[0124] In some embodiments, the controller may use a data structure to store host data. For example, the controller may use a data structure supported by static random access memory (SRAM), dynamic RAM (DRAM), and / or another type of memory to store host data.

[0125] In some implementations, the controller may package the host data. For example, the controller (eg, using an encoder) may package the host data using error correction code (ECC) data.

[0126] In some embodiments, the controller may process the host data or host data (e.g., packaged host data) to identify a first subset of host data to be programmed into the memory cells. The first subset may include the top page of the block data to be programmed into the memory cells. In some embodiments, the controller may process the host data to identify a second subset of host data to be programmed into the memory cells. The second set of host data may include the first three pages of the block data to be programmed into the memory cells. As will be further described herein, the first three pages of the block data may be programmed during the first phase of the programming operation, and the top page of the block data may be programmed with the first three pages during the second phase of the programming operation.

[0127] The controller may provide the first subset of host data to the control circuitry, as indicated by reference numeral 1104. For example, the controller may provide the first subset of host data to a decoder of the control circuitry via a bus. This will allow the top page of the block data to be combined with the other three pages of the block data during the final stages of the programming operation, as will be further described herein.

[0128] The controller may provide a second subset of the host data to the main memory structure, as shown at reference numeral 1106. For example, the controller (e.g., using an encoder) may perform a TLC phase of a programming operation by providing the second set of host data to the NAND memory via the bus. As described, the second set of host data may include three pages of block data (e.g., an upper page, a middle page, and a lower page).

[0129] In some embodiments, when performing the first phase of a programming operation, a 3345 encoding scheme may be implemented. For example, a 3345 encoding scheme or a structurally similar encoding scheme may be implemented such that eight TLC data states are programmed using three pages. This allows for greater spacing between each Vth, thereby improving Vth margin and programming reliability.

[0130] In some embodiments, performing the TLC phase may include programming memory cells based on three pages of block data. For example, three pages of block data may be programmed so that three pages of block data are written as eight TLC data states.

[0131] As shown in reference numeral 1108, the programming data state can be read back to the control circuit. For example, the control circuit can perform a read operation to read the programming data state from the corresponding memory cell. In some embodiments, parity bits can be generated within the NAND memory and stored using a cache. This allows the parity bits to be provided to the control circuit and used to decode the second set of host data, as will be further described herein. As shown in reference numeral 1110, a cache (e.g., an SLC cache) can be used to store parity bits, and the parity bits can be provided to the control circuit of the NAND memory. In some embodiments, the control circuit can perform a read operation to read the parity bits from the cache.

[0132] The control circuitry may decode the second set of host data and may combine the decoded second set of host data with the first set of host data, as indicated by reference numeral 1112. For example, the control circuitry (e.g., using a decoder) may perform a fine phase of a programming operation by decoding three pages of block data (i.e., a second subset of host data) using parity bits such that the parity bits may be used to distinguish between odd and even data states.

[0133] In some embodiments, as part of the refinement phase, the control circuitry can use parity bits to program eight data states into sixteen data states with more compact Vth widths. For example, if the data states programmed during the TLC phase of the programming operation are state 0, state 1, state 4, state 5, state 6, state 10, state 12, and state 14 (e.g., eight of the sixteen QLC data states), then the parity bits can be used to distinguish between state 0 and state 1, state 1 and state 4, state 4 and state 5, state 5 and state 6, etc. In combination Fig.10 Provides additional information about the decoded block data.

[0134] By programming eight data states in the first phase, the memory device reduces NWI relative to the MLC-fine programming operation. This is because the Vth shift between the first phase and the second phase is smaller. In addition, by utilizing parity bits, only the parity bits must be stored in the cache memory, thereby saving resources (e.g., memory resources, computing resources, and / or network resources) relative to one or more conventional solutions that must store pages of block data in the cache. In addition, only four pages of block data must be provided to the NAND memory at one time, thereby reducing the data transfer load on one or more components of the memory device.

[0135] Fig.12 A set of threshold voltage distributions (Vth) for a 3-bit memory cell at various stages of a programming operation according to the principles of the present disclosure are graphically illustrated. As shown in the top line, the first stage of the programming operation may cause the memory cell to be programmed to eight data states (e.g., shown as data state s0, data state s1, data state s4, data state s5, data state s6, data state s10, data state s12, and data state s14). Parity bits may be generated and stored in the SLC cache of one or more memory cells in the memory cell. In the example shown, parity bit 0, parity bit 1, parity bit 0, parity bit 1, parity bit 0, parity bit 1, parity bit 0, parity bit 1 may correspond to data state s0, data state s1, data state s4, data state s5, data state s6, data state s10, data state s12, and data state s14. As will be described, the parity bits allow the control circuit to distinguish between odd data states and even data states. In some embodiments, eight memory cells may be programmed using a set of read levels (shown as read level 1, read level 2, ..., read level 6. For example, each read level may correspond to a parity bit value that may identify one of two possible data states to be selected.

[0136] In some embodiments, a second programming phase (shown as a fine phase) may be performed, as shown by the center and bottom lines. For example, to decode the data state, a recovery operation may be performed that identifies a parity bit between two read levels and determines the data state corresponding to the parity bit based on which read levels the parity bit is positioned between. This may continue until the programming operation is complete.

[0137] In this way, programming operations can be used to effectively and efficiently program memory cells.

[0138] Fig.13 1 is a flow chart illustrating an exemplary method for programming a group of memory cells. Step 1302 receives parity bits stored using a data structure. For example, control circuitry of a non-volatile memory (e.g., a NAND memory) may receive parity bits stored using a data structure (e.g., an SLC cache). Step 1304 receives a first subset of host data including block data associated with the group of memory cells. For example, control circuitry of a NAND memory may receive a first subset of host data including block data associated with the group of memory cells. In some embodiments, the host data may be for a top page of block data associated with the group of memory cells.

[0139] Step 1306 performs a read operation to identify a second subset of host data including the additional block data associated with the group of memory cells. For example, the control circuitry may perform a read operation (or may cause a read operation to be performed) to identify a second subset of host data including the additional block data associated with the group of memory cells. In some embodiments, the second subset of host data may be for three other pages of the additional block data, which may include an upper page, a middle page, and a lower page.

[0140] Step 1308 decodes the second subset of the host data using the parity bits. For example, the control circuitry may decode the second subset of the host data using the parity bits. This may allow the control circuitry to distinguish between odd data states and even data states, such that the control circuitry may reprogram the eight data states to sixteen data states, as described in conjunction with step 1310.

[0141] In some embodiments, the control circuitry may combine the first subset of host data with the second subset of host data. For example, because three other pages have been decoded, the control circuitry may combine the three other pages with the top page so that all four pages can be written to the NAND memory.

[0142] Step 1310 performs a write operation to write the block data and the additional block data to at least one or more memory cells that are part of the group of memory cells. In some embodiments, the control circuitry may perform a write operation to write the block data and the additional block data to at least one or more memory cells that are part of the group of memory cells. For example, the control circuitry may perform a write operation to write the combined four pages of block data to at least one or more memory cells in the group of memory cells.

[0143] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

[0144] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to implement functions such as programming and reading. The associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0145] Those skilled in the art will recognize that the present technology is not limited to the two-dimensional and three-dimensional exemplary structures described, but encompasses all related memory structures within the spirit and scope of the present technology as described herein and as understood by those skilled in the art.

[0146] The above specific embodiments of the present invention have been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments are selected to best explain the principles of the present invention and its practical application, so that other technical personnel in the field can best utilize the present invention in various embodiments and in various modifications suitable for the intended specific use. The scope of the present invention is intended to be limited by the appended claims.

[0147] Various terms are used to refer to specific system components. Different companies may refer to components by different names—this document does not intend to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended manner and, therefore, should be understood to mean "including, but not limited to..." In addition, the terms "couple" or "couples" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0148] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other substrate layer, or there can be intervening layers. Additionally, it should be understood that when a layer is referred to as being "below" another layer, it can be directly below the other layer, and there can also be one or more intervening layers. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0149] As described herein, the controller includes a single circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a processor with control software, a field programmable gate array (FPGA), or a combination thereof.

Claims

1. A non-volatile memory device, comprising: Memory; and a control circuit communicatively coupled to the memory, wherein the control circuit is used to program a group of memory cells and is configured to: receiving a parity bit stored using a data structure; receiving a first subset of host data including block data associated with the set of memory cells; performing a read operation to identify a second subset of the host data including additional block data associated with the group of memory cells; decoding a second subset of the host data using the parity bits; as well as A write operation is performed to write the block data and the additional block data to at least one or more memory cells that are part of the group of memory cells.

2. The non-volatile memory device of claim 1, wherein the parity bit allows the control circuit to distinguish between specific data states.

3. The non-volatile memory device of claim 1, wherein the parity bit allows the control circuit to distinguish between data state n and data state n+1. 4 . The nonvolatile memory device of claim 3 , wherein a first bit corresponding to data state n overlaps with a second bit corresponding to data state n+1.

5. The nonvolatile memory device according to claim 1 , wherein the control circuit is further configured to: A top page of block data and three other pages of decoded additional block data are combined, wherein the top page is combinable with the three other pages based on the parity bits used to decode the three other pages.

6. The non-volatile memory device of claim 1, wherein the group of memory cells are quad level cells (QLC).

7. The non-volatile memory device of claim 1, wherein the one or more memory cells are programmed to eight data states during the first stage of programming.

8. A method of performing a programming operation to program a group of memory cells, wherein performing the programming operation comprises: receiving a parity bit stored using a data structure; receiving a first subset of host data including block data associated with the set of memory cells; performing a read operation to identify a second subset of the host data including additional block data associated with the group of memory cells; decoding a second subset of the host data using the parity bits; as well as A write operation is performed to write the block data and the additional block data to at least one or more memory cells that are part of the group of memory cells.

9. The method of claim 8, wherein the first subset of host data comprises a top page of block data, and wherein the second subset of host data comprises three additional pages of additional block data.

10. The method according to claim 9, further comprising: A top page of the block data and three other pages of the additional block data that have been decoded are combined, wherein the top page can be combined with the three other pages based on the parity bits used to decode the three other pages.

11. The method of claim 8, wherein the parity bit allows differentiation between data state n and data state n+1.

12. The method of claim 11, wherein a first bit corresponding to data state n overlaps with a second bit corresponding to data state n+1.

13. The method according to claim 8, further comprising: A single level cell (SLC) cache is used to store the parity bits.

14. A device, comprising: A control circuit is communicatively coupled to the non-volatile memory, the control circuit being used to program a group of memory cells, wherein the control circuit is configured when programming the group of memory cells to: receiving a parity bit stored using a data structure; receiving a first subset of host data including block data for a top page, wherein the block data is associated with the set of memory cells; performing a read operation to identify a second subset of the host data, the second subset of the host data comprising three other pages of additional block data associated with the group of memory cells; decoding a second subset of the host data using the parity bits; as well as A write operation is performed to write the top page of the block data and the three other pages of the decoded additional block data to at least one or more memory cells that are part of the group of memory cells.

15. The apparatus of claim 14, wherein the parity bit allows the control circuit to distinguish between particular data states.

16. The apparatus of claim 15, wherein the parity bit allows the control circuit to distinguish between data state n and data state n+1.

17. The device of claim 15, wherein the control circuit is further configured to: A single level cell (SLC) cache is used to store the parity bits.

18. The apparatus of claim 15, wherein the one or more memory cells are programmed to eight data states during a first phase of a programming operation, and wherein the control circuitry, when performing the write operation, is configured to: The write operation is performed to program the one or more memory cells to sixteen data states, wherein the write operation is part of a second phase of the programming operation.

19. The device of claim 15, wherein the control circuit is further configured to: The top page of the block data and the three other pages of the additional block data that have been decoded are combined, wherein the top page can be combined with the three other pages based on the parity bits used to decode the three other pages.

20. The apparatus of claim 15, wherein the memory cell is a triple level cell (TLC).

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