Split-gate flash memory device and method for manufacturing the same

Abstract

The present invention provides a split-gate flash memory device and a preparation method thereof, comprising: a substrate, comprising a functional area, a first connection area and a second connection area, a plurality of word line gate lines arranged along a first direction, located on the substrate; a plurality of gate line groups arranged along the first direction, located on the substrate, and each of the gate line groups comprises two floating gate lines and two control gate lines; a plurality of erase gate lines arranged along the first direction, located on the substrate, each of the erase gate lines comprises a first part and a second part, the second part is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction; a plurality of source lines arranged along the first direction, located in the substrate below the erase gate lines; a plurality of first electrical connectors and second electrical connectors, the second electrical connectors being electrically connected to the second part of the erase gate lines; the present invention simplifies the interconnection process of the control gate lines.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate flash memory device and a preparation method thereof. Background Art

[0002] As a non-volatile memory, the working principle of flash memory is to control the switch of the gate channel by changing the critical voltage of the transistor or storage unit to achieve the purpose of storing data, so that the data stored in the memory will not disappear due to power interruption. Flash memory is a special structure of electrically erasable and programmable read-only memory. In the preparation method of flash memory, a floating gate and a control gate are formed on the substrate, and a side wall is formed on the control gate. Since the floating gate needs to be controlled by the control gate, the floating gate can be injected or released with charge to change the threshold voltage of the storage unit to achieve the purpose of storing or releasing data, so the control gate needs to be led out through a metal lead. As the size of the flash memory is reduced, the size of the floating gate, the control gate and the side wall will also be reduced. When the subsequent interconnection process is carried out, the reduction of the process window may make it difficult to lead out the control gate through the metal lead, which increases the difficulty of the interconnection process. Summary of the invention

[0003] The object of the present invention is to provide a split-gate flash memory device and a preparation method thereof, so as to simplify the interconnection process of control gate lines.

[0004] In order to achieve the above object, the present invention provides a split-gate flash memory device, comprising:

[0005] A substrate, comprising a functional area, a first connection area and a second connection area, wherein the first connection area is located between the functional area and the second connection area;

[0006] A plurality of word line gate lines arranged along a first direction, located on the substrate, and extending from the functional area along a second direction to the first connection area and the second connection area;

[0007] A plurality of gate line groups arranged along a first direction, located on the substrate, each of the gate line groups being located between two adjacent word line gate lines, and each of the gate line groups comprising two floating gate lines and two control gate lines, the control gate lines being located on corresponding floating gate lines, the floating gate lines extending from the functional area along the second direction to the first connection area, and the control gate lines extending from the functional area along the second direction to the first connection area and the second connection area;

[0008] A plurality of erase gate lines arranged along a first direction, located on the substrate, each of the erase gate lines being located between two of the floating gate lines and between two of the control gate lines of a corresponding gate line group, each of the erase gate lines comprising a first portion and a second portion, the first portion being located in the functional region, the second portion being located in the second connection region and being electrically connected to two adjacent control gate lines along the first direction;

[0009] A plurality of source lines arranged along the first direction, located in the substrate below the erase gate line, and extending from the functional area along the second direction to the first connection area and the second connection area;

[0010] A plurality of first electrical connectors and second electrical connectors are respectively located in the first connection area and the second connection area. The first electrical connector is electrically connected to the portion of the source line located in the first connection area, and the second electrical connector is electrically connected to the second portion of the erase gate line.

[0011] Optionally, it also includes a plurality of first side walls arranged along the first direction, the first side walls including a first sub-side wall, a second sub-side wall and a third sub-side wall; the first sub-side wall is located on the control gate line and extends from the functional area along the second direction to the first connection area and the second connection area; the second sub-side wall covers the side surfaces of the control gate line adjacent to the erase gate line and at least a portion of the surface of the first sub-side wall, the third sub-side wall covers the side surfaces of the floating gate line adjacent to the erase gate line and at least a portion of the surface of the second sub-side wall, and the second sub-side wall and the third sub-side wall both extend from the functional area along the second direction to the first connection area.

[0012] Optionally, it also includes a plurality of second side walls and a third side wall arranged along the first direction, the second side wall covers the first sub-side wall, the control gate line and the side of the floating gate line away from the erase gate line, the word line gate line covers at least a portion of the surface of the second side wall, the third side wall covers at least a portion of the surface of the word line gate line, and the second side wall and the third side wall both extend from the functional area along the second direction to the first connection area and the second connection area.

[0013] Optionally, it also includes a plurality of drain lines arranged along the second direction, the drain lines are located in the functional area within the substrate and extend along the first direction; and it also includes a plurality of third electrical connectors located in the functional area, the third electrical connectors are electrically connected to the drain lines.

[0014] Optionally, it also includes an interlayer dielectric layer, which covers the substrate, the word line gate line and the erase gate line, the first electrical connection passes through the interlayer dielectric layer and is electrically connected to the portion of the source line located in the first connection area, the second electrical connection passes through the interlayer dielectric layer and is electrically connected to the second portion of the erase gate line, and the third electrical connection passes through the interlayer dielectric layer and is electrically connected to the drain line.

[0015] A method for preparing a split-gate flash memory device, comprising:

[0016] Providing a substrate, the substrate comprising a functional area, a first connection area and a second connection area, wherein the first connection area is located between the functional area and the second connection area;

[0017] Forming a plurality of word lines, gate lines and erase gate lines arranged along a first direction on the substrate, forming a plurality of source lines arranged along the first direction in the substrate below the erase gate lines, and forming a plurality of first electrical connectors and second electrical connectors respectively located in the first connection area and the second connection area;

[0018] Wherein, the word line gate line extends from the functional area along the second direction to the first connection area and the second connection area;

[0019] Each of the gate line groups is located between two adjacent word line gate lines, and each of the gate line groups includes two floating gate lines and two control gate lines, the control gate lines are located on the corresponding floating gate lines, the floating gate lines extend from the functional area along the second direction to the first connection area, and the control gate lines extend from the functional area along the second direction to the first connection area and the second connection area;

[0020] Each of the erase gate lines is located between the two floating gate lines and the two control gate lines of the corresponding gate line group, and each of the erase gate lines includes a first portion and a second portion, the first portion is located in the functional area, and the second portion is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction;

[0021] The source line extends from the functional area along the second direction to the first connection area and the second connection area;

[0022] The first electrical connection member is electrically connected to a portion of the source line located in the first connection area, and the second electrical connection member is electrically connected to a second portion of the erase gate line.

[0023] Optionally, the step of forming the word line gate line, the gate line group and the erase gate line comprises:

[0024] forming a floating gate material layer, a control gate material layer and a first dielectric layer in sequence on the substrate;

[0025] Etching the floating gate material layer, the control gate material layer and the first dielectric layer to form a plurality of openings exposing the surface of the substrate;

[0026] Performing ion implantation on the substrate at the bottom of the plurality of openings to form a plurality of source lines in the substrate;

[0027] filling an erase gate material layer in the opening;

[0028] Etching and removing the first dielectric layer and the floating gate material layer and the control gate material layer directly below the first dielectric layer to form a plurality of floating gate lines and control gate lines, wherein two adjacent floating gate lines and two control gate lines of the erase gate material layer constitute a gate line group;

[0029] forming a plurality of word line gate lines on the side of the floating gate line and the control gate line away from the erase gate material layer; and,

[0030] The erase gate material layer in the first connection area is removed by etching, and the remaining erase gate material layer is used as the erase gate line. The erase gate line in the functional area is used as the first part, and the erase gate line in the second connection area is used as the second part.

[0031] Optionally, before the erase gate material layer is filled in the opening, a first sidewall spacer is formed on an inner wall of the opening.

[0032] Optionally, the step of forming a plurality of openings exposing the surface of the substrate and forming the first sidewalls on inner walls of the openings includes:

[0033] Etching the first dielectric layer to form a first sub-opening, wherein the first sub-opening exposes the surface of the control gate material layer;

[0034] forming a first sub-spacer on a sidewall of the first sub-opening;

[0035] Using the first sub-spacer as a mask, etching the control gate material layer to form a second sub-opening, wherein the second sub-opening exposes the surface of the floating gate material layer;

[0036] forming a second sub-spacer on the sidewall of the second sub-opening, wherein the second sub-spacer covers at least a portion of the surface of the first sub-spacer;

[0037] Using the second sub-spacer as a mask, the floating gate material layer is etched to form a third sub-opening, wherein the third sub-opening exposes the surface of the substrate, and the first sub-opening, the second sub-opening and the third sub-opening are connected to form the opening; and

[0038] A third sub-sidewall is formed on the inner wall of the third sub-opening, and the third sub-sidewall covers at least a portion of the surface of the second sub-sidewall and the first sub-sidewall. The first sub-sidewall, the second sub-sidewall and the third sub-sidewall constitute the first sidewall.

[0039] Optionally, after forming the first sidewall spacer on the inner wall of the opening and before filling the erase gate material layer in the opening, the method further includes:

[0040] A portion of the first sidewall spacer in the second connection region is removed by etching to expose a portion of the surface of the control gate line.

[0041] Optionally, the step of etching and removing a portion of the first sidewall spacer located in the second connection region includes:

[0042] forming a patterned photoresist layer on the functional area and the first connection area; and,

[0043] Using the patterned photoresist layer as a mask, etching away a portion of the thickness of the first sub-spacer, the second sub-spacer and the third sub-spacer; and,

[0044] The patterned photoresist layer is removed.

[0045] Optionally, before forming a plurality of word line lines on the side of the floating gate line and the control gate line away from the erase gate material layer, the method further includes:

[0046] forming a second spacer on the side of the floating gate line and the control gate line away from the erase gate material layer; and,

[0047] After forming a plurality of word line gate lines on the side surfaces of the floating gate line and the control gate line away from the erase gate material layer, a third spacer is further formed on at least a portion of the surface of the word line gate line.

[0048] Optionally, after etching away the erase gate material layer located in the first connection region, the method further includes:

[0049] Ion implantation is performed on the substrate at both sides of the word line gate line in the functional area away from the erase gate line to form a plurality of drain lines arranged along the second direction in the functional area of ​​the substrate, and the drain lines extend along the first direction.

[0050] Optionally, after forming a plurality of drain lines in the substrate, forming a plurality of first electrical connectors and a plurality of second electrical connectors, further comprising forming a plurality of third electrical connectors; the steps of forming a plurality of first electrical connectors, a plurality of second electrical connectors and a plurality of third electrical connectors include:

[0051] forming an interlayer dielectric layer on the substrate, the word line gate line and the erase gate line; and,

[0052] A plurality of the first electrical connectors, the second electrical connectors and the third electrical connectors are formed to penetrate the interlayer dielectric layer, the first electrical connectors are electrically connected to the portion of the source line located in the first connection area, the second electrical connectors are electrically connected to the second portion of the erase gate line, and the third electrical connectors are electrically connected to the drain line.

[0053] In the split-gate flash memory device and the preparation method thereof provided by the present invention, the substrate includes a functional area, a first connection area and a second connection area, the first connection area is located between the functional area and the second connection area; a plurality of erase gate lines arranged along a first direction are located on the substrate, each of the erase gate lines is located between two floating gate lines and two control gate lines of a corresponding gate line group, each of the erase gate lines includes a first part and a second part, the first part is located in the functional area, the second part is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction; a plurality of source lines arranged along the first direction are located in the substrate below the erase gate lines, and extend from the functional area to the first connection area and the second connection area along the second direction; a plurality of first electrical connectors and second electrical connectors are located in the first connection area and the second connection area, respectively, the first electrical connector is electrically connected to the portion of the source line located in the first connection area, and the second electrical connector is electrically connected to the second portion of the erase gate line. In the present invention, the second portion of the erase gate line is electrically connected to the two adjacent control gate lines along the first direction, and the source line is located in the substrate below the erase gate line, that is, the control gate line and the source line located in the second connection area are directly connected through the second portion of the erase gate line, and then the second portion of the erase gate line is connected through the second electrical connection member to facilitate the lead-out of the control gate line. Even if the size of the control gate line is reduced after the process window is reduced, it is still convenient to lead out the control gate line, thereby reducing the difficulty of the interconnection process and simplifying the interconnection process of the control gate line. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A top view of a split-gate flash memory device provided by an embodiment of the present invention;

[0055] Figure 2A flow chart of a method for preparing a split-gate flash memory device provided by an embodiment of the present invention;

[0056] Figure 3 A top view of a substrate provided in a method for preparing a split-gate flash memory device provided in an embodiment of the present invention;

[0057] Figure 4 to Figure 27 A cross-sectional schematic diagram of corresponding steps in a method for preparing a split-gate flash memory device provided in an embodiment of the present invention, wherein: Fig.25 A cross-sectional schematic diagram of a functional area in a split-gate flash memory device provided by an embodiment of the present invention, Fig.26 A cross-sectional schematic diagram of a first connection region in a split-gate flash memory device provided by an embodiment of the present invention, Fig. 27 A schematic cross-sectional view of a second connection region in a split-gate flash memory device provided by an embodiment of the present invention;

[0058] Wherein, the accompanying drawings are marked as follows:

[0059] X1-functional area; X2-first connection area; X3-second connection area;

[0060] 100-substrate; 110-groove structure; 210-first oxide layer; 211-gate oxide line; 220-floating gate material layer; 221-floating gate line; 230-second dielectric layer; 231-inter-gate dielectric line; 240-control gate material layer; 241-control gate line; 300-first dielectric layer; 410-first sub-opening; 420-second sub-opening; 430-third sub-opening; 510-first sub-sidewall; 520 -second sub-spacer; 530-third sub-spacer; 610-source line; 620-drain line; 700-patterned photoresist layer; 800-erase gate material layer; 801-erase gate line; 810-erase gate protection line; 820-second spacer; 830-word line gate line; 840-third spacer; 900-interlayer dielectric layer; 901-first electrical connector; 902-second electrical connector; 903-third electrical connector. DETAILED DESCRIPTION

[0061] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0062] Figure 1 A top view of the split-gate flash memory device provided in this embodiment; Fig.25 A cross-sectional schematic diagram of a functional area in a split-gate flash memory device provided in this embodiment (X1 is Figure 1 Schematic diagram of the cross section along the A1-A2 direction); Fig.26 A cross-sectional schematic diagram of the first connection region in the split-gate flash memory device provided in this embodiment (X2 is Figure 1 Schematic diagram of the cross section along the B1-B2 direction); Fig. 27 A cross-sectional schematic diagram of the second connection region in the split-gate flash memory device provided in this embodiment (X3 is Figure 1 (a cross-sectional view along the C1-C2 direction in Fig. Figure 1 and Figure 25 to Figure 27 The present embodiment provides a split-gate flash memory device, comprising: a substrate 100, a plurality of word line gate lines 830 arranged along a first direction, a plurality of gate line groups arranged along the first direction, a plurality of erase gate lines 801 arranged along the first direction, a plurality of source lines 610 arranged along the first direction, a plurality of first electrical connectors 901 and a plurality of second electrical connectors 902. The substrate 100 comprises a functional region X1, a first connection region X2 and a second connection region X3, wherein the first connection region X2 is located between the functional region X1 and the second connection region X3.

[0063] The word line gate lines 830 arranged along the first direction are all located on the substrate 100 and extend from the functional area X1 to the first connection area X2 and the second connection area X3 along the second direction. In this embodiment, the first direction and the second direction are perpendicular to each other, but not limited thereto.

[0064] Several gate line groups arranged along the first direction are all located on the substrate 100, each of the gate line groups is located between two adjacent word line gate lines 830, and each of the gate line groups includes two floating gate lines 221 and two control gate lines 241, the control gate lines 241 are located on the corresponding floating gate lines 221, the floating gate lines 221 extend from the functional area X1 along the second direction to the first connection area X2, and the control gate lines 241 extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3. In this embodiment, a plurality of inter-gate dielectric lines 231 arranged along the first direction are formed between the control gate line 241 and the floating gate line 221, and the inter-gate dielectric lines 231 extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3, and the material of the inter-gate dielectric lines 231 includes oxide and / or nitride; and a plurality of gate oxide lines 211 arranged along the first direction are formed between the substrate 100 and the floating gate line 221, and the gate oxide lines 211 extend from the functional area X1 along the second direction to the first connection area X2.

[0065] A plurality of erase gate lines 801 arranged along the first direction are all located on the substrate 100, each of the erase gate lines 801 is located between two of the floating gate lines 221 and between two of the control gate lines 241, and each of the erase gate lines 801 includes a first portion and a second portion, the first portion is located in the functional area X1, and the second portion is located in the second connection area X3 and is electrically connected to two adjacent control gate lines 241 along the first direction. In the present embodiment, an erase gate protection line 810 is formed on the erase gate line 801, and the material of the erase gate protection line 810 can be oxide or nitride.

[0066] A plurality of source lines 610 arranged along the first direction are located in the substrate 100 below the corresponding erase gate lines 801 , and extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3 .

[0067] Several first electrical connectors 901 and second electrical connectors 902 are respectively located in the first connection area X2 and the second connection area X3. The first electrical connector 901 is electrically connected to the portion of the source line 610 located in the first connection area X2, and the second electrical connector 902 is electrically connected to the second portion of the erase gate line 801.

[0068] Furthermore, it also includes a plurality of first side walls arranged along the first direction, the first side walls including a first sub-side wall 510, a second sub-side wall 520 and a third sub-side wall 530, the first sub-side wall 510 is located on the control gate line 241, and extends from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3; the second sub-side wall 520 covers the side of the control gate line 241 adjacent to the erase gate line 801 and at least a portion of the surface of the first sub-side wall 510, the third sub-side wall 530 covers the side of the floating gate line 221 adjacent to the erase gate line 801 and at least a portion of the surface of the second sub-side wall 520, and the second sub-side wall 520 and the third sub-side wall 530 both extend from the functional area X1 along the second direction to the first connection area X2.

[0069] Furthermore, it also includes a plurality of second side walls 820 and third side walls 840 arranged along the first direction, and the second side walls 820 cover the sides of the first sub-side walls 510, the control gate line 241 and the floating gate line 221 away from the erase gate line 801; in the present embodiment, since the floating gate line 221 is not provided in the second connection area X3, the second side walls 820 cover the sides of the first sub-side walls 510, the control gate line 241 and the floating gate line 221 away from the erase gate line 801 in the functional area X1 and the first connection area X2; in the second connection area X3, the second side walls 820 cover the sides of the first sub-side walls 510 and the control gate line 241 away from the erase gate line 801. The word line gate line 830 covers at least a portion of the surface of the second side wall 820, the third side wall 840 covers at least a portion of the surface of the word line gate line 830, and the second side wall 820 and the third side wall 840 both extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3.

[0070] Furthermore, it also includes a plurality of drain lines 620 arranged along the second direction, located in the substrate 100, and the drain lines 620 are located in the functional area X1 in the substrate 100 and extend along the first direction; and, it also includes a plurality of third electrical connectors 903, located in the functional area X1, and the third electrical connectors 903 are electrically connected to the drain lines 620.

[0071] Furthermore, it also includes an interlayer dielectric layer 900, the interlayer dielectric layer 900 covers the substrate 100, the word line gate line 830 and the erase gate line 801, the first electrical connection member 901 passes through the interlayer dielectric layer 900 and is electrically connected to the portion of the source line 610 located in the first connection area X2, the second electrical connection member 902 passes through the interlayer dielectric layer 900 and is electrically connected to the second portion of the erase gate line 801, and the third electrical connection member 903 passes through the interlayer dielectric layer 900 and is electrically connected to the drain line 620.

[0072] In this embodiment, the second connection area X3 also includes a plurality of groove structures 110 located in the substrate 100. The control gate line 241, the word line gate line 830, the second side wall 820 and the third side wall 840 are all located on the groove structure 110. The source line 610 and the second portion of the erase gate line 801 located in the second connection area X3 are located between two adjacent groove structures 110.

[0073] Figure 2 Flow chart of the method for preparing the split-gate flash memory device provided in this embodiment. Figure 2This embodiment provides a method for preparing a split-gate flash memory device, comprising:

[0074] Step S1: providing a substrate, wherein the substrate comprises a functional area, a first connection area and a second connection area, wherein the first connection area is located between the functional area and the second connection area;

[0075] Step S2: forming a plurality of word lines, gate lines and erase gate lines arranged along a first direction on the substrate, forming a plurality of source lines arranged along the first direction in the substrate below the erase gate lines, and forming a plurality of first electrical connectors and second electrical connectors respectively located in the first connection area and the second connection area;

[0076] Wherein, the word line gate line extends from the functional area along the second direction to the first connection area and the second connection area;

[0077] Each of the gate line groups is located between two adjacent word line gate lines, and each of the gate line groups includes two floating gate lines and two control gate lines, the control gate lines are located on the corresponding floating gate lines, the floating gate lines extend from the functional area along the second direction to the first connection area, and the control gate lines extend from the functional area along the second direction to the first connection area and the second connection area;

[0078] Each of the erase gate lines is located between the two floating gate lines and the two control gate lines of the corresponding gate line group, and each of the erase gate lines includes a first portion and a second portion, the first portion is located in the functional area, and the second portion is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction;

[0079] The source line extends from the functional area along the second direction to the first connection area and the second connection area;

[0080] The first electrical connection member is electrically connected to a portion of the source line located in the first connection area, and the second electrical connection member is electrically connected to a second portion of the erase gate line.

[0081] Figure 3 A top view of a substrate provided in the method for preparing a split-gate flash memory device provided in this embodiment; Figure 4 to Figure 27 The cross-sectional schematic diagram of the corresponding steps in the method for preparing the split-gate flash memory device provided in this embodiment is shown in FIG. Figure 4 to Figure 27 X1 is Figure 1 The cross-sectional diagram of the corresponding steps along the A1-A2 direction, X2 is Figure 1 The cross-sectional schematic diagram of the corresponding steps along the B1-B2 direction and X3 are Figure 1 The cross-sectional diagram of the corresponding steps along the C1-C2 direction is shown below. Figure 3 to Figure 27 The method for preparing the split-gate flash memory device provided in this embodiment is described in detail.

[0082] Please refer to Figure 3 , perform step S1: provide the substrate 100, the material of the substrate 100 includes one or more of silicon, germanium, gallium, nitrogen or carbon, the substrate 100 includes the functional area X1, the first connection area X2 and the second connection area X3, the first connection area X2 is located between the functional area X1 and the second connection area X3.

[0083] Execute step S2: form a plurality of the word line gate lines 830, the gate line group and the erase gate line 801 arranged along the first direction on the substrate 100, form a plurality of the source lines 610 arranged along the first direction in the substrate 100 below the erase gate line 801, and form a plurality of first electrical connectors 901 and second electrical connectors 902 respectively located in the first connection area X2 and the second connection area X3.

[0084] For details, please refer to Figure 4 , a first oxide layer 210 and a floating gate material layer 220 are formed on the functional area X1, the first connection area X2 and the second connection area X3.

[0085] Please refer to Figure 5 , a plurality of groove structures 110 are formed in the second connection area X3, specifically, the floating gate material layer 220, the first oxide layer 210 and the substrate 100 are sequentially etched to form grooves, and then the material is filled in the grooves to form the groove structures 110, and the groove structures 110 are flush with the surface of the floating gate material layer 220.

[0086] Please refer to Figure 6 and Figure 7 , a second dielectric layer 230, a control gate material layer 240 and a first dielectric layer 300 are sequentially formed on the floating gate material layer 220 in the functional area X1 and the first connection area X2, and the second dielectric layer 230, the control gate material layer 240 and the first dielectric layer 300 are simultaneously sequentially formed on the floating gate material layer 220 and the trench structure 110 in the second connection area X3, and the material of the second dielectric layer 230 can be oxide and / or nitride.

[0087] Please refer to Figure 8 and Fig. 9, in the functional area X1, the first connection area X2 and the second connection area X3, the first dielectric layer 300 is etched to form a plurality of first sub-openings 410, and the first sub-openings 410 expose the surface of the control gate material layer 240; and first sub-spacers 510 are formed on the sidewalls of the first sub-openings 410. In this embodiment, in the second connection area X3, the spacing between two adjacent first sub-spacers 510 in the first sub-openings 410 may be equal to the spacing between two adjacent trench structures 110, but is not limited thereto.

[0088] Please refer to Fig.10 and Fig.11 , in the functional area X1, the first connection area X2 and the second connection area X3, the control gate material layer 240 and the second dielectric layer 230 are etched using the first sub-spacer 510 as a mask to form a second sub-opening 420, and the second sub-opening 420 exposes the surface of the floating gate material layer 220; a second sub-spacer 520 is formed on the sidewall of the second sub-opening 420, and the second sub-spacer 520 covers at least a portion of the surface of the first sub-spacer 510.

[0089] Please refer to Fig.12 and Fig.13 , in the functional area X1, the first connection area X2 and the second connection area X3, the floating gate material layer 220 and the first oxide layer 210 are etched using the second sub-spacer 520 as a mask to form a third sub-opening 430, and the third sub-opening 430 exposes the surface of the substrate 100, and the first sub-opening 410, the second sub-opening 420 and the third sub-opening 430 are connected to form the opening (not shown in the figure), that is, a plurality of the openings are formed and the openings expose the surface of the substrate 100; in the A third sub-side wall 530 is formed on the inner wall of the third sub-opening 430, and the third sub-side wall 530 covers at least part of the surface of the second sub-side wall 520 and the first sub-side wall 510. The third sub-side wall 530 also covers the surface of the substrate 100 in the third sub-opening 430. The first sub-side wall 510, the second sub-side wall 520 and the third sub-side wall 530 constitute the first side wall (not shown in the figure), that is, the first side wall is formed on the inner wall of the opening, and the first side wall is arranged along the first direction.

[0090] Please continue to refer to Fig.12 and Fig.13In the functional area X1, the first connection area X2 and the second connection area X3, ion implantation is performed on the substrate 100 at the bottom of the opening to form a plurality of source lines 610 arranged along the first direction in the substrate 100, and the source lines 610 extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3, wherein the implanted ion type of the ion implantation includes N-type doped ions or P-type doped ions.

[0091] Please refer to Fig.14 and Fig.15 , etching and removing part of the first sidewall spacer in the second connection area X3 to expose part of the surface of the control gate material layer 240 and the source line 610. Specifically, a patterned photoresist layer 700 is formed on the functional area X1 and the first connection area X2, and the patterned photoresist layer 700 covers the functional area X1 and the first connection area X2; then, using the patterned photoresist layer 700 as a mask, etching and removing part of the thickness of the first sub-sidewall spacer 510, the second sub-sidewall spacer 520 and the third sub-sidewall spacer 530 located in the second connection area X3 to expose part of the surface of the control gate material layer 240 and the source line 610, and then removing the patterned photoresist layer 700. After etching away part of the first side wall in the second connection area X3, the first sub-side wall 510 extends from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3, and the second sub-side wall 520 and the third sub-side wall 530 both extend from the functional area X1 along the second direction to the first connection area X2.

[0092] Please refer to Fig.16 and Fig.17 , in the functional area X1, the first connection area X2 and the second connection area X3, the erase gate material layer 800 is filled in the opening; and, an erase gate protection line 810 is formed on the erase gate material layer 800, and the material of the erase gate protection line 810 can be oxide or nitride.

[0093] Please refer to Fig.18 and Fig.19, in the functional area X1 and the first connection area X2, the first dielectric layer 300 and the control gate material layer 240, the second dielectric layer 230, the floating gate material layer 220 and the first oxide layer 210 below the first dielectric layer 300 are etched away, and in the second connection area X3, the first dielectric layer 300 and the control gate material layer 240 and the second dielectric layer 230 below the first dielectric layer 300 are etched away to form a plurality of control gate lines 241, inter-gate dielectric lines 231, floating gate lines 221 and gate oxide lines 211, wherein the floating gate line 221 extends from the functional area X1 to the first connection area X2 along the second direction, the control gate line 241 extends from the functional area X1 to the first connection area X2 and the second connection area X3 along the second direction, two adjacent floating gate lines 221 and two control gate lines 241 of the erase gate material layer 800 constitute a gate line group, and the plurality of gate line groups are arranged along the first direction.

[0094] Please refer to Fig. 20 and Fig.21 , further comprising forming a second sidewall spacer 820 and a word line gate line 830, wherein in the functional area X1 and the first connection area X2, the second sidewall spacer 820 covers the side of the first sub-sidewall spacer 510, the control gate line 241 and the floating gate line 221 away from the erase gate material layer 800; in the second connection area X3, the second sidewall spacer 820 covers the side of the first sub-sidewall spacer 510 and the control gate line 241 away from the erase gate material layer 800. The word line gate line 830 covers at least a portion of the surface of the second sidewall spacer 820, and a plurality of the word line gate lines 830 and the second sidewall spacer 820 are arranged along the first direction, and extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3.

[0095] Please refer to Figure 22 to Figure 24 , the erase gate material layer 800 located in the first connection area X2 is etched and removed, and the remaining erase gate material layer 800 serves as the erase gate line 801. Several erase gate lines 801 are arranged along the first direction, and each erase gate line 801 includes a first part and a second part. The erase gate line 801 located in the functional area X1 serves as the first part, and the erase gate line 801 located in the second connection area X3 serves as the second part, and the second part is electrically connected to the two adjacent control gate lines 241 along the first direction.

[0096] Please refer to Fig.25, in the functional area X1, ion implantation is performed on the substrate 100 on both sides of the word line gate line 830 away from the erase gate line 801 to form a plurality of drain lines 620 arranged along the second direction in the functional area X1 of the substrate 100, and the drain lines 620 extend along the first direction, wherein the ion type of the ion implantation includes N-type doped ions or P-type doped ions; and a third sidewall 840 is formed to cover at least a portion of the surface of the word line gate line 830, and a plurality of the third sidewalls 840 are arranged along the first direction and extend from the functional area X1 along the second direction to the first connection area X2 and the second connection area X3.

[0097] Please continue to refer to Fig.25 ,refer to Fig.26 and Fig. 27 In the functional area X1, the first connection area X2 and the second connection area X3, an interlayer dielectric layer 900 is formed on the substrate 100, the word line gate line 830 and the erase gate line 801. Further, a plurality of first electrical connections 901, second electrical connections 902 and third electrical connections 903 penetrating the interlayer dielectric layer 900 are formed, wherein the first electrical connection 901 is electrically connected to a portion of the source line 610 located in the first connection area X2, the second electrical connection 902 is electrically connected to a second portion of the erase gate line 801, and the third electrical connection 903 is electrically connected to the drain line 620.

[0098] In summary, in the split-gate flash memory device and the preparation method thereof provided by the present invention, the substrate includes a functional area, a first connection area and a second connection area, the first connection area is located between the functional area and the second connection area; a plurality of erase gate lines arranged along a first direction are located on the substrate, each of the erase gate lines is located between two floating gate lines and two control gate lines of a corresponding gate line group, each of the erase gate lines includes a first part and a second part, the first part is located in the functional area, the second part is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction; a plurality of source lines arranged along the first direction are located in the substrate below the erase gate lines, and extend from the functional area to the first connection area and the second connection area along the second direction; a plurality of first electrical connectors and second electrical connectors are located in the first connection area and the second connection area, respectively, the first electrical connector is electrically connected to the part of the source line located in the first connection area, and the second electrical connector is electrically connected to the second part of the erase gate line. In the present invention, the second portion of the erase gate line is electrically connected to the two adjacent control gate lines along the first direction, and the source line is located in the substrate below the erase gate line, that is, the control gate line and the source line located in the second connection area are directly connected through the second portion of the erase gate line, and then the second portion of the erase gate line is connected through the second electrical connection member to facilitate the lead-out of the control gate line. Even if the size of the control gate line is reduced after the process window is reduced, it is still convenient to lead out the control gate line, thereby reducing the difficulty of the interconnection process and simplifying the interconnection process of the control gate line.

[0099] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A split-gate flash memory device, characterized in that: include: A substrate, comprising a functional area, a first connection area and a second connection area, wherein the first connection area is located between the functional area and the second connection area; A plurality of word line gate lines arranged along a first direction, located on the substrate, and extending from the functional area along a second direction to the first connection area and the second connection area; A plurality of gate line groups arranged along a first direction, located on the substrate, each of the gate line groups being located between two adjacent word line gate lines, and each of the gate line groups comprising two floating gate lines and two control gate lines, the control gate lines being located on corresponding floating gate lines, the floating gate lines extending from the functional area along the second direction to the first connection area, and the control gate lines extending from the functional area along the second direction to the first connection area and the second connection area; A plurality of erase gate lines arranged along a first direction, located on the substrate, each of the erase gate lines being located between two of the floating gate lines and between two of the control gate lines of a corresponding gate line group, each of the erase gate lines comprising a first portion and a second portion, the first portion being located in the functional region, the second portion being located in the second connection region and being electrically connected to two adjacent control gate lines along the first direction; A plurality of source lines arranged along the first direction, located in the substrate below the erase gate line, and extending from the functional area along the second direction to the first connection area and the second connection area; A plurality of first electrical connectors and second electrical connectors are respectively located in the first connection area and the second connection area. The first electrical connector is electrically connected to the portion of the source line located in the first connection area, and the second electrical connector is electrically connected to the second portion of the erase gate line.

2. The split-gate flash memory device according to claim 1, wherein: It also includes a plurality of first side walls arranged along the first direction, the first side walls including a first sub-side wall, a second sub-side wall and a third sub-side wall; the first sub-side wall is located on the control gate line and extends from the functional area along the second direction to the first connection area and the second connection area; the second sub-side wall covers the side of the control gate line adjacent to the erase gate line and at least a portion of the surface of the first sub-side wall, the third sub-side wall covers the side of the floating gate line adjacent to the erase gate line and at least a portion of the surface of the second sub-side wall, and the second sub-side wall and the third sub-side wall both extend from the functional area along the second direction to the first connection area.

3. The split-gate flash memory device according to claim 2, wherein: It also includes a plurality of second side walls and a third side wall arranged along the first direction, the second side wall covers the first sub-side wall, the control gate line and the side of the floating gate line away from the erase gate line, the word line gate line covers at least a portion of the surface of the second side wall, the third side wall covers at least a portion of the surface of the word line gate line, and the second side wall and the third side wall both extend from the functional area along the second direction to the first connection area and the second connection area.

4. The split-gate flash memory device according to claim 1, wherein: It also includes a plurality of drain lines arranged along the second direction, the drain lines are located in the functional area within the substrate and extend along the first direction; and it also includes a plurality of third electrical connectors located in the functional area, the third electrical connectors are electrically connected to the drain lines.

5. The split-gate flash memory device according to claim 4, wherein: It also includes an interlayer dielectric layer, which covers the substrate, the word line gate line and the erase gate line. The first electrical connection penetrates the interlayer dielectric layer and is electrically connected to the portion of the source line located in the first connection area. The second electrical connection penetrates the interlayer dielectric layer and is electrically connected to the second portion of the erase gate line. The third electrical connection penetrates the interlayer dielectric layer and is electrically connected to the drain line.

6. A method for preparing a split-gate flash memory device, characterized in that: include: Providing a substrate, the substrate comprising a functional area, a first connection area and a second connection area, wherein the first connection area is located between the functional area and the second connection area; Forming a plurality of word lines, gate lines and erase gate lines arranged along a first direction on the substrate, forming a plurality of source lines arranged along the first direction in the substrate below the erase gate lines, and forming a plurality of first electrical connectors and second electrical connectors respectively located in the first connection area and the second connection area; Wherein, the word line gate line extends from the functional area along the second direction to the first connection area and the second connection area; Each of the gate line groups is located between two adjacent word line gate lines, and each of the gate line groups includes two floating gate lines and two control gate lines, the control gate lines are located on the corresponding floating gate lines, the floating gate lines extend from the functional area along the second direction to the first connection area, and the control gate lines extend from the functional area along the second direction to the first connection area and the second connection area; Each of the erase gate lines is located between the two floating gate lines and the two control gate lines of the corresponding gate line group, and each of the erase gate lines includes a first portion and a second portion, the first portion is located in the functional area, and the second portion is located in the second connection area and is electrically connected to two adjacent control gate lines along the first direction; The source line extends from the functional area along the second direction to the first connection area and the second connection area; The first electrical connection member is electrically connected to a portion of the source line located in the first connection area, and the second electrical connection member is electrically connected to a second portion of the erase gate line.

7. The method for preparing a split-gate flash memory device according to claim 6, wherein: The steps of forming the word line gate line, the gate line group and the erase gate line include: forming a floating gate material layer, a control gate material layer and a first dielectric layer in sequence on the substrate; Etching the floating gate material layer, the control gate material layer and the first dielectric layer to form a plurality of openings exposing the surface of the substrate; Performing ion implantation on the substrate at the bottom of the plurality of openings to form a plurality of source lines in the substrate; filling an erase gate material layer in the opening; Etching and removing the first dielectric layer and the floating gate material layer and the control gate material layer directly below the first dielectric layer to form a plurality of floating gate lines and control gate lines, wherein two adjacent floating gate lines and two control gate lines of the erase gate material layer constitute a gate line group; forming a plurality of word line gate lines on the side of the floating gate line and the control gate line away from the erase gate material layer; and, The erase gate material layer in the first connection area is removed by etching, and the remaining erase gate material layer is used as the erase gate line. The erase gate line in the functional area is used as the first part, and the erase gate line in the second connection area is used as the second part.

8. The method for preparing a split-gate flash memory device according to claim 7, wherein: Before the erase gate material layer is filled in the opening, a first sidewall spacer is formed on the inner wall of the opening.

9. The method for preparing a split-gate flash memory device according to claim 8, wherein: The steps of forming a plurality of openings to expose the surface of the substrate and forming the first sidewalls on the inner walls of the openings include: Etching the first dielectric layer to form a first sub-opening, wherein the first sub-opening exposes the surface of the control gate material layer; forming a first sub-spacer on a sidewall of the first sub-opening; Using the first sub-spacer as a mask, etching the control gate material layer to form a second sub-opening, wherein the second sub-opening exposes the surface of the floating gate material layer; forming a second sub-spacer on the sidewall of the second sub-opening, wherein the second sub-spacer covers at least a portion of the surface of the first sub-spacer; Using the second sub-spacer as a mask, the floating gate material layer is etched to form a third sub-opening, wherein the third sub-opening exposes the surface of the substrate, and the first sub-opening, the second sub-opening and the third sub-opening are connected to form the opening; and A third sub-sidewall is formed on the inner wall of the third sub-opening, and the third sub-sidewall covers at least a portion of the surface of the second sub-sidewall and the first sub-sidewall. The first sub-sidewall, the second sub-sidewall and the third sub-sidewall constitute the first sidewall.

10. The method for preparing a split-gate flash memory device according to claim 9, wherein: After forming the first sidewall spacer on the inner wall of the opening and before filling the erase gate material layer in the opening, the method further includes: A portion of the first sidewall spacer in the second connection region is removed by etching to expose a portion of the surface of the control gate line.

11. The method for preparing a split-gate flash memory device according to claim 10, wherein: The step of etching and removing a portion of the first sidewall spacer located in the second connection region comprises: forming a patterned photoresist layer on the functional area and the first connection area; and, Using the patterned photoresist layer as a mask, etching away a portion of the thickness of the first sub-spacer, the second sub-spacer and the third sub-spacer; and, The patterned photoresist layer is removed.

12. The method for preparing a split-gate flash memory device according to claim 7, wherein: Before forming a plurality of word line gate lines on the side of the floating gate line and the control gate line away from the erase gate material layer, the method further comprises: forming a second spacer on the side of the floating gate line and the control gate line away from the erase gate material layer; and, After forming a plurality of word line gate lines on the side surfaces of the floating gate line and the control gate line away from the erase gate material layer, a third spacer is further formed on at least a portion of the surface of the word line gate line.

13. The method for preparing a split-gate flash memory device according to claim 7, wherein: After etching away the erase gate material layer located in the first connection area, the method further includes: Ion implantation is performed on the substrate at both sides of the word line gate line in the functional area away from the erase gate line to form a plurality of drain lines arranged along the second direction in the functional area of ​​the substrate, and the drain lines extend along the first direction.

14. The method for preparing a split-gate flash memory device according to claim 13, wherein: After forming a plurality of drain lines in the substrate, forming a plurality of the first electrical connections and the second electrical connections, and also forming a plurality of third electrical connections; the steps of forming the plurality of the first electrical connections, the second electrical connections and the third electrical connections include: forming an interlayer dielectric layer on the substrate, the word line gate line and the erase gate line; and, A plurality of the first electrical connectors, the second electrical connectors and the third electrical connectors are formed to penetrate the interlayer dielectric layer, the first electrical connectors are electrically connected to the portion of the source line located in the first connection area, the second electrical connectors are electrically connected to the second portion of the erase gate line, and the third electrical connectors are electrically connected to the drain line.

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