Semiconductor device, high electron mobility transistor, and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the semiconductor device, in particular a high electron mobility transistor (HEMT) having a back barrier layer for blocking electron leakage and increasing a threshold voltage. In one embodiment, a semiconductor device includes: a gallium nitride (GaN) layer; a front barrier layer above the GaN layer; a source electrode, a drain electrode, and a gate electrode formed above the front barrier layer; a 2-dimensional electron gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer includes aluminum nitride (AlN).

Description

Technical Field

[0001] The technology described in the embodiments of the present invention generally relates to semiconductor devices, and more particularly, to semiconductor devices, high electron mobility transistors, and methods for manufacturing the same. Background Art

[0002] High Electron Mobility Transistors (HEMTs) are a type of solid-state transistor. Typically, HEMTs are made of smaller bandgap semiconductor materials, such as silicon (Si) and gallium arsenide (GaAs), which have higher source resistance, lower breakdown voltage, and poor performance at high frequencies. Larger bandgap semiconductor materials, such as gallium nitride (GaN), which can also provide higher peak and saturation electron velocity values, have become promising candidate materials for solving the aforementioned problems. In addition, GaN-based HEMTs having an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) structure in which a 2-dimensional electron gas (2-DEG) with high electron mobility is formed at the AlGaN / GaN interface have been developed for high frequency, high temperature, and high power applications.

[0003] However, electron leakage in the 2-DEG in AlGaN / GaN HEMTs can increase source-drain leakage current and thus reduce the threshold voltage, thereby degrading device performance. Therefore, there is a need to develop methods for improving the performance of AlGaN / GaN HEMTs, particularly methods for reducing source-drain leakage current and increasing threshold voltage. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a gallium nitride layer; a front barrier layer located above the gallium nitride layer; a source electrode, a drain electrode and a gate electrode formed above the front barrier layer; a two-dimensional electron gas located in the gallium nitride layer at a first interface between the gallium nitride layer and the front barrier layer; and a back barrier layer located in the gallium nitride layer, wherein the back barrier layer comprises aluminum nitride.

[0005] An embodiment of the present invention provides a high electron mobility transistor, comprising: a gallium nitride layer; a front barrier layer located above the gallium nitride layer; a source electrode, a drain electrode and a gate electrode formed above the front barrier layer; a two-dimensional electron gas located in the gallium nitride layer at a first interface between the gallium nitride layer and the front barrier layer; and a back barrier layer located in the gallium nitride layer, wherein the back barrier layer comprises aluminum nitride.

[0006] An embodiment of the present invention provides a method for manufacturing a high electron mobility transistor, comprising: forming a first portion of a gallium nitride layer; depositing a back barrier layer on the first portion of the gallium nitride layer; forming a second portion of the gallium nitride layer above the back barrier layer; depositing a front barrier layer on the second portion of the gallium nitride layer; and forming a source electrode, a drain electrode, and a gate electrode on the front barrier layer, wherein the back barrier layer comprises aluminum nitride, and wherein a two-dimensional electron gas in the second portion of the gallium nitride layer is at a first interface between the second portion of the gallium nitride layer and the front barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention are best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of illustration.

[0008] Figure 1 A flow chart illustrating an exemplary method for forming a high electron mobility transistor (HEMT) with a post-barrier layer according to some embodiments of the present invention.

[0009] Figures 2A to 2J Cross-sectional views of an exemplary high electron mobility transistor (HEMT) with a post-barrier layer during various fabrication stages are shown in accordance with some embodiments of the present invention.

[0010] Figure 3 A cross-sectional diagram of a conduction band of a high electron mobility transistor (HEMT) with a post-barrier layer in an equilibrium state is shown according to some embodiments of the present invention.

[0011] Figure 4A A comparison of DC transfer characteristics (source-drain current versus gate-source voltage) in a semi-logarithmic scale of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown.

[0012] Figure 4B A comparison of DC transfer characteristics (source-drain current and gate-source voltage) of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown.

[0013] Figure 4C A p-pipe diagram showing drain leakage current of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention.

[0014] Figure 4DA p-pole diagram showing source leakage current of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention.

[0015] Figure 5A A comparison of DC transfer characteristics (source-drain current versus gate-source voltage) in a semi-logarithmic scale of a high electron mobility transistor (HEMT) with a post-barrier layer at different locations and a HEMT without a post-barrier layer is shown according to some embodiments of the present invention.

[0016] Figure 5B A comparison of DC transfer characteristics (source-drain current and source-drain voltage) of a high electron mobility transistor (HEMT) with a post-barrier layer at different locations and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown.

[0017] Figure 5C Wafer mapping of thresholds of high electron mobility transistors (HEMTs) with post-barrier layers at different locations according to some embodiments of the present invention is shown. DETAILED DESCRIPTION

[0018] The following disclosure describes various exemplary embodiments for implementing the different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these components and arrangements are only examples and are not intended to be limiting. For example, it should be understood that when an element is referred to as being "connected to" another element or "coupled to" another element, it can be directly connected to another element or coupled to another element, or there can be one or more intervening elements.

[0019] The present invention provides various embodiments of a high electron mobility transistor (HEMT) having a post-barrier layer and a method for manufacturing a HEMT to reduce electron leakage in a 2-DEG, thereby further improving the threshold voltage and performance of the HEMT device.

[0020] Figure 1 1 is a flow chart showing a method 100 for forming a high electron mobility transistor (HEMT) with a post-barrier layer according to some embodiments of the present invention. It should be noted that the method 100 is only an example and is not intended to limit the present invention. Therefore, it should be understood that the method 100 may be used in the following embodiments. Figure 1 Additional operations are provided before, during, and after the method 100, and some other operations may only be briefly described herein. In some embodiments, the operations of the method 100 may be similar to those of Figures 2A to 2J , which will be discussed in further detail below.

[0021] Reference Figure 1The method 100 begins with operation 102 of setting and preparing a substrate according to some embodiments. In some embodiments, the substrate includes <111> oriented Si on the surface of the substrate. The method 100 continues with operation 104 of depositing a buffer layer on the substrate. In some embodiments, according to some embodiments, the buffer layer is deposited on the polished surface of the substrate. In some embodiments, the buffer layer includes a group III-Nitride compound semiconductor to reduce the lattice mismatch between the substrate and the subsequent GaN layer (e.g., AlN and AlGaN). According to some embodiments, the method 100 continues with operation 106 of depositing a first GaN layer over the first buffer layer on the substrate. In some embodiments, the first GaN layer is conductive and has a resistivity higher than the resistivity of the second GaN layer. The method 100 continues with operation 108 of depositing a second GaN layer over the first GaN layer. In some embodiments, the second GaN layer does not contain intentional doping and is an intrinsic GaN layer having a thickness in the range of 200 nanometers to 4000 nanometers. According to some embodiments, the method 100 continues with operation 110 of depositing a post-barrier layer over the second GaN layer. In some embodiments, the back barrier layer includes a Group III nitride compound semiconductor including at least one of aluminum (Al), gallium (Ga), and indium (In) in the form of a binary, ternary, or tertiary compound. In some embodiments, the back barrier layer includes Al x Ga 1-x N, where 0≤x≤1. According to some embodiments, method 100 continues with operation 112 of depositing a third GaN layer on the post-barrier layer. In some embodiments, the third GaN layer does not contain intentional doping and is an intrinsic GaN layer having a thickness in a range of 25 nanometers to 350 nanometers. In some embodiments, the sum of the thickness of the second GaN layer and the thickness of the third GaN layer is in a range of 200 nanometers to 4000 nanometers. According to some embodiments, method 100 continues with operation 114 of depositing a pre-barrier layer over the third GaN layer and forming a fourth GaN layer over the pre-barrier layer. In some embodiments, the pre-barrier layer includes a Group III nitride compound semiconductor, including at least one of: aluminum (Al), gallium (Ga), and indium (In) in the form of a binary, ternary, or tertiary compound. In some embodiments, the pre-barrier layer includes Al x Ga 1-x N, wherein 0≤x≤1. In some embodiments, a front barrier layer is formed on the third GaN layer to form a 2-DEG.

[0022] The method 100 continues with operation 116 of etching the fourth GaN layer to form an island region and expose a portion of the front barrier layer. At operation 118, the exposed front barrier layer is etched according to a pattern. At operation 120, a metal material is deposited onto the etched front barrier layer to form source and drain electrodes (i.e., source and drain contacts), thereby forming source and drain regions of the HEMT. In some embodiments, a doped semiconductor material is deposited on the etched front barrier layer before depositing the metal material to form the source and drain. At operation 122, a metal material is deposited onto the island region of the fourth GaN layer to form a gate electrode (i.e., gate contact), thereby forming a gate of the HEMT.

[0023] As mentioned above, Figures 2A to 2J 1 shows a cross-sectional view of an exemplary high electron mobility transistor (HEMT) with a post-barrier layer during various fabrication stages according to some embodiments of the present invention. Figures 2A to 2J Although the figure shows a HEMT 200, it is understood that the IC may include other components that are not shown for clarity of illustration. Figures 2A to 2J Several other devices shown in the figure, such as resistors, capacitors, inductors, fuses, etc.

[0024] Figure 2A is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The substrate 202 is at one of the various stages of fabrication of operation 102. In some embodiments, the substrate 202 is a Si substrate. In some embodiments, the substrate 202 is a <111> In some embodiments, the substrate 202 has a surface orientation of 0.0° to 0.5°. In some embodiments, the substrate 202 has a doping type and a resistivity of 1000 ohms per centimeter to 3000 ohms per centimeter. In some embodiments, the substrate 202 is cleaned using an RCA cleaning process and a vacuum annealing process. Alternatively, the substrate 202 may include other basic semiconductor materials, such as germanium (Ge). The first substrate 202 may also include a compound semiconductor, such as sapphire, silicon carbide (SiC), gallium arsenide, GaN, indium arsenide (InAs), and indium phosphide (In2P3). The substrate 202 may include an alloy semiconductor, such as SiGe, SiGeC, gallium arsenide phosphide (GaAsP), and gallium indium phosphide (GaInP). In some embodiments, SiC is one of the following polytypes: 4H, 3C, 6H, and 15R. In one embodiment, the substrate 202 includes an epitaxial layer.

[0025] Figure 2BA cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 including a substrate 202 and a buffer layer 204 at one of various stages of fabrication corresponding to Figure 1 operation 104. In some embodiments, before depositing the buffer layer 204 on the polished surface (e.g., Si<111>) of the substrate 202, the substrate 202 is etched with a buffered oxide etchant that typically contains hydrofluoric acid (HF) or by vacuum annealing at a high temperature in the range of 900 °C to 1200 °C to remove the native oxide layer formed on the polished surface of the substrate 202.

[0026] In some embodiments, the buffer layer 204 includes a Group III nitride compound semiconductor, including at least one of the following: aluminum (Al), gallium (Ga), and indium (In) in the form of a binary, ternary, or tertiary compound. In some embodiments, the buffer layer 204 is formed on the polished Si<111> surface to reduce the lattice mismatch between the substrate 202 and subsequent layers in the HEMT 200 (e.g., the first GaN layer). In some embodiments, the buffer layer 204 is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the buffer layer 204 has a thickness in the range of about 100 nanometers (nm) to 350 nanometers (nm). In some embodiments, the buffer layer includes a graded aluminum gallium nitride layer (Al x Ga 1-x N), where the value of x is the aluminum content in the aluminum gallium composition and 0 < x < 1. In some embodiments, the graded aluminum gallium nitride layer includes multiple layers, where the value of x decreases across the multiple layers from the bottom layer to the top layer. For example, the graded aluminum gallium nitride layer includes three layers with the following x ratios: a bottom layer in the range of 0.5 to 0.9, an intermediate layer in the range of 0.4 to 0.7, and a top layer in the range of 0.1 to 0.5. In some embodiments, the thickness of the buffer layer 204 is in the range of 500 nanometers to 2500 nanometers.

[0027] Figure 2C A cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 including at one of various stages of fabrication corresponding to Figure 1The substrate 202, the buffer layer 204, and the first GaN layer 206 at one of the various stages of fabrication of operation 106 of FIG. In some embodiments, the first GaN layer 206 is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the thickness of the first GaN layer 206 is in a range of 200 nanometers to 4000 nanometers. In some embodiments, the first GaN layer 206 is a conductive GaN layer. In some embodiments, the conductive GaN layer 206 is doped with a p-type dopant including at least one of the following elements: carbon (C), iron (Fe), magnesium (Mg), and zinc (Zn). The first GaN layer 206 has a resistivity higher than that of the channel layer to increase the breakdown voltage of the HEMT device structure.

[0028] Figure 2D is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The substrate 202, the buffer layer 204, the first GaN layer 206, and the second GaN layer 208A at one of the various stages of fabrication of operation 108 of FIG. In some embodiments, the second GaN layer 208A is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the thickness of the second GaN layer 208A is in a range of 200 nanometers to 3625 nanometers. In some embodiments, the second GaN layer 208A is an intrinsic GaN layer. In some embodiments, the intrinsic GaN layer 208A does not contain intentional doping. Compared to the buffer layer 204, the second GaN layer 208A has a lower resistivity to improve the current performance of the HEMT device.

[0029] Figure 2E is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The back barrier layer 210 and the third GaN layer 208B are fabricated at one of the various stages of operations 110 and 112. In some embodiments, the back barrier layer 210 includes a Group III nitride compound semiconductor including at least one of aluminum (Al), gallium (Ga), and indium (In) in the form of a binary, ternary, or tertiary compound. In some embodiments, the back barrier layer 210 includes Al x Ga 1-xN, where 0≤x≤1. In some embodiments, the back barrier layer 210 is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the back barrier layer 206 has a thickness in the range of 0.2 nm to 15 nm. In some embodiments, the back barrier layer 210 is an AlN layer.

[0030] In some embodiments, the third GaN layer 208B is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the third GaN layer 208B has a thickness of about 25 nanometers to 350 nanometers. In some embodiments, the sum of the thickness of the second GaN layer 208A and the thickness of the third GaN layer 208B is in the range of 200 nanometers to 4000 nanometers. In some embodiments, the third GaN layer 208B is an intrinsic GaN layer. In some embodiments, the intrinsic GaN layer 208B does not contain intentional doping and has a lower resistivity than the buffer layer.

[0031] Figure 2F is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The front barrier layer 212 and the fourth GaN layer 214 at one of the various stages of fabrication of operation 114. In some embodiments, the front barrier layer 212 includes a Group III nitride compound semiconductor including at least one of aluminum (Al), gallium (Ga), and indium (In) in the form of a binary, ternary, or tertiary compound. In some embodiments, the front barrier layer 212 includes Al x Ga 1-x N, where 0≤x≤1. In some embodiments, a front barrier layer 212 is formed on the third GaN layer 208B to form a 2-DEG. In some embodiments, the front barrier layer 212 is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the thickness of the front barrier layer 212 is in the range of 10 nanometers to 100 nanometers. In some embodiments, the thickness of the front barrier layer 212 is determined by the Al composition of the front barrier layer 212 (that is, the value of x).

[0032] In some embodiments, the fourth GaN layer 214 is deposited using one of the following techniques: metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and physical vapor deposition (PVD). In some embodiments, the fourth GaN layer 214 has a thickness of about 20 nanometers to 100 nanometers. In some embodiments, the fourth GaN layer 214 is a p-doped GaN layer (p-GaN) and a p-doped AlGaN (p-AlGaN), and contains at least one of the following elements: carbon (C), iron (Fe), magnesium (Mg), and zinc (Zn) in the range of 1E+18 atoms / cm3 to 1E+21 atoms / cm3.

[0033] Figure 2G is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 Operation 116 is one of the various stages of fabrication of a patterned GaN layer 214. The GaN layer 214 is patterned to form Figure 2G In some embodiments, the patterning of the GaN layer 214 includes, for example: (i) forming a mask layer (e.g., photoresist, etc.) over the GaN layer 214, the mask layer including an opening over the portion of the GaN layer 214 to be removed; and (ii) removing the portion of the GaN layer 214 not exposed by the mask layer (e.g., via a wet or dry etching process). Figure 2G As shown in FIG. 2 , after patterning of the GaN layer 214, portions of the front barrier layer 212 are exposed without covering the GaN layer 214. In some embodiments, the island region of the GaN layer 214 defines the location of the gate to be formed thereon and has a width W_p in the range of 1 micron to 3 microns.

[0034] Figure 2H is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 including a Figure 1 The front barrier layer 212 is patterned at one of the various stages of fabrication of operation 118. The front barrier layer 212 is patterned to form Figure 2H, and the two grooves 215 and the groove 217 are shown in FIG. In some embodiments, the patterning of the front barrier layer 212 includes, for example: (i) forming a mask layer (e.g., photoresist, etc.) over the exposed front barrier layer 212, the mask layer including an opening over the portion of the front barrier layer 212 to be removed; and (ii) removing the portion of the front barrier layer 212 not exposed by the mask layer (e.g., via a wet or dry etching process). In some embodiments, the groove 215 of the patterned front barrier layer 212 defines the location where the source is to be formed, and has a width W_S in the range of 1 micron to 5 microns. In some embodiments, the groove 217 of the patterned front barrier layer 212 defines the location where the drain is to be formed, and has a width W_D in the range of 1 micron to 5 microns.

[0035] Fig.2I is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The source electrode 216 and the drain electrode 218 of the HEMT 200 are at one of the various stages of fabrication of the operation 120. Fig.2I As shown in , the source electrode 216 is deposited into the groove 215 of the front barrier layer 212, and the drain electrode 218 is deposited into the groove 217 of the front barrier layer 212. Therefore, the source electrode 216 has a width W_S in the range of 1 micron to 1000 microns; and the drain electrode 218 has a width W_D in the range of 1 micron to 1000 microns. In some embodiments, the source electrode 216 and the drain electrode 218 may be made of a stack of metal layers. The metal layer may be made of: Co, Ni, W, Pt, Ta, Pd, Mo, TiN, Al-Cu alloy or other applicable materials. In some embodiments, each of the source electrode 216 / drain electrode 218 includes a bottom Ti / TiN layer, an AlCu layer overlying the bottom Ti / TiN layer, and a top Ti layer overlying the AlCu layer. In some embodiments, the source electrode 216 and the drain electrode 218 are deposited using one of the following techniques: chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or other applicable processes.

[0036] Figure 2J is a cross-sectional view of a HEMT 200 according to some embodiments of the present invention, the HEMT 200 includes a Figure 1 The gate electrode 220 of the HEMT 200 is at one of the various stages of fabrication of operation 122. Figure 2JAs shown in , the gate electrode 220 is deposited on the island region of the fourth GaN layer 214. In some embodiments, the gate electrode 220 has a width in the range of 1 micron to 3 microns. In some embodiments, the distance D1 between the source electrode 216 and the island region of the fourth GaN layer 214 is in the range of 0.1 micron to 5 microns; and the distance D2 between the drain electrode 218 and the island region of the fourth GaN layer 214 is in the range of 10 microns to 40 microns. In some embodiments, the gate electrode 220 can be made of a stack of metal layers. The metal layer can be made of: Co, Ni, W, Pt, Ta, Pd, Mo, TiN, Al-Cu alloy or other applicable materials. In some embodiments, the gate electrode 220 includes a bottom Ti / TiN layer, an AlCu layer overlying the bottom Ti / TiN layer, and a top Ti layer overlying the AlCu layer. In some embodiments, the gate electrode 220 is deposited using one of the following techniques: chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or other applicable processes.

[0037] In some embodiments, the HEMT 200 may further include a passivation layer (not shown) formed over the source electrode 216, the drain electrode 218, the gate electrode 220, and the island region of the fourth GaN layer 214. The passivation layer may be made of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the passivation layer is deposited using one of the following techniques: chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0038] Figure 3 A conductive band profile 300 of a high electron mobility transistor (HEMT) with a post-barrier layer in an equilibrium state according to some embodiments of the present invention is shown. In the illustrated embodiment, the conductive band profile 300 is shown vertically through the HEMT 200 from the fourth GaN layer 214 to the first GaN layer 206. In the illustrated embodiment, the band diagram 300 includes six regions corresponding to the fourth GaN layer 214, the pre-barrier layer 212, the third GaN layer 208B, the post-barrier layer 210, the second GaN layer 208A, and the first GaN layer 206: a first region 302, a second region 304, a third region 306, a fourth region 308, a fifth region 310, and a sixth region 312, respectively. In the illustrated embodiment, the conductive band edges of the corresponding layers of the HEMT 200 are depicted as solid lines 320, and the Fermi levels of the corresponding layers of the HEMT 200 are depicted as dashed lines 322.

[0039] At the interface between the second region 304 corresponding to the front barrier layer 212 and the third region 306 corresponding to the third GaN layer 208B, the 2-DEG 314 in the third GaN layer 208B is generated by spontaneous piezoelectric polarization and donor states on the front barrier layer 212 (i.e., AlGaN). Different from HEMTs without a back barrier layer, electrons in the 2-DEG 314 can be blocked by the fourth region 308 corresponding to the back barrier layer 210, which is caused by the larger bandgap and larger conduction band offset of the back barrier layer 210. In some embodiments, the back barrier layer 210 is an electron blocking layer (EBL), which effectively reduces electron leakage from the 2-DEG, thus improving the confinement of electrons in the 2-DEG.

[0040] Figure 4A Shows a comparison of the DC transfer characteristics 400 (source-drain current versus gate voltage) in semi-logarithmic scale of a high electron mobility transistor (HEMT) 200 with a back barrier layer and a HEMT without a back barrier layer according to some embodiments of the present invention. In some embodiments, the DC transfer characteristics 400 are measured on the HEMT at a constant source-drain voltage (Vds) of 0.1 volts. In the illustrated embodiment, at a given gate voltage (Vg) in the first region 410 (i.e., Vg ≤ 0 volts), the source-drain current (Ids) (in milliamperes per millimeter (mA / mm)) 402 of the HEMT with a back barrier layer is higher than the Ids 404 of the HEMT without a back barrier layer.

[0041] In the illustrated embodiment, at a given Vg in the second region 412 (i.e., 0 < Vg ≤ 3 volts), the Ids 402 of the HEMT with a back barrier layer is generally lower than the Ids 404 of the HEMT without a back barrier layer. The threshold voltage of the HEMT with a back barrier layer is higher than the threshold voltage of the HEMT without a back barrier layer. In one embodiment, for a HEMT with a back barrier layer having a vertical distance of about 100 nanometers from the front barrier layer, that is, when Figure 2J the third GaN layer 208B in has a thickness of about 100 nanometers, the HEMT with a back barrier layer has a threshold voltage that is about 25% higher than the threshold voltage of the HEMT without a back barrier layer. In some embodiments, the threshold voltage is measured by a constant current method with Vt linearly measured. When Id meets certain user-specified conditions, Vt is simply defined as Vgs.

[0042] Figure 4BA comparison of DC transfer characteristics 420 (source-drain current versus gate-source voltage) of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown. In some embodiments, the DC transfer characteristics 420 on the HEMT are measured at a constant source-drain voltage (Vds). In the illustrated embodiment, at 6 volts Vg, the saturated Ids 422 of the HEMT with the post-barrier layer is less than the saturated Ids 424 of the HEMT without the post-barrier layer.

[0043] Figure 4C A p-pipe graph 430 of gate leakage current of a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown. In the embodiment shown, the gate leakage current (Ig_leak) is measured at a constant Vds of 200V and a Vg of 0 volts.

[0044] Figure 4D A p-pipe graph 440 of source leakage current for a high electron mobility transistor (HEMT) with a post-barrier layer and a HEMT without a post-barrier layer according to some embodiments of the present invention is shown. In the illustrated embodiment, the source-drain leakage current (Ids_leak) is measured at a constant Vds of 200 volts and a Vg of 0 volts. In the graph, 1 represents 100% on the y-axis, and the x-axis plots the leakage source-drain current (in milliamps / mm).

[0045] Figure 5A A comparison of DC transfer characteristics 500 (source-drain current versus gate-source voltage) in a semi-logarithmic scale of a high electron mobility transistor (HEMT) with a back barrier layer at different locations and a HEMT without a back barrier layer according to some embodiments of the present invention is shown. In some embodiments, the DC transfer characteristics 500 on the HEMT are measured at a constant source-drain voltage (Vds) of 0.1 volts. In the illustrated embodiment, the back barrier layer is an AlN layer with a thickness of 10 nanometers located in the intrinsic GaN layer (that is, between the second GaN layer 208A and the third GaN layer 208B) and has a vertical distance of 25 nanometers, 100 nanometers, and 350 nanometers from the front barrier layer 212. In the illustrated embodiment, at a given gate voltage (Vg) in the sub-threshold region 510 (i.e., Vg≤0 volts), the Ids 502 / Ids 504 / Ids 506 of the HEMT having the back barrier layer located at 25 nanometers, 100 nanometers, and 350 nanometers from the front barrier layer, respectively, are higher than the Ids 508 of the HEMT without the back barrier layer.

[0046] In the illustrated embodiment, at a given gate voltage (Vg) in the sub-threshold exponential region 512 (i.e., 0 < Vg ≤ 2 volts), the Ids 502 / Ids 504 / Ids 506 of the HEMT having back barrier layers located at 25 nanometers, 100 nanometers, and 350 nanometers from the front barrier layer respectively are higher than the Ids 508 of the HEMT without a back barrier layer. The threshold voltage of the HEMT having a back barrier layer is higher than the threshold voltage of the HEMT without a back barrier layer.

[0047] Figure 5B Shows a comparison of the DC transfer characteristics 520 (source-drain current vs. source-drain voltage) of high electron mobility transistors (HEMTs) having back barrier layers at different positions with HEMTs without back barrier layers according to some embodiments of the present invention. In the illustrated embodiment, the leakage Ids is measured at a constant Vg of 0 volts.

[0048] Figure 5C Shows a wafer map 530 of the thresholds of high electron mobility transistors (HEMTs) having back barrier layers at different positions according to some embodiments of the present invention.

[0049] In one embodiment, a semiconductor device includes: a gallium nitride (GaN) layer; a front barrier layer located above the GaN layer; a source electrode, a drain electrode, and a gate electrode formed above the front barrier layer; a two-dimensional electron gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer is composed of aluminum nitride (AlN).

[0050] In a related embodiment, the front barrier layer includes Al x Ga 1-x N, and wherein 0 ≤ x ≤ 1.

[0051] In a related embodiment, the back barrier layer is in the gallium nitride layer, separating a first portion of the gallium nitride layer from the first interface by a first thickness.

[0052] In a related embodiment, the first thickness is in the range of 25 nanometers to 350 nanometers.

[0053] In a related embodiment, the second thickness of the back barrier layer is in the range of 0.5 nanometers to 10 nanometers.

[0054] In a related embodiment, electrons in the two-dimensional electron gas in the gallium nitride layer at the first interface are blocked by a second interface between the first portion of the gallium nitride layer and the back barrier layer.

[0055] In a related embodiment, the third thickness of the gallium nitride layer is in a range between 300 nanometers and 1500 nanometers.

[0056] In another embodiment, a high electron mobility transistor (HEMT) includes: a gallium nitride (GaN) layer, a front barrier layer located above the GaN layer; a source electrode, a drain electrode and a gate electrode formed above the front barrier layer; a two-dimensional electron gas (2-DEG) located in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer located in the GaN layer, wherein the back barrier layer is composed of aluminum nitride (AlN).

[0057] In a related embodiment, the front barrier layer comprises Al x Ga 1-x N, and where 0≤x≤1.

[0058] In a related embodiment, the post-barrier layer is located in the gallium nitride layer and is separated from the first interface by a first thickness of a first portion of the gallium nitride layer.

[0059] In a related embodiment, the first thickness is within a range of 25 nanometers and 350 nanometers.

[0060] In a related embodiment, the second thickness of the post-barrier layer is in a range between 0.5 nanometers and 10 nanometers.

[0061] In a related embodiment, electrons in the 2-dimensional electron gas in the gallium nitride layer at the first interface are blocked by a second interface between the first portion of the gallium nitride layer and the post-barrier layer.

[0062] In a related embodiment, the third thickness of the gallium nitride layer is in a range between 300 nanometers and 1500 nanometers.

[0063] Furthermore, in another embodiment, a method for manufacturing a high electron mobility transistor includes: forming a first portion of a gallium nitride (GaN) layer; depositing a back barrier layer on the first portion of the GaN layer; forming a second portion of the GaN layer above the back barrier layer; depositing a front barrier layer on the second portion of the GaN layer; and forming a source electrode, a drain electrode, and a gate electrode on the front barrier layer, wherein the back barrier layer is composed of aluminum nitride (AlN), and wherein a two-dimensional electron gas (2-DEG) in the second portion of the GaN layer is at a first interface between the second portion of the GaN layer and the front barrier layer.

[0064] In a related embodiment, the front barrier layer comprises Al x Ga 1-x N, and where 0≤x≤1.

[0065] In a related embodiment, a first thickness of the second portion of the gallium nitride layer is in a range between 25 nanometers and 350 nanometers, and a second thickness of the gallium nitride layer is in a range between 300 nanometers and 1500 nanometers.

[0066] In a related embodiment, the third thickness of the post-barrier layer is in a range between 0.5 nanometers and 10 nanometers.

[0067] In a related embodiment, electrons in the 2-dimensional electron gas in the gallium nitride layer at the first interface are blocked by a second interface between the first portion of the gallium nitride layer and the post-barrier layer.

[0068] In a related embodiment, the method further comprises: before forming the first portion of the gallium nitride layer, preparing a buffer layer on the silicon substrate, wherein the buffer layer comprises Al y Ga 1-y N, and the surface orientation of the silicon substrate is <111> ; and forming a conductive gallium nitride layer on the buffer layer.

[0069] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures for implementing the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that this equivalent construction does not depart from the spirit and scope of the present invention, and those skilled in the art can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising: a first gallium nitride layer comprising a first resistivity; A front barrier layer, located above the first gallium nitride layer; A source electrode, a drain electrode and a gate electrode are formed on the front barrier layer; A 2D electron gas located in the first gallium nitride layer at a first interface between the first gallium nitride layer and the front barrier layer; a back barrier layer, located below the first gallium nitride layer, wherein the back barrier layer comprises aluminum nitride; a second gallium nitride layer disposed below the post-barrier layer, wherein the second gallium nitride layer comprises a second resistivity; and A third gallium nitride layer is disposed below the second gallium nitride layer, wherein the third gallium nitride layer comprises a third resistivity, The third resistivity is higher than the second resistivity. 2 . The semiconductor device according to claim 1 , wherein the front barrier layer comprises AlxGa1-xN, and wherein 0≤x≤1. 3 . The semiconductor device of claim 1 , wherein the back barrier layer is located below the first gallium nitride layer and is separated from the first interface by a first thickness of a first portion of the first gallium nitride layer. The semiconductor device according to claim 3 , wherein the first thickness is in a range of 25 nanometers to 350 nanometers. 5 . The semiconductor device according to claim 1 , wherein a second thickness of the post-barrier layer is in a range between 0.5 nm and 10 nm. 6 . The semiconductor device of claim 3 , wherein electrons in the 2-dimensional electron gas in the first gallium nitride layer at the first interface are blocked by a second interface between the first portion of the first gallium nitride layer and the back-barrier layer. 7 . The semiconductor device of claim 1 , wherein a third thickness of the first gallium nitride layer is in a range between 300 nanometers and 1500 nanometers.

8. A high electron mobility transistor, comprising: a first gallium nitride layer; A front barrier layer, located above the first gallium nitride layer; A source electrode, a drain electrode and a gate electrode are formed on the front barrier layer; A 2D electron gas located in the first gallium nitride layer at a first interface between the first gallium nitride layer and the front barrier layer; a back barrier layer, located below the first gallium nitride layer, wherein the back barrier layer comprises aluminum nitride; a second gallium nitride layer disposed below the post-barrier layer, wherein the second gallium nitride layer comprises a second resistivity; and A third gallium nitride layer is disposed below the second gallium nitride layer, wherein the third gallium nitride layer comprises a third resistivity, The third resistivity is higher than the second resistivity. 9 . The high electron mobility transistor according to claim 8 , wherein the front barrier layer comprises AlxGa1-xN, and wherein 0≤x≤1. 10 . The high electron mobility transistor of claim 8 , wherein the post-barrier layer is located below the first gallium nitride layer and is separated from the first interface by a first thickness of a first portion of the first gallium nitride layer. 11 . The high electron mobility transistor of claim 10 , wherein the first thickness is in the range of 25 nanometers to 350 nanometers.

12. The high electron mobility transistor according to claim 8, wherein the second thickness of the back barrier layer is in the range of 0.5 nanometers to 10 nanometers.

13. The high electron mobility transistor according to claim 10, wherein electrons in the two-dimensional electron gas in the first gallium nitride layer at the first interface are blocked by a second interface between the first portion of the first gallium nitride layer and the back barrier layer.

14. The high electron mobility transistor according to claim 8, wherein the third thickness of the first gallium nitride layer is in the range of 300 nanometers to 1500 nanometers.

15. A method for manufacturing a high electron mobility transistor, comprising: forming a third gallium nitride layer, wherein the third gallium nitride layer has a third resistivity; depositing a second gallium nitride layer on the third gallium nitride layer, wherein the second gallium nitride layer has a second resistivity, and the third resistivity is higher than the second resistivity; depositing a back barrier layer on the second gallium nitride layer; forming a first gallium nitride layer above the back barrier layer; depositing a front barrier layer on the first gallium nitride layer; and forming a source electrode, a drain electrode, and a gate electrode on the front barrier layer, wherein the back barrier layer includes aluminum nitride, and wherein the two-dimensional electron gas in the first gallium nitride layer is at a first interface between the first gallium nitride layer and the front barrier layer.

16. The method according to claim 15, wherein the front barrier layer includes AlxGa1-xN, and wherein 0 ≤ x ≤ 1.

17. The method according to claim 15, wherein the first thickness of the first gallium nitride layer is in the range of 25 nanometers to 350, and the second thickness of the second gallium nitride layer is in the range of 300 nanometers to 1500 nanometers.

18. The method according to claim 15, wherein the third thickness of the back barrier layer is in the range of 0.5 nanometers to 10 nanometers.

19. The method according to claim 15, wherein electrons in the two-dimensional electron gas in the first gallium nitride layer at the first interface are blocked by a second interface between the second gallium nitride layer and the back barrier layer.

20. The method according to claim 15, the method further comprising: before forming the second gallium nitride layer, preparing a buffer layer on a silicon substrate, wherein the buffer layer includes AlyGa1-yN, 0 < y < 1, and the surface orientation of the silicon substrate is <111>; and forming a conductive gallium nitride layer as the third gallium nitride layer on the buffer layer.

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