Semiconductor devices

Abstract

The present invention provides a semiconductor device, comprising: a semiconductor substrate; a plurality of peaks of doping concentration, which are arranged on the back side of the semiconductor substrate; a flat portion, which is arranged between the plurality of peaks in the depth direction of the semiconductor substrate and has a doping concentration that is 2.5 times or more of the substrate concentration of the semiconductor substrate, at least one of the plurality of peaks is a first peak arranged at a position closer to the front side than the flat portion, and the doping concentration of the first peak is less than twice the doping concentration of the flat portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device including a buffer region functioning as a field stop layer (see, for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2016 / 0141399 Summary of the invention

[0006] Technical issues

[0007] Conventional semiconductor devices may oscillate at a low collector-emitter voltage when short-circuited.

[0008] Technical Solution

[0009] In order to solve the above-mentioned problem, in a first embodiment of the present invention, a semiconductor device is provided, which comprises: a semiconductor substrate; a plurality of peaks of doping concentration, which are arranged on the back side of the semiconductor substrate; and a flat portion, which is arranged between the plurality of peaks in the depth direction of the semiconductor substrate and has a doping concentration that is more than 2.5 times the substrate concentration of the semiconductor substrate, at least one of the plurality of peaks is a first peak arranged at a position closer to the front side than the flat portion, and the doping concentration of the first peak is less than 2 times the doping concentration of the flat portion.

[0010] The doping concentration of the flat portion may be 10 times or less of the substrate concentration of the semiconductor substrate.

[0011] The depth position of the first peak may be 25 μm or more and 35 μm or less.

[0012] The semiconductor device may include a gently inclined region, which is disposed at a position closer to the front side of the semiconductor substrate than the first peak, and has a doping concentration gradient in the depth direction that is gentler than the first peak. The slope α of the doping concentration in the gently inclined region may be greater than 750 and less than 1500. The unit of the slope α is [ / cm].

[0013] The thickness of the gently sloped region may be 5 μm or more and 10 μm or less.

[0014] The plurality of peaks may include a second peak that is disposed at a second depth position from the front surface side of the semiconductor substrate and has a doping concentration that is twice or less than a doping concentration of the flat portion.

[0015] The doping concentration of at least one of the plurality of peaks may be 1.5 times or less of the doping concentration of the flat portion.

[0016] The positions of the plurality of peaks in the depth direction may correspond to the depths of the peaks of the hydrogen chemical concentration.

[0017] The planar portion may include a first planar portion, and a second planar portion having a doping concentration different from that of the first planar portion.

[0018] The doping concentration of the second flat portion may be within ±10% of the doping concentration of the first flat portion.

[0019] The plurality of peaks may include a first peak, a second peak, a third peak, and a fourth peak in order from the front side in the depth direction, and the first flat portion may be provided between the first peak and the second peak.

[0020] The second flat portion may be disposed between the third peak and the fourth peak.

[0021] The integrated concentration of the dopant from the rising position of the substrate concentration on the back side to the end of the second flat portion on the back side can be 0.8×10 11 cm -2 Above and 5.0×10 11 cm -2 the following.

[0022] Multiple peaks can be set in the buffer. The oxygen chemical concentration in the buffer can be 1×10 17 cm -3 Above and 6×10 17 cm -3 the following.

[0023] A plurality of peaks of doping concentration may be present on the front side of the flat portion without a flat region between the peaks.

[0024] The positions in the depth direction of the peaks of the plurality of doping concentrations without a flat area may correspond to the positions in the depth direction of the peaks of the hydrogen chemical concentration. With respect to the plurality of doping concentrations without a flat area and the hydrogen chemical concentrations corresponding to the plurality of doping concentrations, a ratio of a valley adjacent to a predetermined peak of the hydrogen chemical concentration to the hydrogen chemical concentration of the peak may be smaller than a ratio of a valley adjacent to a predetermined peak of the doping concentration to the doping concentration of the peak.

[0025] The flat portion may be provided on the rear surface side relative to the peak of the hydrogen doping concentration distribution.

[0026] The flat portion may have a composite defect including two or more of lattice defects including vacancies, C, O, and H.

[0027] The total thickness of the flat portion may be thicker than the thickness of the semiconductor substrate below the flat portion.

[0028] The semiconductor substrate may be a MCZ substrate.

[0029] It should be noted that the above invention summary does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A An example of the configuration of the semiconductor device 100 according to the embodiment is shown.

[0031] Figure 1B It is shown Figure 1A A diagram showing an example of the a-a' cross section in FIG.

[0032] Figure 1C An example of the doping concentration distribution of the semiconductor device 100 according to the embodiment is shown.

[0033] Figure 2 An example of doping concentration distribution of Examples and Comparative Examples is shown.

[0034] Figure 3 Another example of the doping concentration distribution of the example and the comparative example is shown.

[0035] Figure 4 Modifications of the doping concentration distribution of the semiconductor device 100 according to the embodiment are shown.

[0036] Figure 5 The characteristics of the semiconductor device of the comparative example when short-circuited are shown.

[0037] Figure 6 The characteristics of the semiconductor device 100 according to the embodiment when short-circuited are shown.

[0038] Figure 7 The relationship between the backside boron ion implantation concentration and the latch-up withstand breakdown current is shown.

[0039] Figure 8 The latch-up withstand current before breakdown during short circuit in the embodiment and the comparative example is shown.

[0040] Explanation of symbols

[0041] 10···semiconductor substrate, 11···well region, 12···emitter region, 14···base region, 15···contact region, 16···accumulation region, 18···drift region, 21···front surface, 22···collector region, 23···back surface, 24···collector electrode, 29···extension portion, 30···dummy trench portion, 31···connection portion, 32···dummy insulating film, 33···dummy conductive portion, 34···dummy conductive portion, 38···interlayer insulating film, 39···extension portion, 40···gate trench portion, 41···connection portion, 42···gate insulating film, 44···gate conductive portion, 49···contact hole, 50···gate metal layer, 52···emitter electrode, 54···contact hole, 56···contact hole, 61···first terrace portion, 62···second terrace portion, 70···transistor portion, 80···diode portion, 82···cathode region, 90···buffer region, 91···peak, 92···flat portion, 93···gently inclined region, 100···semiconductor device, 110···doping concentration distribution, 120···hydrogen chemical concentration distribution, 130···substrate concentration distribution, 140···oxygen chemical concentration distribution, 510···doping concentration distribution, 550···doping concentration distribution DETAILED DESCRIPTION

[0042] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0043] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as the front surface, and the other surface is referred to as the back surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted on the substrate, etc. when actually mounted.

[0044] In this specification, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. In this specification, the plane parallel to the front surface of the semiconductor substrate is referred to as the XY plane, and the direction forming a right-hand system with the X-axis and the Y-axis, that is, the depth direction of the semiconductor substrate is referred to as the Z-axis. It should be noted that in this specification, the situation of observing the semiconductor substrate along the Z-axis direction is referred to as a top view.

[0045] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0046] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of taking electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors function as donors that supply electrons.

[0047] In this specification, the layers and regions prefixed with n or p respectively mean that electrons or holes are majority carriers. In addition, + and - marked on n and / or p respectively mean that the doping concentration is higher and lower than that of the layers and / or regions not marked with + and -. Unless otherwise specified, the units of this specification are SI units. Although cm is sometimes used to represent the unit of length, it can also be converted to meters (m) for various calculations.

[0048] In this specification, chemical concentration refers to the atomic density of an element measured regardless of the state of electrical activation. Chemical concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). In this specification, concentration per unit volume is expressed in atoms / cm 3 or / cm 3 This unit is used for chemical concentrations in semiconductor substrates, or donor or acceptor concentrations. The representation of atoms can also be omitted. Each concentration in this specification can be a value at room temperature. As an example, the value at room temperature can be a value at 300K (Kelvin) (approximately 26.9°C).

[0049] In this specification, the doping concentration refers to the concentration of the donor or acceptor dopant. The unit of doping concentration is / cm2, which is the same as the chemical concentration. 3 . In this specification, the concentration difference between the donor and the acceptor (i.e., the net doping concentration) is sometimes used as the doping concentration. The net doping concentration can be measured by the voltage-capacitance measurement method (CV method). Alternatively, the carrier concentration that can be measured by the diffusion resistance measurement method (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be used as a value in a thermal equilibrium state. In addition, the chemical concentration of the donor and the acceptor can also be used as the doping concentration. In this case, the doping concentration can be measured by the SIMS method. Unless otherwise specified, any of the above can be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doping region can be used as the doping concentration in the doping region.

[0050] When the concentration distribution of the donor, acceptor or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor or net doping in the region. When the concentrations of the donor, acceptor or net doping are almost equal, the average value of the concentrations of the donor, acceptor or net doping in the region can be used as the concentration of the donor, acceptor or net doping.

[0051] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. For example, the donor concentration of phosphorus or arsenic as a donor, or the acceptor concentration of boron as an acceptor in a silicon semiconductor is about 99% or more of their chemical concentrations.

[0052] In this specification, the dose refers to the number of ions implanted per unit area of ​​the wafer during ion implantation. Therefore, its unit is / cm 2 It should be noted that the dose of the semiconductor region can be set to the integrated concentration obtained by integrating the doping concentration in the depth direction of the semiconductor region. The unit of the integrated concentration is / cm 2 Therefore, the dose and the integrated concentration can be treated as the same thing. The integrated concentration can be set as the integrated value up to the half-maximum width, or it can be derived by removing the influence of other semiconductor regions when the spectrum overlaps with other semiconductor regions.

[0053] Therefore, in this specification, the high and low doping concentrations can be read as the high and low doses. That is, when the doping concentration of one region is higher than that of other regions, it can be understood that the dose of the one region is higher than that of other regions.

[0054] The semiconductor substrate 10 described later is implanted with hydrogen ions. In the semiconductor substrate 10, in the passage area through which the hydrogen ions pass, lattice defects mainly composed of vacancies such as monoatomic vacancies (V) and diatomic vacancies (VV) are formed by the passage of hydrogen. Atoms adjacent to the vacancies have dangling bonds. In this specification, the term "lattice defect" includes lattice defects mainly composed of vacancies, interstitial atoms and / or dislocations, and in a broad sense, donors and / or acceptors.

[0055] The entire semiconductor substrate 10 contains oxygen. The oxygen is introduced intentionally or unintentionally when manufacturing a semiconductor ingot. Hydrogen (H), vacancies (V) and oxygen (O) combine inside the semiconductor substrate 10 to form VOH defects. In addition, by heat treating the semiconductor substrate 10 to diffuse hydrogen, the formation of VOH defects is promoted. VOH defects function as donors that supply electrons. In this specification, VOH defects are sometimes referred to as hydrogen donors. The doping concentration of hydrogen donors is lower than the chemical concentration of hydrogen. For example, in a silicon semiconductor, if the ratio of the doping concentration of hydrogen donors to the chemical concentration of hydrogen is set as the activation rate, the activation rate can be a value of 0.1% to 30%. Although the deviation of the chemical concentration of the body donor when manufacturing the semiconductor substrate 10 is relatively large, the dose of hydrogen ions can be controlled with relatively high precision. Therefore, the concentration of lattice defects generated by the injection of hydrogen ions can also be controlled with high precision, and the donor concentration of the pass region can be controlled with high precision.

[0056] Figure 1A An example of the configuration of the semiconductor device 100 of the embodiment is shown. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).

[0057] The transistor section 70 is a region formed by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the front side 21 of the semiconductor substrate 10. The collector region 22 has the second conductivity type. As an example, the collector region 22 in this example is a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0058] The diode portion 80 may be a region formed by projecting the cathode region 82 onto the front surface 21 of the semiconductor substrate 10. The diode portion 80 includes a diode such as a freewheel diode (FWD) provided adjacent to the transistor portion 70 on the front surface 21 of the semiconductor substrate 10.

[0059] exist Figure 1A The area around the chip end as the edge side of the semiconductor device 100 is shown, and other areas are omitted. For example, an edge terminal structure portion can be provided in the area on the negative side in the X-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the front side 21 of the semiconductor substrate 10. The edge terminal structure portion has, for example, a guard ring, a field plate, a surface electric field reduction, and a structure obtained by combining them. It should be noted that in this example, the edge on the negative side in the X-axis direction is described for convenience, but the same is true for other edges of the semiconductor device 100.

[0060] The semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 of this example is an MCZ substrate produced by the MCZ (Magnetic field applied Czochralski) method. The MCZ substrate is more suitable for producing a larger diameter wafer than an FZ (Floating Zone) substrate produced by the FZ method.

[0061] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0062] The emitter electrode 52 and the gate metal layer 50 are made of a material including a metal. For example, at least a portion of the emitter electrode 52 may be made of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be made of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium and / or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. The emitter electrode 52 and the gate metal layer 50 are arranged to be separated from each other.

[0063] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10 via an interlayer insulating film. Figure 1A The contact hole 49 , the contact hole 54 , and the contact hole 56 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0064] The contact hole 49 connects the gate metal layer 50 to the gate conductive portion 44 in the gate trench portion 40. The gate conductive portion 44 will be described later. A plug made of tungsten or the like may be formed inside the contact hole 49.

[0065] The contact hole 56 connects the emitter electrode 52 to the dummy conductive portion 33 in the dummy trench portion 30. The dummy conductive portion 33 will be described later. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0066] The gate grooves 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate grooves 40 of this example may include two extension portions 39 extending along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 41 connecting the two extension portions 39.

[0067] Preferably, at least a portion of the connection portion 41 is formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 39 can be alleviated. At the connection portion 41 of the gate groove portion 40, the gate metal layer 50 can be connected to the gate conductive portion 44.

[0068] Similar to the gate groove portion 40, the dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The dummy groove portion 30 of this example can be formed in a curved shape at least in part, similar to the gate groove portion 40. As an example, the dummy groove portion 30 can have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy groove portion 30 can have two extension portions 29 extending along the extension direction, and a connecting portion 31 connecting the two extension portions 29.

[0069] It should be noted that, here, a dummy trench portion 30 is provided between the gate trench portions 40 in the transistor portion 70, but the number and / or arrangement of the dummy trench portions 30 relative to the gate trench portions 40 can be set according to design conditions. In addition, a so-called full gate structure can be provided in which no dummy trench portion 30 is provided in the transistor portion 70 but all gate trench portions 40 are provided.

[0070] Emitter electrode 52 is formed above gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 is set to an emitter potential. As an example, the emitter potential may be a ground potential.

[0071] The well region 11 is a region of the second conductivity type disposed at a position closer to the front surface 21 side of the semiconductor substrate 10 than the drift region 18 described later. The well region 11 is an example of a well region disposed on the edge side of the semiconductor device 100. As an example, the well region 11 is of P+ type. The well region 11 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is disposed. The diffusion depth of the dopant in the well region 11 can be set deeper than the depth of the gate groove portion 40 and the dummy groove portion 30. A portion of the gate metal layer 50 side of the gate groove portion 40 and the dummy groove portion 30 is formed in the well region 11. The ends of the gate groove portion 40 and the dummy groove portion 30 in the extension direction can be covered by the well region 11 at the bottom of the depth direction of each groove.

[0072] In the transistor portion 70, the contact hole 54 is formed above each region of the emitter region 12 and the contact region 15. In addition, in the diode portion 80, the contact hole 54 is formed above the second mesa portion 62. The contact hole 54 is not provided above the base region 14 and the well region 11 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. One or more contact holes 54 can be provided to extend along the extension direction.

[0073] The first mesa portion 61 and the second mesa portion 62 are mesa portions provided adjacent to each groove portion in the X-axis direction in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 that is sandwiched between two adjacent groove portions when the extension portion of each groove portion is regarded as one groove portion. That is, the area sandwiched between the two extension portions of the adjacent groove portions can be the mesa portion. In addition, the depth of the mesa portion can be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion.

[0074] In the transistor portion 70, the first mesa portion 61 is provided adjacent to at least one of the dummy groove portion 30 and the gate groove portion 40. In addition, at the boundary portion between the transistor portion 70 and the diode portion 80, the first mesa portion 61 is provided adjacent to the dummy groove portion 30. The first mesa portion 61 has a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the first mesa portion 61, the emitter region 12 and the contact region 15 are alternately provided in the extension direction.

[0075] In the diode portion 80, the second mesa portion 62 is provided adjacent to the dummy trench portion 30. The second mesa portion 62 has a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the second mesa portion 62, the emitter region 12 and the contact region 15 are alternately provided in the extending direction.

[0076] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 in the transistor portion 70. As an example, the base region 14 is a P-type. On the front surface 21 of the semiconductor substrate 10, the base region 14 can be provided at both ends of the first mesa portion 61 and the second mesa portion 62 in the Y-axis direction. Figure 1A Only one end portion of the base region 14 in the Y-axis direction is shown.

[0077] The base region 14-e is arranged at both ends of each mesa portion in the Y-axis direction. The base region 14-e of this example is provided in the first mesa portion 61 and the second mesa portion 62. The base region 14-e is in contact with the contact region 15 at the center side of each mesa portion. The base region 14-e is in contact with the well region 11 at the side opposite to the contact region 15.

[0078] On the front surface 21 of the first mesa portion 61, the emitter region 12 is provided to contact the gate groove portion 40. The emitter region 12 may be provided along the X-axis direction from one of two groove portions extending along the Y-axis direction sandwiching the first mesa portion 61 to the other. The emitter region 12 is also provided below the contact hole 54.

[0079] In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 in this example is of the first conductivity type. As an example, the emitter region 12 in this example is of the N+ type.

[0080] The contact region 15 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 can be provided along the X-axis direction from one of the two groove portions extending along the Y-axis direction to the other. The contact region 15 can be provided in both the first terrace portion 61 and the second terrace portion 62. The contact region 15 may or may not be in contact with the gate groove portion 40. In addition, the contact region 15 may or may not be in contact with the dummy groove portion 30. The contact region 15 is also provided below the contact hole 54.

[0081] The cathode region 82 is a region of the first conductivity type provided on the back side of the semiconductor substrate 10 in the diode portion 80. As an example, the cathode region 82 in this example is of N+ type. The region where the cathode region 82 is provided is indicated by a dashed line in a plan view.

[0082] Figure 1B It is shown Figure 1A FIG. 1 is a diagram showing an example of an a-a' cross section in FIG. The a-a' cross section is an XZ plane passing through the emitter region 12, the base region 14, and the contact region 15 in the transistor portion 70 and the diode portion 80. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section. The emitter electrode 52 is formed on the front surface 21 of the semiconductor substrate 10 and the front surface of the interlayer insulating film 38.

[0083] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doped regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0084] The buffer region 90 is a region of the first conductivity type provided below the drift region 18. As an example, the buffer region 90 of this example is of N type. The doping concentration of the buffer region 90 is higher than the doping concentration of the drift region 18. The buffer region 90 can function as a field stop layer that prevents the depletion layer extending from the back side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0085] As an example, the upper surface of the buffer region 90 is provided at a depth Zf from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The buffer region 90 of this example has a plurality of peaks 91. As an example, the plurality of peaks 91 are formed by multiple proton ion implantations into the semiconductor substrate 10.

[0086] The collector region 22 is a region of the second conductivity type provided on the back side of the semiconductor substrate 10 in the transistor portion 70. As an example, the collector region 22 is of P+ type. The collector region 22 of this example is provided below the buffer region 90.

[0087] The cathode region 82 is a region of the first conductivity type provided on the back side of the semiconductor substrate 10 in the diode portion 80 . As an example, the cathode region 82 is of N+ type. The cathode region 82 in this example is provided below the buffer region 90 .

[0088] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0089] The accumulation region 16 is a region of the first conductivity type disposed above the drift region 18. As an example, the accumulation region 16 of this example is of N type. The accumulation region 16 is disposed in contact with the gate groove portion 40. The accumulation region 16 may or may not be in contact with the dummy groove portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be increased, thereby reducing the on-voltage of the transistor portion 70.

[0090] The base region 14 is a region of the second conductivity type provided above the accumulation region 16. The base region 14 is provided so as to be in contact with the gate trench portion 40. As an example, the base region 14 is of P-type.

[0091] In the first terrace portion 61, the emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided to be in contact with the gate groove portion 40. The emitter region 12 may or may not be in contact with the dummy groove portion 30. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. An example of a dopant of the emitter region 12 is arsenic (As) or phosphorus (P). It should be noted that the emitter region 12 may not be provided in the second terrace portion 62.

[0092] The contact region 15 is provided above the reservoir region 16. The contact region 15 of this example is provided so as to be in contact with the gate trench portion 40. As an example, the contact region 15 is of P+ type.

[0093] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the front side 21. Each groove portion is provided from the front side 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each groove portion also penetrates these regions to reach the drift region 18. The groove portion penetrating the doped region is not limited to being manufactured in the order of forming the groove portion after forming the doped region. The case where the doped region is formed between the groove portions after the groove portions are formed is also included in the case where the groove portion penetrates the doped region.

[0094] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove. The gate conductive portion 44 is formed inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front side 21.

[0095] As an example, the dummy trench 30 and the gate trench 40 are provided to have a depth Zt from the semiconductor substrate front surface 21 to the bottom of each trench in the depth direction of the semiconductor substrate 10. However, the depth of the bottom of each trench may vary due to design.

[0096] The gate conductive portion 44 includes a region that is opposed to the base region 14 adjacent to the first terrace portion 61 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in contact with the gate trench in the base region 14.

[0097] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 is covered by an interlayer insulating film 38 on the front side 21.

[0098] The interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter region 12 to the emitter electrode 52. Other contact holes 49 and contact holes 54 can also be provided by penetrating the interlayer insulating film 38 in the same manner. The emitter electrode 52 is provided above the interlayer insulating film 38. The dummy conductive portion 34 can be controlled by a potential different from that of the gate conductive portion 44. As another example, the dummy conductive portion 34 is connected to the emitter electrode 52 via the contact hole 54 and is set to the emitter potential.

[0099] Figure 1C FIG. 1 shows an example of doping concentration distribution of the buffer region 90 of the semiconductor device 100 of the embodiment. In the graph of this example, the vertical axis represents the doping concentration [ / cm 3 ], the horizontal axis represents the depth [μm] from the back surface 23, and the negative side of the horizontal axis represents a deeper depth position of the semiconductor substrate 10 relative to the positive side of the horizontal axis. The graph of this example is a semi-logarithmic graph that uses a logarithmic scale to represent the scale of the vertical axis. The doping concentration distribution of the graph of this example is for Figure 1B The b-b' section depicts the distribution.

[0100] The doping concentration profile 110 shows the distribution of the doping concentration of the buffer region 90. The buffer region 90 of this example has a plurality of peaks 91, a flat portion 92, and a gently sloping region 93.

[0101] The plurality of peaks 91 are provided on the rear surface 23 side of the semiconductor substrate 10. The plurality of peaks 91 have a peak 91a, a peak 91b, a peak 91c, and a peak 91d in order from the front surface 21 side in the depth direction.

[0102] Peak 91a is an example of the first peak disposed on the side closest to the front surface 21 of the semiconductor substrate 10 among the plurality of peaks 91. For example, the depth position of peak 91a is greater than 25 μm and less than 35 μm. By reducing the amount of change in doping concentration between the plurality of peaks 91 and the flat portion 92, it is possible to suppress oscillation of the voltage value in the case of a short circuit between the collector electrode 24 and the emitter electrode 52. In particular, by reducing the amount of change in doping concentration between peak 91a, which is shallow in depth position of the buffer zone from the front surface of the semiconductor substrate 10, and the flat portion 92, it is easier to suppress oscillation. For example, peak 91a is less than twice the doping concentration of the flat portion 92.

[0103] The peak 91b is an example of a second peak provided at the second depth position from the front surface 21 side of the semiconductor substrate 10 among the plurality of peaks 91. For example, the doping concentration of the peak 91b is twice or less the doping concentration of the flat portion 92.

[0104] The peak 91c is an example of a third peak provided at a third depth position from the front surface 21 side of the semiconductor substrate 10 among the plurality of peaks 91. The doping concentration of the peak 91c may be higher than the doping concentrations of the peaks 91a and 91b.

[0105] The peak 91d is an example of a fourth peak located at the fourth depth from the front surface 21 of the semiconductor substrate 10 among the plurality of peaks 91. The doping concentration of the peak 91d may be higher than the doping concentrations of the peaks 91a, 91b, and 91c.

[0106] The flat portion 92 is provided between the plurality of peaks 91 in the depth direction of the semiconductor substrate 10. The flat portion 92 of this example includes a flat portion 92a and a flat portion 92b. The flat portion 92 is a region having a substantially flat or substantially flat doping concentration distribution.

[0107] As an example, the doping concentration distribution in a predetermined area is "flat", which means that the variation range of the doping concentration distribution in the area is less than 30% of the average value of the concentration at both ends of the area. When the doping concentration varies within this range, the distribution in the area shown in the graph can be considered to be flat. The above ratio can be less than 20% or less than 10%. The variation range of the concentration distribution is the difference between the maximum and minimum values ​​of the doping concentration in the area.

[0108] The flat portion 92a is provided between the peak 91a and the peak 91b. The flat portion 92a is an example of a first flat portion.

[0109] The flat portion 92b is provided between the peak 91b and the peak 91c. The flat portion 92b is an example of a second flat portion. The flat portion 92b has a doping concentration different from that of the flat portion 92a. For example, the doping concentration of the flat portion 92b is within ±10% of the doping concentration of the flat portion 92a. The flat portion 92 may have a doping concentration that is 2.5 times or more of the substrate concentration of the semiconductor substrate 10. In addition, the flat portion 92 may have a doping concentration that is 10 times or less of the substrate concentration of the semiconductor substrate 10, or may have a doping concentration that is 5 times or less of the substrate concentration of the semiconductor substrate 10.

[0110] The gently inclined region 93 is a region whose doping concentration gradient in the depth direction is gentler than that of the peak 91 a. The gently inclined region 93 is provided at a position closer to the front surface 21 of the semiconductor substrate 10 than the peak 91 a.

[0111] The slope α of the gently sloping region 93 can be expressed as a semi-logarithmic slope. The position of one end of the predetermined region is set to x1 [cm], and the position of the other end is set to x2 [cm]. The doping concentration at x1 is set to N1 [ / cm 3 ], set the doping concentration at x2 to N2[ / cm 3 The semi-logarithmic slope α[ / cm] in the predetermined region is defined as α=(log 10 (N2)-log 10 (N1)) / (x2-x1). Here, the numerator of α includes a logarithm and is dimensionless. The slope α of the doping concentration in the gently sloping region 93 is greater than 750 and less than 1500. For example, the thickness of the gently sloping region 93 is greater than 5 μm and less than 10 μm. By setting the thickness of the gently sloping region 93 to be greater than 5 μm, it is easy to reduce the surge voltage.

[0112] As an index of the slope of the flat portion 92, a semi-logarithmic slope may also be used. The position of one end of the flat portion 92 is x3 [cm], and the position of the other end is x4 [cm]. The concentration at x3 is N3 [ / cm 3 ], set the concentration at x4 to N4[ / cm 3 The semi-logarithmic slope η [ / cm] of the flat portion 92 is defined as η = (log 10 (N4)-log 10 (N3)) / (x4-x3). The absolute value of the semi-logarithmic slope η of the approximate linear distribution of the flat portion 92 may be greater than 0 and less than 50, or greater than 0 and less than 30. In addition, the absolute value of the semi-logarithmic slope η of the approximate linear distribution of the flat portion 92 may be greater than 0 and less than 20, or greater than 0 and less than 10.

[0113] For example, the doping concentration of at least one of the plurality of peaks 91 is less than twice the doping concentration of the flat portion 92. In addition, the doping concentration of at least one of the plurality of peaks 91 may be less than 1.5 times the doping concentration of the flat portion 92. As one example, the peaks 91c on both sides contacting with the flat portion 92b and the peak 91b on the front side of the peak 91b may be less than 1.5 times the doping concentration of the flat portion 92. In addition, as another example, the peaks 91b on both sides contacting with the flat portion 92a and at least the peak 91a on the front side of the peak 91a may be less than 1.5 times the doping concentration of the flat portion 92. In addition, the peak 91b on the back side may also be less than 1.5 times the doping concentration of the flat portion 92. Thus, the size of the peak 91 can be suppressed and the doping concentration of the entire buffer region 90 can be ensured.

[0114] Here, if the doping concentration of the peak 91 of the buffer region 90 is increased, short-circuit oscillation is likely to occur. On the other hand, if the doping concentration of the buffer region 90 itself is reduced, punch-through may be likely to occur.

[0115] The semiconductor device 100 of this example suppresses the doping concentration of the peak 91, but increases the doping concentration of the flat portion 92, thereby suppressing the slope of the doping concentration and ensuring the integrated concentration of the dopant in the entire buffer region 90. As a result, the semiconductor device 100 can suppress short-circuit oscillation at a low collector-emitter voltage and can suppress punch-through.

[0116] The integrated concentration of the dopant from the rise of the substrate concentration on the back side to the end of the flat portion 92b on the back side can be 0.8×10 11 cm -2 Above and 5.0×10 11 cm -2 Below, it can also be 1.0×10 11 cm -2 Above and 4.0×10 11 cm -2 Below, it can also be 2.0×10 11 cm -2 Above and 3.0×10 11 cm -2 the following.

[0117] The chemical hydrogen concentration profile 120 indicates the distribution of the chemical hydrogen concentration in the semiconductor device 100. The depth of the peak of the chemical hydrogen concentration profile 120 corresponds to the position in the depth direction of the plurality of peaks 91. That is, the doping concentration profile is formed by ion implantation of protons.

[0118] The substrate concentration distribution 130 indicates the doping concentration (ie, substrate concentration) of the semiconductor substrate 10. The substrate concentration of the semiconductor substrate 10 may be 1×10 12 cm-3 Above, it can also be 1×10 13 cm -3 For example, the substrate concentration of the semiconductor substrate 10 is 7×10 13 cm -3 .

[0119] The oxygen chemical concentration distribution 140 represents the distribution of the oxygen chemical concentration in the semiconductor substrate 10. The oxygen chemical concentration distribution 140 of this example is substantially constant in the depth direction of the semiconductor substrate 10. For example, the oxygen chemical concentration in the buffer region 90 is 1×10 17 cm -3 Above and 6×10 17 cm -3 By setting the oxygen chemical concentration in the buffer zone 90 to 1×10 17 cm -3 Above and 6×10 17 cm -3 Next, the doping concentration of the flat portion 92 can be easily adjusted.

[0120] Unlike the doping concentration distribution, the hydrogen chemical concentration distribution of the flat portion 92 is not flat. The hydrogen chemical concentration distribution of the flat portion 92 has a reduced concentration at positions between adjacent peaks 91 and has a valley. The reason why the doping concentration distribution of the flat portion 92 is flat, unlike the hydrogen chemical concentration distribution, is as follows. If hydrogen ions are injected from the back side in order to form the peak 91, the stopping portion of the hydrogen ions becomes the peak 91, and the area closer to the back side than the stopping portion becomes the passage portion for the hydrogen ions. Lattice defects mainly composed of vacancies are formed in the passage portion. The concentration distribution of the vacancies forming the lattice defects is roughly flat. Through heat treatment, hydrogen terminates the dangling bonds caused by the vacancies. Therefore, VOH defects (hydrogen donors) are also formed roughly flat. In addition, in this example, the oxygen chemical concentration is 1×10 17 cm -3 Above and 6×10 17 cm -3 Therefore, the concentration of VOH defects (hydrogen donors) in the flat portion is distributed at a higher concentration than that in the semiconductor substrate.

[0121] It should be noted that the semiconductor substrate 10 may contain carbon. For example, the carbon chemical concentration in the buffer region 90 is 1×10 13 cm -3 Above and 3×10 16 cm -3 In addition, the carbon chemical concentration in the buffer zone 90 may be 1×10 13 cm -3 Above and 1×10 16 cm -3 the following.

[0122] The flat portion 92 may be disposed at a position deeper than the back surface 23, or may be disposed at a position closer to the back surface than the peak of the hydrogen chemical concentration. Thus, the integrated concentration of the dopant in the entire buffer region 90 can be increased. In addition, as a structure, the flat portion 92 has a VOH defect. In addition, the flat portion 92 may have a composite defect including two or more of the following lattice defects, including vacancies (V, VV, etc.), C, O, and H.

[0123] Furthermore, the total thickness of the flat portion 92 can be set thicker than the thickness of the semiconductor substrate 10 below the flat portion 92. Thus, the ratio of the region with a constant doping concentration increases on the front surface 21 side of the buffer region 90, so that the surge voltage is easily reduced, and the integrated concentration of the dopant is easily increased while suppressing the peak concentration.

[0124] Figure 2 An example of doping concentration distribution of the embodiment and the comparative example is shown. The vertical axis represents the doping concentration [ / cm 3 ], and the horizontal axis represents the depth [μm] from the back surface 23. The graph of this example shows the doping concentration distribution 110 of the embodiment and the doping concentration distribution 510 of the comparative example. In this example, the cases where the buffer zone 90 is provided on different substrates under the same manufacturing conditions are compared.

[0125] Doping concentration distribution 110 and Figure 1C The doping concentration distribution 110 is the same as that of the semiconductor substrate 10. The doping concentration distribution 110 shows the concentration distribution of the doping concentration when an MCZ substrate is used as the semiconductor substrate 10.

[0126] Doping concentration profile 510 shows a doping concentration distribution when an FZ substrate is used as the semiconductor substrate. The peak of doping concentration profile 510 is also formed by ion implantation of protons into the buffer region 90 of the semiconductor substrate 10 , similarly to the peak 91 of doping concentration profile 110 .

[0127] The MCZ substrate is a semiconductor substrate 10 grown by crystal growth in a quartz (SiO2) crucible using a carbon heater. Therefore, compared with the FZ substrate, the oxygen chemical concentration and the carbon chemical concentration are higher overall. Therefore, the doping concentration profile 110 is likely to provide a doping concentration that is higher than the doping concentration profile 510 as a whole.

[0128] Since the overall doping concentration in the doping concentration distribution 510 is low, the depletion layer easily reaches the collector electrode 24 during switching. As a result, a penetration current easily occurs.

[0129] The doping concentration profile 110 and the doping concentration profile 510 have different types of semiconductor substrates, but the other conditions such as the dopant implantation conditions are the same. The doping concentration profile 110 of this example has a lower peak than the doping concentration profile 510 .

[0130] Figure 3 Another example of doping concentration distribution of the embodiment and the comparative example is shown. The vertical axis represents the doping concentration [ / cm 3 ], and the horizontal axis represents the depth [μm] from the rear surface 23. In this example, the condition is adjusted so that the buffer area 90 has the same integrated concentration for different substrates.

[0131] The graph of this example shows the doping concentration profile 110 of the embodiment and the doping concentration profile 550 of the comparative example. The doping concentration profile 550 of the comparative example is adjusted so that the integrated concentration of the dopant, i.e., the total dose of the dopant, is the same as that of the doping concentration profile 110 of the embodiment. The comparative example uses an FZ substrate as a semiconductor substrate. The oxygen chemical concentration of the semiconductor substrate in the comparative example is 1×10 16 cm -3 .

[0132] Thus, in the doping concentration profile 110 of the embodiment, the doping concentration of the flat portion 92 is higher than that of the doping concentration profile 550 of the comparative example. Therefore, in the doping concentration profile 110, the doping concentration of the peak 91 required to achieve the same integrated concentration can be reduced.

[0133] In particular, in the doping concentration distribution 110, the first peak 91a and the second peak 91b show peaks lower than the doping concentration distribution of the comparative example. Although the doping concentration distribution 110 shows slightly higher peaks than the doping concentration distribution 550 in the third peak 91c and the fourth peak 91d, this is because the integrated concentrations of the dopants are adjusted to be the same.

[0134] The doping concentration distribution 110 has a low peak concentration as a whole, and in particular, provides a low peak concentration at a peak at a shallow depth position of the semiconductor substrate 10, such as the concentrations of the first peak 91a and the second peak 91b. As a result, the doping concentration distribution becomes flat until the slope providing the third peak 91c is reached, and short-circuit oscillation can be suppressed.

[0135] When the collector and emitter of the semiconductor device 100 are short-circuited, the gate-emitter voltage oscillates in the early stage of the short circuit. This oscillation may damage the semiconductor device 100.

[0136] Figure 4 FIG. 1 shows a modified example of the doping concentration distribution of the buffer region 90 of the semiconductor device 100 of the embodiment. In the graph of this example, the vertical axis represents the doping concentration [ / cm 3], the horizontal axis represents the depth [μm] from the back surface 23, and the negative side of the horizontal axis represents a deeper depth position of the semiconductor substrate 10 relative to the positive side of the horizontal axis. The graph of this example is a semi-logarithmic graph that uses a logarithmic scale to represent the scale of the vertical axis. The doping concentration distribution of the graph of this example is for Figure 1B In this example, the distribution of the b-b' section is particularly modified. Figure 1C The differences are explained.

[0137] The semiconductor device 100 of this example has a plurality of peaks of doping concentrations with no flat region between the peaks at a position closer to the front surface 21 than the flat portion 92a. Similar to the flat portion 92a, the flat region may be a region where the doping concentration distribution is substantially flat. Peak 91a, peak 91e, peak 91f, and peak 91g are examples of a plurality of peaks of doping concentrations disposed at a position closer to the front surface 21 than the flat portion 92a. Although the semiconductor device 100 of this example has four peaks at a position closer to the front surface 21 than the flat portion 92a, the number of peaks closer to the front surface 21 than the flat portion 92a may be 2, 3, or 5 or more.

[0138] Multiple peaks of doping concentrations without flat areas between the peaks may be provided with valleys respectively between the peaks. There is no region such as the flat portion 92 between the peaks of multiple doping concentrations without flat areas. For example, valleys are provided between peaks 91a and 91e, between peaks 91e and 91f, and between peaks 91f and 91g. In each valley, the inclination of the doping concentration distribution may continuously change from a negative value to a positive value in the direction from the back 23 toward the front 21. On the other hand, in the flat portion 92, the inclination of the doping concentration distribution may be substantially continuous at a value of 0 in the direction from the back 23 toward the front 21. It should be noted that for the measurement points based on the CV method or the SR method, the inclination of the doping concentration distribution may be the average value of multiple measurement points within a predetermined measurement range, and the average value may be a value calculated by a known fitting.

[0139] In addition, the positions in the depth direction of the peaks of the plurality of doping concentrations having no flat region between the peaks correspond to the positions in the depth direction of the peaks of the hydrogen chemical concentration. With respect to the plurality of doping concentrations having no flat region between the peaks and the hydrogen chemical concentrations corresponding to the plurality of doping concentrations, C Hv / C Hp Can be compared to N v / N p Small. C Hv / C Hp is the valley of hydrogen chemical concentration (e.g., C Hv ) relative to the hydrogen chemical concentration of the peak (e.g., C Hp), the peak is a preset peak, and the valley is a valley adjacent to the peak. v / N p is the valley of doping concentration (e.g., N v ) relative to the peak doping concentration (e.g., N p ), the peak is a preset peak, and the valley is a valley adjacent to the peak. v / N p The concentration distribution may be set so that the plurality of peaks on the front surface 21 side relative to the flat portion 92a gradually descend to the substrate concentration distribution 130. Hv / C Hp Can be N v / N p Less than 0.8 times of N v / N p Less than 0.5 times of N v / N p Less than 0.2 times of N v / N p Less than 0.1 times of N v / N p Less than 0.01 times of C Hv / C Hp Can be N v / N p More than 0.001 times, can be N v / N p More than 0.01 times, can be N v / N p More than 0.1 times.

[0140] The semiconductor device 100 has a plurality of peaks with no flat region between the peaks at a position closer to the front surface 21 than the flat portion 92a, so that the distribution of the doping concentration can be made gentle, and the change in the electric field strength when the depletion layer reaches the buffer region 90 can be made gentle. Thus, a sharp change in the voltage waveform can be suppressed.

[0141] Figure 5 The characteristics of the semiconductor device of the comparative example when short-circuited are shown. The vertical axis represents the current and voltage in arbitrary units, and the horizontal axis represents the time t [μs]. V' GE The gate-emitter voltage of the semiconductor device of the comparative example is shown in FIG. CE I' represents the collector-emitter voltage of the semiconductor device of the comparative example. CE : represents the collector-emitter current of the semiconductor device of the comparative example. In the semiconductor device of the comparative example, at the time point when the collector-emitter voltage is low at the initial stage of the short circuit, V' GE The waveform produces a large oscillation site OSc.

[0142] Figure 6 The characteristics of the semiconductor device 100 of the embodiment when short-circuited are shown. The vertical axis represents the current and voltage in arbitrary units, and the horizontal axis represents an arbitrary time t [μs]. GE V represents the gate-emitter voltage of the semiconductor device 100. CE I represents the collector-emitter voltage of the semiconductor device 100. CE represents the collector-emitter current of the semiconductor device 100. In the semiconductor device 100, at the time point when the collector-emitter voltage is low in the initial stage of short circuit, V GE The waveform does not produce a large oscillation portion OSc. Therefore, the semiconductor device 100 of this example can suppress the V GE oscillation.

[0143] Figure 7 The relationship between the backside boron ion implantation concentration and the latch-up withstand breakdown current is shown. For the FZ substrate, a peak of doping concentration in the buffer zone is formed by implanting boron (B) ions from the backside of the semiconductor substrate. As the backside boron ion implantation concentration decreases, the depletion layer becomes easier to stretch, and the latch-up withstand capability decreases.

[0144] Figure 8 The current before the breakdown of the latch tolerance during short circuit in the embodiment and the comparative example is shown. In the comparative example, the amount of hydrogen ion implantation on the back surface 23 side closer to the peak 91a is reduced to reduce the oscillation during short circuit, and the doping profile concentration is reduced. As a result, since the doping integrated concentration of the flat portion is reduced, the depletion layer is easily extended, and thus the current [A] just before the breakdown of the latch tolerance is also reduced, and the semiconductor device of the comparative example becomes easy to latch.

[0145] Compared with the comparative example, Figure 8 In the semiconductor device 100 of the embodiment shown, the current before the breakdown of the latch-up tolerance is improved. In the semiconductor device 100 of this example, by reducing the doping concentration of the peak 91 and increasing the integrated concentration of the flat portion, it is possible to suppress oscillation during short circuits, take into account high-speed switching caused by the reduction in the back boron ion implantation concentration, and provide sufficient latch-up tolerance.

[0146] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0147] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order as long as "earlier than" or "in advance" is not specifically stated, and the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is explained using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: Semiconductor substrates; a plurality of peaks of doping concentration disposed in a buffer region of the semiconductor substrate; and a flat portion disposed between the plurality of peaks in the depth direction of the semiconductor substrate and having a doping concentration that is 2.5 times or more of a substrate concentration of the semiconductor substrate, At least one of the plurality of peaks is a first peak disposed on a front side of the flat portion, The doping concentration of the first peak is less than or equal to twice the doping concentration of the flat portion.

2. The semiconductor device according to claim 1, wherein: The doping concentration of the flat portion is 10 times or less than the substrate concentration of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein: The depth position of the first peak is 25 μm or more and 35 μm or less.

4. The semiconductor device according to claim 2 or 3, characterized in that The semiconductor device includes a gently inclined region, the gently inclined region being provided at a position closer to the front surface side of the semiconductor substrate than the first peak, and having a doping concentration gradient in a depth direction that is gentler than the first peak. The slope α of the doping concentration in the gently sloping region is greater than or equal to 750 and less than or equal to 1500, The unit of the slope α is [ / cm].

5. The semiconductor device according to claim 4, wherein: The gently sloping region has a thickness of 5 μm or more and 10 μm or less.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that The plurality of peaks include a second peak that is located at a second depth position from the front surface side of the semiconductor substrate and has a doping concentration that is twice or less than a doping concentration of the flat portion.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that The doping concentration of at least one of the plurality of peaks is 1.5 times or less than the doping concentration of the flat portion.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that The positions of the plurality of peaks in the depth direction correspond to the depths of the peaks of the hydrogen chemical concentration.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that The flat portion includes a first flat portion and a second flat portion having a doping concentration different from that of the first flat portion.

10. The semiconductor device according to claim 9, wherein: The doping concentration of the second flat portion is within ±10% of the doping concentration of the first flat portion.

11. The semiconductor device according to claim 9, wherein: The plurality of peaks include a first peak, a second peak, a third peak, and a fourth peak in order from the front side along the depth direction, The first flat portion is disposed between the first peak and the second peak.

12. The semiconductor device according to claim 10, wherein: The plurality of peaks include a first peak, a second peak, a third peak, and a fourth peak in order from the front side along the depth direction, The first flat portion is disposed between the first peak and the second peak.

13. The semiconductor device according to claim 11, wherein: The second flat portion is disposed between the third peak and the fourth peak.

14. The semiconductor device according to claim 12, wherein: The second flat portion is disposed between the third peak and the fourth peak.

15. The semiconductor device according to claim 9, wherein: The integrated concentration of the dopant from the rising position of the substrate concentration on the back side to the end of the second flat portion on the back side is 0.8×10 11 cm -2 Above and 5.0×10 11 cm -2 the following.

16. The semiconductor device according to any one of claims 1 to 3, characterized in that The plurality of peaks are arranged in a buffer zone, The oxygen chemical concentration in the buffer was 1 × 10 17 cm -3 Above and 6×10 17 cm -3 the following.

17. The semiconductor device according to claim 1, wherein: The semiconductor device has a plurality of peaks of doping concentration with no flat region between the peaks at positions closer to the front surface than the flat portion.

18. The semiconductor device according to claim 17, wherein: The positions in the depth direction of the peaks of the plurality of doping concentrations without the flat region correspond to the positions in the depth direction of the peaks of the hydrogen chemical concentration, Regarding the multiple doping concentrations that do not have the flat area, and the hydrogen chemical concentrations corresponding to the multiple doping concentrations, the ratio of the hydrogen chemical concentration of the valley adjacent to a predetermined peak of the hydrogen chemical concentration to the peak is smaller than the ratio of the doping concentration of the valley adjacent to a predetermined peak of the doping concentration to the peak.

19. The semiconductor device according to any one of claims 1 to 3, characterized in that The flat portion is provided on the rear surface side relative to the peak of the hydrogen doping concentration distribution.

20. The semiconductor device according to any one of claims 1 to 3, characterized in that The flat portion has a composite defect including two or more of lattice defects, and the lattice defects include vacancies, C, O, and H.

21. The semiconductor device according to any one of claims 1 to 3, characterized in that The total thickness of the flat portion is thicker than the thickness of the semiconductor substrate below the flat portion.

22. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor substrate is a MCZ substrate.

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