Parasitic capacitance test circuit and test method

Abstract

The present invention provides a parasitic capacitance test circuit and test method, wherein a reference branch and a test branch are divided into several functional areas, the gate of the transistor of the reference branch is electrically connected to the reference drive branch, a reference contact hole is provided on the functional area, and the reference contact hole outputs a reference current to the reference reading branch; a reference gate pass size parallel to a first direction is provided between the reference contact hole and the gate; the gate of the transistor of the test branch is electrically connected to the test drive branch, a test contact hole is provided on the functional area, and the test contact hole outputs a test current to the test reading branch; a test gate pass size parallel to the first direction is provided between the test contact hole and the gate, and the test gate pass size is greater than 0 and less than or equal to the reference gate pass size. By separately extracting the first capacitance test value, the second capacitance test value and the third capacitance test value of the transistor, the extraction accuracy of the parasitic capacitance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a parasitic capacitance testing circuit and testing method. Background Art

[0002] With the development of advanced CMOS technology, the size of transistors is shrinking to obtain high-speed, low-power and high-density integrated circuits. In circuit simulation, the influence of parasitic capacitance is becoming more and more important. Figure 1 As shown, Figure 1 This is a schematic diagram of the distribution of MOSFET parasitic capacitance. Figure 1 The device capacitance of the transistor includes the gate-to-body capacitance (C gg ), the gate capacitance to the shallowly doped overlap region (C ov ), junction capacitance (C js ), gate edge to source-drain capacitance (C f ) and the capacitance of the gate to the contact hole (Cctg). gg It can be directly measured by the traditional MOSFET device CV test circuit, C js It can be measured and extracted through large source and drain area structures. However, other parasitic capacitances such as C ov , Cctg and C f It cannot be measured, especially when the distance between the gate and the contact hole becomes very small due to process miniaturization, the capacitance contribution of Cctg becomes very large, C f cannot be ignored. Therefore, Cctg and C f It needs to be separated out and written into the parasitic capacitance extraction tool.

[0003] The foundry model generally puts Cctg into C f However, it is not possible to simply verify these two parasitic capacitance models or parasitic capacitance extraction through general test circuits and CV measurement methods. The existing technology uses 3D analysis simulation tools to calculate, but it is not possible to extract and verify Cctg and C through wafer data. f Capacitance value. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned defects in the prior art. In a first aspect of the present invention, a parasitic capacitance test circuit is provided.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A parasitic capacitance test circuit comprises a reference circuit and a test circuit, wherein the reference circuit comprises a coupled reference drive branch, a reference read branch and a reference branch, and the test circuit comprises a coupled test drive branch, a test read branch and a plurality of cascaded test branches, wherein the reference drive branch and the test drive branch are respectively connected to a drive current; wherein the reference branch and the test branch are respectively provided with a plurality of functional areas, and transistors are provided on the functional areas; the gate of the transistor of the reference branch is electrically connected to the reference drive branch, and a reference contact hole is provided on the functional area of ​​the reference branch, and the reference contact hole outputs a reference current to the reference read branch; a reference gate pass size parallel to a first direction is provided between the reference contact hole and the gate; the gate of the transistor of the test branch is electrically connected to the test drive branch, and a test contact hole is provided on the functional area of ​​the test branch, and the test contact hole outputs a test current of the corresponding test branch to the test read branch; a test gate pass size parallel to the first direction is provided between the test contact hole and the gate, and the test gate pass size is greater than 0 and less than or equal to the reference gate pass size

[0007] Preferably, the number of the reference contact holes and the test contact holes is the same and greater than or equal to 2; the reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area, and the test contact holes of each test branch are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area.

[0008] Preferably, the functional area includes a diffusion area, the reference branch includes a diffusion reference branch, the test branch includes a plurality of cascaded diffusion test branches, the reference contact hole includes a diffusion reference contact hole, the test contact hole includes a diffusion test contact hole, the diffusion reference contact hole outputs a diffusion reference current to the reference read branch, the diffusion test contact hole outputs the diffusion test current of the corresponding diffusion test branch to the test read branch, a diffusion reference gate pass size is provided between the diffusion reference contact hole and the corresponding gate, a diffusion test gate pass size is provided between the diffusion test contact hole and the corresponding gate, and the diffusion reference gate pass size is equal to the diffusion test gate pass size.

[0009] Preferably, the diffusion region has a diffusion size parallel to the first direction, the diffusion region of the diffusion reference branch has a minimum diffusion region size, a first reference capacitor is formed between the diffusion reference contact hole and the corresponding gate, a first test capacitor is formed between the diffusion test contact hole and the corresponding gate, and the diffusion size of the diffusion region of each diffusion test branch is greater than or equal to the minimum diffusion region size.

[0010] Preferably, the first reference capacitor has a first reference capacitance value, and the first test capacitor has a first test capacitance value; and the diffusion size of the diffusion region of each diffusion test branch gradually increases.

[0011] Preferably, the functional area also includes an isolation area, the test branch also includes a plurality of cascaded isolation test branches, the test contact hole also includes an isolation test contact hole, and the isolation test contact hole outputs the isolation test current of the corresponding isolation test branch to the test reading branch; a second test capacitor is formed between the isolation test contact hole and the corresponding gate, the second test capacitor has a second test capacitance value, and the test gate pass size between each of the isolation test branches gradually increases.

[0012] Preferably, the functional area also includes an active area, the reference branch also includes an active reference branch, the test branch also includes a number of cascaded active test branches, the reference contact hole also includes an active reference contact hole, the test contact hole also includes an active test contact hole, the active reference contact hole outputs an active reference current to the reference read branch, and the active test contact hole outputs an active test current of the corresponding active test branch to the test read branch; a third reference capacitor is formed between the active reference contact hole and the corresponding gate, a third test capacitor is formed between the active test contact hole and the corresponding gate, the third reference capacitor has a third reference capacitance value, and the third test capacitor has a third test capacitance value; the active gate pass reference size of the active reference branch is the maximum gate pass size, and the test gate pass size between each of the active test branches gradually increases to the maximum gate pass size.

[0013] Preferably, the numbers of the isolation reference contact holes, the isolation test contact holes, the active reference contact holes and the active reference contact holes are the same, and the numbers of the diffusion reference contact holes and the diffusion test contact holes are both 2.

[0014] Preferably, the reference circuit and the test circuit are provided with shielding rings at their peripheries, the shielding rings have openings, the reference drive branch, the reference read branch, the test drive branch, and the test read branch are respectively led out through the openings and are electrically connected to the CBCM circuit.

[0015] A second aspect of the present invention provides a test method for a parasitic capacitance test circuit, wherein a first capacitance difference curve is obtained based on the difference between the first test capacitance value and the first reference capacitance value and the corresponding diffusion size, and the first capacitance difference curve is fitted to obtain the first capacitance saturation value of the transistor; an initial third capacitance difference curve is obtained based on the difference between the third test capacitance value and the third reference capacitance value and the corresponding test gate pass size; a third capacitance difference curve is obtained by fitting the first capacitance saturation value and the initial third capacitance difference curve, and a second capacitance curve is obtained based on the second test capacitance value and the corresponding test gate pass size; and a third capacitance curve is obtained by fitting the second capacitance curve and the third capacitance difference curve.

[0016] It can be seen from the above technical solution that the present invention provides a parasitic capacitance testing method, which separates and extracts the first capacitance test value, the second capacitance test value and the third capacitance test value of the transistor, thereby improving the accuracy of parasitic capacitance extraction, and writes the separated and extracted capacitance test values ​​into a parasitic parameter extraction tool to ensure the reliability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is a schematic diagram of the distribution of MOSFET parasitic capacitance;

[0019] Figure 2 A schematic diagram of a layout of a parasitic capacitance test circuit according to an embodiment of the present invention;

[0020] Figure 3 A schematic diagram showing a layout comparison of a diffused reference branch and a diffused test branch of a parasitic capacitance test circuit according to an embodiment of the present invention is shown;

[0021] Figure 4 A schematic diagram of a first capacitance difference curve according to an embodiment of the present invention is shown;

[0022] Figure 5 A schematic structural diagram of an isolated test branch of a parasitic capacitance test circuit according to an embodiment of the present invention is shown;

[0023] Figure 6 A plan view of an isolated test branch of a parasitic capacitance test circuit according to an embodiment of the present invention is shown;

[0024] Figure 7A schematic diagram showing a layout comparison of an active reference branch and an active test branch of a parasitic capacitance test circuit according to an embodiment of the present invention is shown;

[0025] Figure 8 A schematic diagram of an initial third capacitance difference curve according to an embodiment of the present invention is shown;

[0026] Fig. 9 A schematic diagram of a third capacitance difference curve according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0027] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings of the specification. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0028] It should be noted that the specific embodiments provided herein are provided as examples to teach a broader inventive concept, and those skilled in the art can easily apply the teachings of the present invention to other methods and systems. In addition, it is understood that the methods and systems discussed in the present invention include some common structures and / or processes. Because these structures and processes are well known in the art, they will only be discussed in general details. For convenience and example, the reference numerals in the drawings may be repeated, and these repetitions do not represent any necessary combination of the features or steps in the drawings.

[0029] The present invention provides a test method for a parasitic capacitance test circuit. The present invention applies a CBCM (Charge Based Capacitance Measurement) test method to a front-end test structure of a MOSFET transistor. A plurality of transistors, an isolation region, a diffusion region, and an active region are defined on a substrate; in an exemplary embodiment, the transistors include an N-type MOSFET and a P-type MOSFET. The transistors are arranged on the isolation region, the diffusion region, and the active region, and different functional regions are formed according to different test requirements.

[0030] Specifically, the parasitic capacitance test circuit includes a reference circuit and a test circuit, the reference circuit includes a coupled reference drive branch, a reference read branch and a reference branch, the test circuit includes a coupled test drive branch, a test read branch and several cascaded test branches, and the reference drive branch and the test drive branch are respectively connected to the drive current.

[0031] In this embodiment, in order to shield the electromagnetic field influence generated by the detection pad near the reference circuit and the test circuit, shielding rings are provided around the reference circuit and the test circuit. At the same time, the reference drive branch and the test drive branch are separate signal drive branches, and the design of non-overlapping signal circuits can reduce the short-circuit current during the inverter transmission process. The transistor includes a thick oxide layer transistor to reduce gate leakage. At the same time, only a transmission gate switch is used for one branch to eliminate CIE (charge injection error).

[0032] like Figure 2 As shown, Figure 2 The present invention is a schematic diagram of a layout of a parasitic capacitance test circuit according to an embodiment of the present invention, wherein the reference circuit and the test circuit are symmetrically arranged, thereby reducing the test error caused by local mismatch of the circuit layout. At the same time, a shielding ring is also arranged around the reference circuit and the test circuit, and a shielding wall is shared between the reference circuit and the test circuit, thereby shielding the electromagnetic field influence generated by the detection pad near the circuit layout. The shielding ring shields the static electricity around the reference circuit and the test circuit, so that the corresponding reference branch and test branch in the reference circuit and the test circuit are at a similar potential, eliminating the risk of transistor breakdown due to high electric field caused by high potential difference, improving the anti-static damage capability, and thus improving the production yield.

[0033] The shielding ring has an opening, and the reference driving branch, the reference reading branch, the test driving branch, and the test reading branch are respectively led out through the corresponding openings of the shielding ring and are electrically connected to the CBCM circuit.

[0034] The reference branch and the test branch are divided into several functional areas, and transistors are arranged on the functional areas. The gate of the transistor in the reference branch is electrically connected to the reference drive branch through the reference input terminal, and the gate of the transistor in the test branch is electrically connected to the test drive branch through the test input terminal. The CBCM circuit provides an AC signal to the reference drive branch and the test drive branch respectively, the gate of the transistor is electrically connected to the AC signal, the source and the drain are grounded, and the AC signal charges the transistor.

[0035] A reference contact hole is provided on the functional area of ​​the reference branch, and the reference contact hole outputs a reference current to the reference reading branch; a test contact hole is provided on the functional area of ​​the test branch, and the test contact hole outputs a test current to the test reading branch. The number of the reference contact holes and the test contact holes is the same, and is greater than or equal to 2; the reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area, and the test contact holes of each test branch are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area.

[0036] According to I=C*V*f, I is the reference current value of the reference current or the test current value of the test current, V is the voltage value of the AC signal, and f is the frequency value of the AC signal, the coupling capacitance value of the transistor of the corresponding reference branch or the test branch is obtained, the coupling capacitance value is the sum of the first capacitance value, the second capacitance value and the third capacitance value, the first capacitance value is the capacitance value between the gate edge of the transistor of the reference branch or the test branch and the corresponding source or drain, the second capacitance value is the capacitance value between the gate of the transistor of the reference branch or the test branch and the corresponding reference contact hole or test contact hole, and the third capacitance value is the capacitance value between the gate of the transistor of the reference branch or the test branch and the corresponding functional area.

[0037] Specifically, there is a reference gate pass size parallel to the first direction between the reference contact hole and the gate; there is a test gate pass size parallel to the first direction between the test contact hole and the gate, and the test gate pass size is greater than 0 and less than or equal to the reference gate pass size. Different test gate pass sizes are set between the test branches, and as the test gate pass size increases, the second capacitance value and the third capacitance value decrease, and the first capacitance value increases. When the test gate pass size increases to a sufficiently large size, the second capacitance value and the third capacitance value both decrease to approach zero and are almost negligible; the first capacitance value correspondingly increases to a first capacitance saturation value, and the difference between the coupling capacitance value of the test branch and the coupling capacitance value of the reference branch is equal to the sum of the first capacitance value of the test branch and the corresponding second capacitance value minus the first capacitance saturation value.

[0038] In this embodiment, the reference branch and the test branch are divided into several functional areas. When the functional area is a diffusion area, the reference branch includes a diffusion reference branch, the test branch includes several cascaded diffusion test branches, the reference contact hole includes a diffusion reference contact hole, the test contact hole includes a diffusion test contact hole, the diffusion reference contact hole outputs the diffusion reference current of the corresponding diffusion test branch to the reference reading branch, the diffusion test contact hole outputs the diffusion test current to the test reading branch, the diffusion reference contact hole and the corresponding gate have a diffusion reference gate pass size, the diffusion test contact hole and the corresponding gate have a diffusion test gate pass size, and the diffusion reference gate pass size is equal to the diffusion test gate pass size. The diffusion area has a diffusion size parallel to the first direction, the diffusion area of ​​the diffusion reference branch has a minimum diffusion area size, a first reference capacitor is formed between the diffusion reference contact hole and the corresponding gate, a first test capacitor is formed between the diffusion test contact hole and the corresponding gate, and the diffusion size of the diffusion area of ​​each diffusion test branch is greater than or equal to the minimum diffusion area size.

[0039] like Figure 3 As shown, Figure 3 FIG. 4 is a schematic diagram showing a layout comparison of a diffused reference branch and a diffused test branch of a parasitic capacitance test circuit according to an embodiment of the present invention. Figure 3 The left figure in the middle is a schematic diagram of the diffusion test branch layout, and the right figure is a schematic diagram of the diffusion reference branch layout. In this embodiment, the number of the diffusion reference contact holes and the diffusion test contact holes are both 2, and the diffusion reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area; the diffusion test contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area.

[0040] Specifically, two diffusion reference contact holes located at the upper and lower edges of the diffusion region, and two diffusion test contact holes located at the upper and lower edges of the diffusion region, are respectively used to electrically connect corresponding diffusion regions and output diffusion reference current and diffusion test current respectively.

[0041] The test branch includes several cascaded diffusion test branches, and the diffusion areas of different diffusion test branches have different diffusion sizes SA. The first capacitance difference curve is obtained according to the difference between the first test capacitance value and the first reference capacitance value and the corresponding diffusion size SA. The first capacitance difference curve is fitted to obtain the first capacitance saturation value of the transistor.

[0042] like Figure 4 As shown, Figure 4FIG. 2 is a schematic diagram of a first capacitance difference curve of an embodiment of the present invention. In this embodiment, the minimum diffusion region size is 0.075 μm, and the first reference capacitor has a first reference capacitance value C fref , the first reference capacitance value C fref is the capacitance value between the gate edge and the corresponding source or drain of the transistor of the reference branch, and the first test capacitor has a first test capacitance value C fx , the first test capacitance value C fx is the capacitance value between the gate edge and the corresponding source or drain of the transistor of the test branch. The first reference capacitance value C fref is a fixed value, according to the first test capacitance value C fx With the first reference capacitance value C fref The difference between the two and the corresponding diffusion size x obtains the first capacitance difference (C fx -C fref ) curve, such as Figure 4 The lower curve in the figure is the first capacitance difference curve. The diffusion size is 0, and there is a negative intercept between the first capacitance difference curve and the vertical axis. As the diffusion size of the diffusion area of ​​the diffusion test branch gradually increases, the corresponding diffusion test current gradually increases, and the first test capacitance value C fx The first capacitance difference curve is fitted, and the first capacitance difference curve is along Figure 4 Push the middle vertical axis up until the intercept is at the origin, such as Figure 4 As shown in the upper curve in FIG. 1 , the saturation value of the upper curve is the first capacitance saturation value C of the transistor. f0 , the first capacitor saturation value C f0 is the saturation capacitance between the gate edge of the transistor and the corresponding source or drain.

[0043] In this embodiment, the functional area also includes an isolation area, the reference branch also includes an isolated reference branch, the test branch also includes a number of cascaded isolated test branches, the reference contact hole also includes an isolated reference contact hole, the test contact hole also includes an isolated test contact hole, the isolated reference contact hole outputs an isolated reference current to the reference read branch, and each of the isolated test contact holes outputs the isolated test current of the corresponding isolated test branch to the test read branch.

[0044] Please refer to Figure 5 and Figure 6 , Figure 5 FIG. 4 is a schematic diagram showing a structure of an isolated test branch of a parasitic capacitance test circuit according to an embodiment of the present invention. Figure 6The plan layout of an isolation test branch of a parasitic capacitance test circuit according to an embodiment of the present invention is shown. In this embodiment, the number of the isolation reference contact holes and the number of the isolation test contact holes are both 4, and the isolation reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding isolation region; the isolation test contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding isolation region.

[0045] A second reference capacitor is formed between the isolation reference contact hole and the corresponding gate, a second test capacitor is formed between the isolation test contact hole and the corresponding gate, the second reference capacitor has a second reference capacitance value, and the second test capacitor has a second test capacitance value C gctx The second reference capacitance value is the capacitance value between the gate of the transistor of the reference branch and the corresponding reference contact hole, and the second test capacitance value C gctx is the capacitance value between the gate of the transistor of the test branch and the corresponding test contact hole. The test gate pass size of each test branch gradually increases, the corresponding isolation test current gradually decreases, and the second test capacitance value C gctx According to the second test capacitance value C gctx A second capacitance curve is obtained with the corresponding test gate pass size.

[0046] In this embodiment, the functional area also includes an active area, the reference branch also includes an active reference branch, the test branch also includes a number of cascaded active test branches, the reference contact hole also includes an active reference contact hole, the test contact hole also includes an active test contact hole, the active reference contact hole outputs an active reference current to the reference read branch, and each active test contact hole outputs the active test current of the corresponding active test branch to the test read branch.

[0047] like Figure 7 As shown, Figure 7 FIG. 4 is a schematic diagram showing a layout comparison of an active reference branch and an active test branch of a parasitic capacitance test circuit according to an embodiment of the present invention. Figure 7The left figure in the middle is a schematic diagram of the active test branch layout, and the right figure is a schematic diagram of the active reference branch layout. The number of the isolated reference contact holes, the isolated test contact holes, the active reference contact holes and the active reference contact holes is the same. Specifically, the number of the active reference contact holes matches the length of the active area along the first direction, so that the active area is covered by a plurality of the active reference contact holes along the first direction, and the arrangement of the active test contact holes, the isolated reference contact holes and the isolated test contact holes is the same as that of the active reference contact holes. In this embodiment, the number of the active reference contact holes and the active test contact holes are both 4, and the active reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding active area; the active test contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding active area.

[0048] A third reference capacitor is formed between the active reference contact hole and the corresponding gate, and a third test capacitor is formed between the active test contact hole and the corresponding gate. The third reference capacitor has a third reference capacitance value C ref , the third test capacitor has a third test capacitance value C x , where C ref =C fx0 +C ov +C gct0 , C x =C fx +C ov +C gctx In this embodiment, the active gate reference size of the active reference branch is the maximum gate size, C gct0 Considered as zero, C fx0 Equal to C f0 , C ov is the overlap capacitance value between the gate and the corresponding source or drain of the transistor of the active reference branch or the active test branch. Therefore, the test gate pass size of each active test branch is gradually increased to the maximum gate pass size, and the corresponding active test current is gradually reduced. The third test capacitance value C x Gradually decrease to the third reference capacitance value C ref .

[0049] According to the third test capacitance value C x With the third reference capacitance value C ref Difference C x -C ref =C fx +C gctx -C f0 An initial third capacitance difference curve is obtained with the corresponding test gate pass size.

[0050] like Figure 8 As shown, Figure 8 FIG. 2 is a schematic diagram of an initial third capacitance difference curve of an embodiment of the present invention. As the test gate size of the active test branch gradually increases, the third test capacitance value C x With the third reference capacitance value C ref The difference gradually approaches zero until the test gate size between the active test branches gradually increases to the maximum gate size, C x =C ref .

[0051] Then, the first capacitance saturation value and the initial third capacitance difference curve are fitted to obtain a third capacitance difference curve.

[0052] like Fig. 9 As shown, Fig. 9 The third capacitance difference curve schematic diagram of the embodiment of the present invention is shown. f0 The initial third capacitance difference curve is fitted, that is, the initial third capacitance difference curve is raised along the vertical axis C f0 , a third capacitance difference curve is obtained by fitting, and the third capacitance difference is C fx +C gctx .

[0053] Finally, the second capacitance curve and the third capacitance difference curve are fitted to obtain a third capacitance curve. Specifically, the third capacitance difference C of the third capacitance curve is fx +C gctx Deduct the C corresponding to the second capacitance curve gctx Get C fx The second capacitance curve and the third capacitance curve are normalized and written into the parasitic extraction tool, which can improve the accuracy of parasitic parameter extraction.

[0054] By adopting the testing method of the parasitic capacitance testing circuit of the present invention, the first capacitance test value, the second capacitance test value and the third capacitance test value of the transistor are separated and extracted, thereby improving the extraction accuracy of the parasitic capacitance. The separated and extracted capacitance test values ​​are written into the parasitic parameter extraction tool to ensure the reliability of the design, and the error between the simulation data and the test result is within 7%.

[0055] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.

[0056] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parasitic capacitance test circuit, characterized in that: The invention comprises a reference circuit and a test circuit, wherein the reference circuit comprises a coupled reference drive branch, a reference read branch and a reference branch, and the test circuit comprises a coupled test drive branch, a test read branch and a plurality of cascaded test branches, and the reference drive branch and the test drive branch are respectively connected to a drive current; wherein, The reference branch and the test branch are divided into several functional areas, and transistors and isolation areas are arranged on the functional areas; The gate of the transistor of the reference branch is electrically connected to the reference driving branch, a reference contact hole is provided on the functional area of ​​the reference branch, and the reference contact hole outputs a reference current to the reference reading branch; a reference gate pass dimension parallel to the first direction is provided between the reference contact hole and the gate; The gate of the transistor of the test branch is electrically connected to the test drive branch, a test contact hole is provided on the functional area of ​​the test branch, and the test contact hole outputs the test current of the corresponding test branch to the test reading branch; there is a test gate pass size parallel to the first direction between the test contact hole and the gate, and the test gate pass size is greater than 0 and less than or equal to the reference gate pass size; The test branch also includes a number of cascaded isolation test branches, and the test contact hole also includes an isolation test contact hole, which outputs the isolation test current of the corresponding isolation test branch to the test reading branch; a second test capacitor is formed between the isolation test contact hole and the corresponding gate, and the second test capacitor has a second test capacitance value, and the test gate pass size of each isolation test branch gradually increases.

2. The parasitic capacitance test circuit according to claim 1, characterized in that: The number of the reference contact holes and the test contact holes is the same and greater than or equal to 2; the reference contact holes are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area, and the test contact holes of each test branch are arranged at intervals perpendicular to the first direction along the edge of the corresponding functional area.

3. The parasitic capacitance test circuit according to claim 2, characterized in that: The functional area includes a diffusion area, the reference branch includes a diffusion reference branch, the test branch includes a plurality of cascaded diffusion test branches, the reference contact hole includes a diffusion reference contact hole, the test contact hole includes a diffusion test contact hole, the diffusion reference contact hole outputs a diffusion reference current to the reference read branch, the diffusion test contact hole outputs a diffusion test current of the corresponding diffusion test branch to the test read branch, a diffusion reference gate pass size is provided between the diffusion reference contact hole and the corresponding gate, a diffusion test gate pass size is provided between the diffusion test contact hole and the corresponding gate, and each diffusion reference gate pass size is equal to the diffusion test gate pass size.

4. The parasitic capacitance test circuit according to claim 3, characterized in that: The diffusion region has a diffusion size parallel to the first direction, the diffusion region of the diffusion reference branch has a minimum diffusion region size, a first reference capacitor is formed between the diffusion reference contact hole and the corresponding gate, a first test capacitor is formed between the diffusion test contact hole and the corresponding gate, and the diffusion size of the diffusion region of each diffusion test branch is greater than or equal to the minimum diffusion region size.

5. The parasitic capacitance testing circuit according to claim 4, characterized in that: The first reference capacitor has a first reference capacitance value, and the first test capacitor has a first test capacitance value; the diffusion size of the diffusion region of each diffusion test branch increases gradually.

6. The parasitic capacitance testing circuit according to claim 5, characterized in that: The functional area further includes an active area, the reference branch further includes an active reference branch, the test branch further includes a plurality of cascaded active test branches, the reference contact hole further includes an active reference contact hole, the test contact hole further includes an active test contact hole, the active reference contact hole outputs an active reference current to the reference read branch, and the active test contact hole outputs an active test current of the corresponding active test branch to the test read branch; A third reference capacitor is formed between the active reference contact hole and the corresponding gate, a third test capacitor is formed between the active test contact hole and the corresponding gate, the third reference capacitor has a third reference capacitance value, and the third test capacitor has a third test capacitance value; the active gate pass reference size of the active reference branch is the maximum gate pass size, and the test gate pass size of each active test branch gradually increases to the maximum gate pass size.

7. The parasitic capacitance testing circuit according to claim 6, characterized in that: The numbers of the isolation test contact holes, the active reference contact holes and the active reference contact holes are the same, and the numbers of the diffusion reference contact holes and the diffusion test contact holes are both 2.

8. The parasitic capacitance testing circuit according to claim 1, wherein: The reference circuit and the test circuit are respectively provided with shielding rings at their peripheries, and the shielding rings have openings. The reference drive branch, the reference read branch, the test drive branch, and the test read branch are respectively led out through the openings and electrically connected to the CBCM circuit.

9. A method for testing a parasitic capacitance test circuit as claimed in claim 6, characterized in that: A first capacitance difference curve is obtained according to the difference between the first test capacitance value and the first reference capacitance value and the corresponding diffusion size, and the first capacitance difference curve is fitted to obtain the first capacitance saturation value of the transistor; an initial third capacitance difference curve is obtained according to the difference between the third test capacitance value and the third reference capacitance value and the corresponding test gate pass size; the first capacitance saturation value and the initial third capacitance difference curve are fitted to obtain a third capacitance difference curve, and a second capacitance curve is obtained according to the second test capacitance value and the corresponding test gate pass size; the second capacitance curve and the third capacitance difference curve are fitted to obtain a third capacitance curve.

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