In-Memory Computing Circuit, Chip and Computing Device Based on Hybrid Data Input

Abstract

Embodiments of the present disclosure disclose a memory-computation integrated circuit, a chip, and a computing device based on hybrid data input. Among them, the circuit includes: a memory-computation unit array and a hybrid data input unit array; the hybrid data input unit in the hybrid data input unit array includes a computing data input subunit, a storage data input subunit, a data switching subunit, a data input port, and a data switching signal input port; the storage data input subunit is connected to the corresponding data storage subunit, and the computing data input subunit is connected to the corresponding multiple computing subunits; the data switching subunit is configured to switch the data received at the data input port to the data storage subunit or the computing subunit according to the data switching signal input at the data switching signal input port. Compared with the conventional solution in which the storage data input unit and the computing data input unit are separately arranged, the embodiments of the present disclosure reduce the area of the circuit layout by setting the hybrid data input unit.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a storage-computing integrated circuit, chip, and computing device based on mixed data input. Background Art

[0002] Storage-computing integration is a storage-computing design that integrates static random access memory and computing modules, usually including storage structure and multiplication-addition structure. Compared with traditional memory, the storage-computing integration design has not only a port for writing storage data, but also a port for input data for multiplication with storage data. This port is responsible for transmitting input data to the storage computing unit for calculation.

[0003] The existing implementation solution is to design the storage data write port and the calculation data input port separately. Since the number of calculation data input ports is often the same as the number of memory word lines, the integrated storage design has more ports than traditional memory, which increases the area of ​​the overall integrated storage and calculation design, and significantly increases the routing of the docking input ports when the integrated storage and calculation design is used externally. Summary of the invention

[0004] An embodiment of the present disclosure provides a storage-computation integrated circuit based on hybrid data input, the circuit comprising: a storage computing unit array, a hybrid data input unit array, the storage computing unit array comprising a first preset number of storage computing unit groups, the storage computing units in each storage computing unit group corresponding one-to-one to the hybrid data input units in the hybrid data input unit array; the hybrid data input units in the hybrid data input unit array comprise a computing data input sub-unit, a storage data input sub-unit, a data switching sub-unit, a data input port and a data switching signal input port; the storage data input sub-unit is connected to the data storage sub-unit included in the corresponding storage computing unit, and the computing data input sub-unit is connected to the computing sub-unit included in the storage computing unit in the corresponding storage computing unit group; the data switching sub-unit is used to input the data received by the data input port into the data storage sub-unit or the computing sub-unit according to the data switching signal input from the data switching signal input port.

[0005] In some embodiments, the computing subunit includes a multiplier, and the multiplier is used to perform multiplication calculation on the data in the corresponding data storage subunit and the computing subunit.

[0006] In some embodiments, the circuit further includes a main controller configured to adjust the current memory-computation mode. The memory-computation mode includes a storage mode and a computation mode. In the storage mode, the main controller sends a first switching signal to the data switching signal input port. In the computation mode, the main controller sends a second switching signal to the data switching signal input port. The first switching signal is used to indicate that the data received by the current data input port is input into the corresponding storage data input sub-unit. The second switching signal is used to indicate that the data received by the current data input port is input into the corresponding computation data input sub-unit.

[0007] In some embodiments, the circuit further includes an address decoder. The main controller is further configured to obtain the address of the data to be input and send the address of the data to be input to the address decoder. The address decoder is configured to determine a target memory-computation unit group from a first preset number of memory-computation unit groups according to the address of the data to be input. The main controller is further configured to send the data to be input to the target memory-computation unit group through the data input ports included in the hybrid data input unit array.

[0008] In some embodiments, the circuit further includes an adder array configured to add the computation results input from a first preset number of memory-computation unit groups to obtain an accumulation result.

[0009] In some embodiments, the adder array includes a second preset number of adder groups. The second preset number of adder groups are connected in cascade in sequence, and the inputs of the adders included in the first-stage adder group of the second preset number of adder groups are respectively connected to the corresponding memory-computation unit groups.

[0010] In some embodiments, the circuit further includes a shift accumulator configured to perform shifting and accumulation of at least two values output successively by the adder array for corresponding bits to obtain an accumulation result.

[0011] According to another aspect of the embodiments of the present disclosure, there is provided a chip including the above-mentioned memory-computation integrated circuit based on hybrid data input.

[0012] According to another aspect of the embodiments of the present disclosure, there is provided a computing device including the above-mentioned chip.

[0013] The computing-in-memory circuit, chip, and computing device provided in the above embodiments of the present disclosure integrate the input port for computing data and the input port for storage data into a hybrid data input unit, reducing the number of input ports of the computing-in-memory circuit to the same as that of a traditional memory with only storage function, thereby reducing the consumption of routing resources caused by the connection traces between the inside and outside of the computing-in-memory circuit and the data input ports. By combining the computing data input sub-unit and the storage data input sub-unit, compared with the traditional solution where the storage data input unit and the computing data input unit are separately arranged, the embodiments of the present disclosure reduce the circuit layout area by setting up a hybrid data input unit.

[0014] The technical solution of the present disclosure will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By describing the embodiments of the present disclosure in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent. The drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation to the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1 is a schematic structural diagram of a computing-in-memory circuit in the prior art.

[0017] Figure 2 is a schematic structural diagram of a computing-in-memory circuit based on hybrid data input provided by an exemplary embodiment of the present disclosure.

[0018] Figure 3 is a schematic structural diagram of a hybrid data input unit provided by an exemplary embodiment of the present disclosure.

[0019] Figure 4 is a schematic structural diagram of an adder array provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Next, exemplary embodiments according to the present disclosure will be described in detail with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments of the present disclosure. It should be understood that the present disclosure is not limited by the exemplary embodiments described herein.

[0021] It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present disclosure.

[0022] Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0023] It should also be understood that in the embodiments of the present disclosure, "a plurality of" may refer to two or more, and "at least one" may refer to one, two, or more.

[0024] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present disclosure, in the absence of a clear limitation or contrary indication in the context, it is generally understood to be one or more.

[0025] In addition, the term "and / or" in the present disclosure is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0026] It should also be understood that the description of each embodiment in the present disclosure emphasizes the differences between the embodiments, and their similarities or similarities can be referred to each other. For the sake of brevity, they will not be elaborated one by one.

[0027] At the same time, it should be understood that for the sake of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0028] The following description of at least one exemplary embodiment is actually merely illustrative and in no way a limitation on the present disclosure and its application or use.

[0029] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0030] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0031] Application Overview

[0032] The current in-memory computing design architecture has an additional computing data input unit compared to the traditional memory, which increases the area and also increases the input data ports. As Figure 1As shown, for the input of 128-bit stored data and the input of 128-bit computed data, a total of 256-bit data input ports are required, that is, 128 stored data input units and 128 computed data input units. Due to the large number of input data ports in the prior art, the area of the overall memory-computation integrated circuit is large, and when using the memory-computation integrated circuit externally, the wire resources consumed for docking the input ports increase significantly.

[0033] Exemplary Structure

[0034] Figure 2 FIG. is a schematic structural diagram of a memory-computation integrated circuit based on hybrid data input provided by an exemplary embodiment of the present disclosure. Each component included in this circuit can be integrated into one chip, or can be arranged in different chips or circuit boards, and a data communication link is established between these chips or circuit boards.

[0035] As Figure 2 shown, this circuit includes: a memory-computation unit array 201 and a hybrid data input unit array 202. Among them, the memory-computation unit array 201 includes a first preset number of memory-computation unit groups, and the memory-computation units in each memory-computation unit group correspond one-to-one with the hybrid data input units in the hybrid data input unit array 202. As Figure 2 shown, the first preset number is N, and M cells (i.e., memory-computation units) in each row represent a memory-computation unit group, that is, one memory-computation unit group can store M single-bit data. The hybrid data input unit array 202 includes M hybrid data input units.

[0036] In this embodiment, each hybrid data input unit in the hybrid data input unit array 202 also corresponds to a memory-computation unit group. For example, Figure 2 the Mth hybrid data input unit shown corresponds to the Nth memory-computation unit group (i.e., the Nth row of cells).

[0037] As Figure 3 shown, it shows the structure of one of the hybrid data input units 2021. The hybrid data input unit 2021 includes a computed data input subunit 20211, a stored data input subunit 20212, a data switching subunit 20213, a data input port 20214, and a data switching signal input port 20215. The stored data input subunit 20212 is connected to the data storage subunit 20112 included in the corresponding memory-computation unit 2011, and the computed data input subunit 20211 is connected to the memory-computation units included in the corresponding memory-computation unit group (i.e., Figure 2 a row of cells in Figure 3 including the memory-computation units 2011, 2012,..., 2013 inFigure 3 are connected to the computing sub-units 20111, 20121, …, 20131 therein.

[0038] Among them, the data storage sub-unit 20112 is used to store a single-bit data, and the computing sub-unit 20111 is used to perform calculations in a preset manner on the stored data in the data storage sub-unit 20112 and the single-bit computing data input by the computing data input sub-unit 20211. The functions of other computing sub-units are the same and will not be elaborated here.

[0039] It should be noted that, as Figure 2 shown, a row of cells usually stores different bits of a multi-bit data. Therefore, when performing calculations on the stored data and the computing data, the computing data input sub-unit 20211 simultaneously inputs the same single-bit data to a row of cells. After multiple inputs, the single-bit positions included in a complete multi-bit computing data can be respectively calculated with the multi-bit stored data stored in the cells of that row.

[0040] In this embodiment, the data switching sub-unit 20213 is used to input the data received by the data input port 20214 into the data storage sub-unit 20112 or the computing sub-unit 20111 according to the data switching signal input by the data switching signal input port 20215.

[0041] Among them, the data switching signal can be a signal sent by the main controller included in this circuit or an external electronic device. The data switching sub-unit 20213 can include a circuit module of an analog single-pole double-throw switch, and this circuit module can connect the data switching signal input port 20215 to the computing data input sub-unit 20211 or the stored data input sub-unit 20212.

[0042] The circuit provided by the above embodiment of the present disclosure integrates the input ports of the computing data and the input ports of the stored data into a hybrid data input unit, reducing the number of input ports of the memory-in-computation circuit to the same as that of a traditional memory with only storage function, thereby reducing the consumption of routing resources caused by the connection traces between the inside and outside of the memory-in-computation circuit and the data input ports. By combining the computing data input sub-unit and the stored data input sub-unit, compared with the traditional solution where the stored data input unit and the computing data input unit are separately arranged, the embodiment of the present disclosure reduces the circuit layout area by setting the hybrid data input unit.

[0043] In some alternative implementations, the computing subunit may include a multiplier, which is used to perform multiplication calculations on the data in the corresponding data storage subunit and the computing subunit. This multiplier is typically a single-bit multiplier, and there are various implementation methods for the single-bit multiplier, such as the combination of an AND gate, a NOT gate, and a NOR gate (i.e., performing a NOR operation after inverting the stored data and the computing data), etc.

[0044] In this implementation, the computing subunit is set as a single-bit multiplier, which can implement in-memory multiplication operations. It can also be combined with an adder array to implement in-memory multiply-accumulate operations, thereby effectively utilizing the characteristic of the small number of circuit ports and improving the efficiency of in-memory multiplication or multiply-accumulate operations.

[0045] In some alternative implementations, as Figure 2 shown, the circuit further includes a main controller 203, and the main controller 203 is used to adjust the current memory-computation mode. Among them, the memory-computation mode includes a storage mode and a computing mode.

[0046] In the storage mode, the main controller 203 sends a first switching signal to the data switching signal input port; in the computing mode, the main controller sends a second switching signal to the data switching signal input port.

[0047] Among them, referring to Figure 3 , the first switching signal is used to indicate that the data received by the current data input port 20214 is input into the corresponding storage data input subunit 20212; the second switching signal is used to indicate that the data received by the current data input port 20214 is input into the corresponding computing data input subunit 20211.

[0048] Specifically, if the circuit is used in a traditional data storage scenario, the main controller 203 can adjust the memory-computation mode to the storage mode. At this time, the hybrid data input unit array 202 is equivalent to a traditional storage data input array. If the circuit is used in a scenario of in-memory computing for algorithms such as neural networks, the controller can first adjust the memory-computation mode to the storage mode. At this time, the hybrid data input unit array 202 inputs the storage data received by the data input port into the corresponding storage computing unit group for storage. Then, the main controller 203 can adjust the memory-computation mode to the computing mode, and the computing data received by the data input port is input into the corresponding storage computing unit group for calculation.

[0049] In this implementation, by setting a main controller in the circuit and having the main controller adjust the memory-computation mode, it is possible to effectively control the data transmission and data calculation of each component in the circuit, making the function of the memory-computation integrated circuit more perfect and improving the efficiency of storage computing from the memory-computation integrated circuit.

[0050] In some alternative implementations, as Figure 2As shown, the circuit further includes an address decoder 204.

[0051] The main controller 203 is further configured to obtain the address of the data to be input and send the address of the data to be input to the address decoder. Among them, the address of the data to be input can be automatically determined when the program on the main controller 203 runs.

[0052] The address decoder is configured to determine the target storage and calculation unit group from the first preset number of storage and calculation unit groups according to the address of the data to be input. After sending the address of the data to be input add1 to the address decoder 204, the address decoder 204 further selects the target storage and calculation unit group. As Figure 2 shown, the storage and calculation unit group located in the first row is the target storage and calculation unit group.

[0053] The main controller 203 is further configured to send the data to be input to the target storage and calculation unit group through the data input ports included in the hybrid data input unit array 202 of the hybrid data input unit. Specifically, the main controller 203 can control the word line corresponding to the target storage and calculation unit group to be connected to the hybrid data input unit array 202, and the main controller 203 sends a data switching signal to the data switching signal input ports in each hybrid data input unit according to the current storage and calculation mode, so that each hybrid data input unit sends the data to be input to the target storage and calculation unit group for data storage or calculation.

[0054] In this implementation manner, by setting the address decoder, the target storage and calculation unit group can be accurately determined, which helps to further improve the accuracy of data transmission when using fewer data input ports.

[0055] In some alternative implementation manners, as Figure 2 shown, the circuit further includes an adder array 205, and the adder array 205 is configured to add the calculation results input from the first preset number of storage and calculation unit groups to obtain an accumulated result.

[0056] In this implementation manner, by setting the adder array, the calculation results output by the storage and calculation unit array can be added to obtain an accumulated result, which can support the multiply-accumulate operations in scenarios such as neural networks, and reduce the area of the multiply-accumulate operation circuit and the consumed routing resources by reducing the number of data input ports.

[0057] In some alternative implementation manners, the adder array includes a second preset number of adder groups, the second preset number of adder groups are connected in cascade in sequence, and the inputs of the adders included in the first-stage adder group of the second preset number of adder groups are respectively connected to the corresponding storage and calculation unit groups.

[0058] As Figure 4As shown in the figure, the adder array includes P (i.e., the second preset number) columns. Each column includes an adder group, that is, the first column marked as "adder_1" is the first-level adder group, the second column marked as "adder_2" is the second-level adder group,..., and the Pth column marked as "adder_P" is the Pth-level adder group. Starting from the second-level adder group, each adder corresponds to two adders in the previous level, that is, the outputs of two adders in the previous level are used as the inputs of the adder in the next level. Each adder included in the first-level adder group receives the calculation result input by the corresponding storage calculation unit. The Pth-level adder group only includes one adder, and the data output by it is the sum of the data respectively output by N storage calculation unit groups.

[0059] In this implementation manner, by setting cascaded adder groups, the area occupied by the adder array can be effectively saved, the area utilization rate of the circuit can be improved, and the length of the data transmission line in the circuit can be shortened, which is beneficial to reducing the circuit power consumption.

[0060] In some optional implementation manners, as Figure 2 shown in the figure, the circuit further includes a shift accumulator 206, and the shift accumulator is used to perform shifting and accumulation of corresponding bits on at least two values successively output by the adder array to obtain an accumulation result.

[0061] As an example, if the hybrid data input unit array 202 sequentially inputs the 0th bit, 1st bit, 2nd bit, and 3rd bit of N calculation data through each calculation data input subunit four times in sequence, the summation results successively output by the adder array are s0, s1, s2, s3, and the shift accumulator calculates the multiply-accumulate result according to the following formula: SUM = s3 * 8 + s2 * 4 + s1 * 2 + s0.

[0062] In this implementation manner, by setting a shift accumulator, the multiply-accumulate operation of multi-bit data can be realized, effectively utilizing the characteristic of fewer data input ports, further improving the area utilization rate of the multi-bit data multiply-accumulate operation circuit, reducing the routing complexity in the circuit, and being beneficial to reducing the circuit power consumption.

[0063] The embodiments of the present disclosure further provide a chip, on which a memory-computation integrated circuit based on hybrid data input is integrated. The technical details of the memory-computation integrated circuit based on hybrid data input are as Figures 1-4 shown and described relatedly, and will not be elaborated here.

[0064] Embodiments of the present disclosure also provide a computing device, which includes the chip described in the above embodiments. In addition, the computing device may further include an input device, an output device, and necessary memories, etc. Among them, the input device may include, for example, a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting stored data, calculation data, etc. The output device may include, for example, a display, a printer, a communication network, and remote output devices connected thereto, etc., for outputting data such as accumulated results. The memory is used to store the data input by the above input device and the data generated during the operation of the memory-computation integrated circuit based on the hybrid data input. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0065] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. In addition, the above specific details disclosed are only for the purposes of illustration and facilitating understanding, rather than limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0066] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0067] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any way. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used here refer to "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used here refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0068] The circuits of the present disclosure can be implemented in many ways. For example, the circuits of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the methods in the circuits is for illustration only. The steps of the methods of the present disclosure are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the functions of the circuits according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the functions of the circuits according to the present disclosure.

[0069] It should also be noted that in the circuits of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present disclosure.

[0070] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0071] The above description has been presented for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A memory - in - computing circuit based on hybrid data input, comprising: a memory - computing unit array and a hybrid data input unit array, wherein the memory - computing unit array includes a first preset number of memory - computing unit groups, and the memory - computing units in each memory - computing unit group correspond one - to - one with the hybrid data input units in the hybrid data input unit array; the hybrid data input units in the hybrid data input unit array include a computing data input subunit, a storage data input subunit, a data switching subunit, a data input port, and a data switching signal input port; the storage data input subunit is connected to the data storage subunit included in the corresponding memory - computing unit, and the computing data input subunit is connected to the computing subunit included in the memory - computing unit in the corresponding memory - computing unit group; the data switching subunit is configured to input the data received by the data input port into the data storage subunit or the computing subunit according to the data switching signal input through the data switching signal input port.

2. The circuit according to claim 1, wherein, the computing subunit includes a multiplier, and the multiplier is configured to perform a multiplication calculation on the data in the corresponding data storage subunit and computing subunit.

3. The circuit according to claim 1, wherein, the circuit further includes a main controller, and the main controller is configured to adjust the current memory - in - computing mode. The memory - in - computing mode includes a storage mode and a computing mode. In the storage mode, the main controller sends a first switching signal to the data switching signal input port; in the computing mode, the main controller sends a second switching signal to the data switching signal input port. The first switching signal is used to indicate inputting the data currently received by the data input port into the corresponding storage data input subunit; the second switching signal is used to indicate inputting the data currently received by the data input port into the corresponding computing data input subunit.

4. The circuit according to claim 3, wherein, the circuit further includes an address decoder; the main controller is further configured to obtain the address of the data to be input and send the address of the data to be input to the address decoder; the address decoder is configured to determine a target memory - computing unit group from the first preset number of memory - computing unit groups according to the address of the data to be input; the main controller is further configured to send the data to be input to the target memory - computing unit group through the data input port included in the hybrid data input units in the hybrid data input unit array.

5. The circuit according to claim 1, wherein, the circuit further includes an adder array, and the adder array is configured to add the calculation results input from the first preset number of memory - computing unit groups to obtain an accumulation result.

6. The circuit according to claim 5, wherein, The adder array includes a second preset number of adder groups, the second preset number of adder groups are sequentially connected in a cascaded manner, and the input ends of the adders included in the first-stage adder group among the second preset number of adder groups are respectively connected to the corresponding storage calculation unit groups.

7. The circuit according to claim 5, wherein, the circuit further includes a shift accumulator, and the shift accumulator is configured to perform shifting and accumulation of corresponding bits on at least two values sequentially output by the adder array to obtain an accumulation result.

8. A chip, characterized in that, it includes the memory-computation integrated circuit based on hybrid data input according to any one of claims 1-7.

9. A computing device, characterized in that, it includes the chip according to claim 8.

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