Memory device and operating method thereof

Abstract

The present invention relates to a memory device and an operating method thereof. The present technology relates to an electronic device. According to the present technology, a method for operating a memory device includes a programming operation speed that reduces interference effects and includes multiple memory blocks, each memory block includes multiple memory cell strings, each memory cell string includes multiple memory cells connected in series between a bit line and a source line, multiple source select transistors connected in series between the source line and the multiple memory cells, and multiple drain select transistors connected in series between the bit line and the multiple memory cells, the method comprising: applying a precharge voltage to the source line; and applying a precharge voltage to a first source select line, the first source select line being connected to a source select transistor adjacent to the source line among source select transistors included in an unselected memory block among the multiple memory blocks.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices can be categorized as volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device may be a device that stores data only when power is supplied and loses the stored data when the power is disconnected. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0004] Non-volatile memory devices are devices that do not lose data even when power is turned off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] Embodiments of the present disclosure provide a memory device having a program operation speed with reduced disturb effects and a method of operating the memory device.

[0006] According to an embodiment of the present disclosure, a method for operating a memory device includes a plurality of memory blocks, each memory block includes a plurality of memory cell strings, each memory cell string includes a plurality of memory cells connected in series between a bit line and a source line, a plurality of source selection transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain selection transistors connected in series between the bit line and the plurality of memory cells, the method comprising: applying a precharge voltage to the source line; and applying a precharge voltage to a first source selection line, the first source selection line being connected to a source selection transistor adjacent to the source line among the source selection transistors included in an unselected memory block among the plurality of memory blocks.

[0007] According to an embodiment of the present disclosure, a memory device includes: a plurality of memory blocks, each memory block including a plurality of memory cell strings, each memory cell string including a plurality of memory cells connected in series between a bit line and a source line, a plurality of source selection transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain selection transistors connected in series between the bit line and the plurality of memory cells; a peripheral circuit configured to perform a plurality of programming loops, each programming loop including a programming step of providing a programming voltage to a selected memory block among the plurality of memory blocks; and a verification step of verifying a programming state of the selected memory block; and a programming operation controller configured to control the peripheral circuit to apply a precharge voltage to the source line in the programming step, and to apply a precharge voltage to a first source selection line connected to a source selection transistor adjacent to the source line among the source selection transistors included in an unselected memory block among the plurality of memory blocks.

[0008] According to an embodiment of the present disclosure, a method for operating a memory device includes a plurality of memory blocks, each memory block includes a plurality of memory cell strings, each memory cell string includes a plurality of memory cells connected in series between a bit line and a source line, a plurality of source selection transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain selection transistors connected in series between the bit line and the plurality of memory cells, the method comprising: applying a precharge voltage to the source line; and after the source line is precharged to a first voltage level, applying a precharge voltage to a first source selection line, the first source selection line being connected to a source selection transistor adjacent to the dummy source line among the source selection transistors included in an unselected memory block among the plurality of memory blocks.

[0009] According to an embodiment of the present disclosure, a method for programming a string of nonvolatile memory cells, the nonvolatile memory cells being coupled to at least a source line and including at least a source select transistor, the method comprising: applying a precharge voltage to the source line during a precharge period; and during the precharge period, after applying the precharge voltage to the source line, applying a precharge voltage to a source select line coupled to an adjacent source select transistor, wherein the adjacent source select transistor is most adjacent to the source line among the source select transistors.

[0010] According to the present technology, a memory device having a program operation speed with reduced disturbance influence and a method of operating the memory device are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram for describing a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 is used to describe Figure 1 Figure 1 is a diagram of a memory device.

[0013] Figure 3 It is an example Figure 2 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0014] Figure 4 It is an example Figure 3 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0015] Figure 5 It is an example Figure 3 FIG. 1 is a circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0016] Figure 6 It is an example Figure 3 1 is a circuit diagram of another embodiment of any one memory block BLKi among the memory blocks BLK1 to BLKz.

[0017] Figure 7 is used to describe Figure 2 FIG. 1 is a diagram of a programming operation of a memory device.

[0018] Figure 8 is used to describe Figure 2 A diagram illustrating the order in which memory cells included in a memory device are programmed.

[0019] Figure 9 is a waveform diagram for describing a method of operating a memory device according to an embodiment of the present disclosure.

[0020] Figure 10 is used to describe Figure 2 The control logic included in the programming operation controller is a block diagram of the configuration.

[0021] Figure 11 is used to describe Figure 1 Figure 1. Memory controller diagram.

[0022] Figure 12 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0023] Figure 13 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0024] Figure 14 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0025] The specific structures or functions disclosed in this specification or application are merely exemplified for describing the embodiments according to the present disclosure. The embodiments of the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0026] Figure 1 is a diagram for describing a storage device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device. The storage device 50 may be a device that stores data under the control of a host 300 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0028] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any one of the following types of storage devices: an SSD; a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC; a secure digital card in the form of SD, mini SD, and micro SD; a universal serial bus (USB) storage device; a universal flash storage (UFS) device; a personal computer memory card international association (PCMCIA) card type storage device; a peripheral component interconnect (PCI) card type storage device; a PCI-Express (PCI-E) card type storage device; a compact flash (CF) card; a smart media card, and a memory stick.

[0029] The storage device 50 may be manufactured as any of various types of packages. For example, the storage device 50 may be manufactured as any of various types of packages such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabricated package (WFP), and wafer-level stacked package (WSP).

[0030] The memory device 100 may store data and operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells storing data.

[0031] Each of the memory cells can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0032] The memory cell array (not shown) may include a plurality of memory blocks. A memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0033] In embodiments, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low-power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low-power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, the memory device 100 is a NAND flash memory.

[0034] The memory device 100 is configured to receive a command CMD and an address ADDR from the memory controller 200 and access an area selected by the address in the memory cell array. The memory device 100 can perform an operation indicated by the command CMD on the area selected by the address ADDR. For example, the memory device 100 can perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device 100 can program data in the area selected by the address ADDR. During a read operation, the memory device 100 can read data from the area selected by the address ADDR. During an erase operation, the memory device 100 can erase data stored in the area selected by the address ADDR.

[0035] The memory controller 200 may control overall operations of the storage device 50 .

[0036] When power is applied to the storage device 50, the memory controller 200 may execute the firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the memory controller 200 and the host 300, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0037] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and may convert the LBA into a physical block address (PBA) indicating an address of a memory cell in which data included in the memory device 100 is to be stored. In this specification, LBA and "logical address" or "logical address" may be used to have the same meaning. In this specification, PBA and "physical address" may be used to have the same meaning.

[0038] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. according to a request from the host 300. During a program operation, the memory controller 200 can provide a write command, a PBA, and data to the memory device 100. During a read operation, the memory controller 200 can provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 can provide an erase command and a PBA to the memory device 100.

[0039] In an embodiment, the memory controller 200 may independently generate commands, addresses, and data, regardless of a request from the host 300, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing read and program operations, and may also perform wear leveling, read reclamation, garbage collection, and the like.

[0040] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be a method of controlling the operations of at least two memory devices 100 to overlap with each other.

[0041] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0042] Figure 2 is used to describe Figure 1 FIG. 1 is a diagram of a memory device 100 .

[0043] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0044] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz can be connected to a page buffer group 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0045] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0046] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0047] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or discharge the applied voltages under the control of the control logic 130.

[0048] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , and an input / output circuit 125 .

[0049] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe select line.

[0050] The row decoder 121 is configured to operate in response to the control of the control logic 130. The row decoder 121 receives a row address RADD from the control logic 130.

[0051] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 can select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0052] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a level higher than the read voltage to unselected word lines.

[0053] In an embodiment, an erase operation of the memory device 100 is performed in memory block units. During the erase operation, the row decoder 121 may select a memory block according to a decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to a word line connected to the selected memory block.

[0054] The voltage generator 122 operates in response to the control of the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage provided to the memory device 100. Specifically, the voltage generator 122 can generate various operating voltages Vop for program operations, read operations, and erase operations in response to the operation signal OPSIG. For example, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. in response to the control of the control logic 130.

[0055] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0056] In an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0057] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and may selectively activate the plurality of pumping capacitors in response to the control of the control logic 130 to generate a plurality of voltages.

[0058] The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121 .

[0059] The page buffer group 123 includes a first page buffer PB1 to an mth page buffer PBm. The first page buffer PB1 to the mth page buffer PBm are connected to the memory cell array 110 through the first bit line BL1 to the mth bit line BLm, respectively. The first page buffer PB1 to the mth page buffer PBm operate in response to the control of the control logic 130. Specifically, the first page buffer PB1 to the mth page buffer PBm can operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verify operation, the first page buffer PB1 to the mth page buffer PBm can temporarily store data received through the first bit line BL1 to the mth bit line BLm, or can sense the voltage or current of the bit lines BL1 to BLm.

[0060] Specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first to m-th page buffers PB1 to PBm can transmit data DATA received through the input / output circuit 125 to the selected memory cells through the first to m-th bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a program permission voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a program inhibition voltage (e.g., a power supply voltage) is applied can be maintained. During a program verification operation, the first to m-th page buffers PB1 to PBm can read page data from the selected memory cells through the first to m-th bit lines BL1 to BLm.

[0061] During a read operation, the first to mth page buffers PB1 to PBm read data DATA from memory cells of a selected page through the first to mth bit lines BL1 to BLm and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0062] During an erase operation, the first to m-th page buffers PB1 to PBm may float the first to m-th bit lines BL1 to BLm.

[0063] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to mth page buffers PB1 to PBm through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0064] The input / output circuit 125 can transmit the reference signal to the control logic 130. Figure 1 The depicted memory controller 200 receives a command CMD and an address ADDR, or may exchange data DATA with the column decoder 124 .

[0065] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the permission bit signal VRYBIT and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0066] The control logic 130 may output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and a permission bit VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. In addition, the control logic 130 may determine whether a verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0067] In an implementation, the control logic 130 may include a programming operation controller 131 .

[0068] The program operation controller 131 may control the peripheral circuit 120 to perform a program operation according to a program command input from the memory controller 200. Figure 9 and Figure 10 The program operation performed by the program operation controller 131 is described in more detail.

[0069] Figure 3 It is an example Figure 2 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0070] Reference Figure 3, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0071] Figure 4 It is an example Figure 3 A circuit diagram of any memory block BLKa among the memory blocks BLK1 to BLKz.

[0072] Reference Figure 4 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged along a row direction (ie, +X direction). Figure 4 , two cell strings are arranged along the column direction (ie, +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings may be arranged along the column direction.

[0073] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0074] Each of the select transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating film, the charge storage film, and the blocking insulating film may be provided in each cell string.

[0075] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0076] In an embodiment, source selection transistors of cell strings arranged in the same row are connected to a source selection line extending in a row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4, the source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1, and the source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2.

[0077] In another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0078] The first to nth memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0079] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in a direction opposite to the +Z direction and are connected in series between a source select transistor SST and a tube transistor PT. The (p+1)th memory cells MCp+1 to nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between a tube transistor PT and a drain select transistor DST. The first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn are connected to each other via the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

[0080] The gate of the pipe transistor PT of each cell string is connected to a pipe line PL.

[0081] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The drain select transistors of the cell strings arranged along the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to a second drain select line DSL2.

[0082] The cell strings arranged along the column direction are connected to the bit lines extending in the column direction. Figure 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1, and the cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

[0083] Memory cells connected to the same word line in the cell strings arranged in the row direction constitute a page. For example, the memory cells connected to the first word line WL1 in the cell strings CS11 to CS1m in the first row constitute one page. The memory cells connected to the first word line WL1 in the cell strings CS21 to CS2m in the second row constitute another page. The cell strings arranged in a row can be selected by selecting any one of the drain select lines DSL1 and DSL2. A page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0084] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

[0085] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells are provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operational reliability of the memory block BLKa is improved; however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa can be reduced; however, the operational reliability of the memory block BLKa is reduced.

[0086] In order to effectively control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a programming operation can be performed on all or part of the dummy memory cells. When the erase operation is performed after the programming operation, the dummy memory cells can be made to have the desired threshold voltage by controlling the voltage applied to the dummy word line connected to each dummy memory cell.

[0087] Figure 5 It is an example Figure 3 FIG. 1 is a circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0088] Reference Figure 5, the memory block BLKb includes a plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along the +Z direction. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLK1′.

[0089] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11′ to CS1m′ arranged in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21′ to CS2m′ arranged in the second row are connected to a second source select line SSL2. In another embodiment, the source select transistors of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ can be connected in common to one source select line.

[0090] The first to nth memory cells MC1 to MCn of each cell string are connected in series between a source select transistor SST and a drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0091] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged along the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11′ to CS1m′ in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21′ to CS2m′ in the second row are connected to the second drain select line DSL2.

[0092] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 5 The memory block BLKb has Figure 4 The equivalent circuit of the memory block BLKa is similar.

[0093] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to even bit lines, respectively, and odd cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to odd bit lines, respectively.

[0094] In an embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operational reliability of the memory block BLKb is improved; however, the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb can be reduced; however, the operational reliability of the memory block BLKb is reduced.

[0095] To effectively control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation of memory block BLKb, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after a programming operation, the dummy memory cells can be set to the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the respective dummy memory cells.

[0096] Figure 6 It is an example Figure 3 1 is a circuit diagram of another embodiment of any one memory block BLKi among the memory blocks BLK1 to BLKz.

[0097] Reference Figure 6 , a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be source selection lines SSL1 and SSL2, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLm and the source line SL. The bit lines BL1 to BLm may be connected to the strings ST, respectively, and the source line SL may be connected to the strings ST in common. Since the strings ST may be configured identically to each other, the string ST connected to the first bit line BL1 will be described in detail as an example.

[0098] The string ST may include source select transistors SST1 and SST2 connected in series between a source line SL and a first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain select transistor DST. One string ST may include at least one or more drain select transistors DST, and may include more source select transistors and memory cells than the number of source select transistors SST1 and SST2 and memory cells MC1 to MC16 shown in the figure.

[0099] The sources of the source select transistors SST1 and SST2 can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source select transistors SST1 and SST2 and the drain select transistor DST. The gates of the source select transistors SST1 and SST2 included in different strings ST can be connected to multiple source select lines SSL1 and SSL2, respectively, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a page PG. Therefore, the memory block BLKi can include page PGs as many as the number of word lines WL1 to WL16.

[0100] In embodiments, the source select transistor SST1 adjacent to the source line SL among the source select transistors SST1 and SST2 may be connected to the first source select line SSL1. In this case, capacitive coupling may occur between the first source select line SSL1 and the source line SL. Alternatively, in embodiments, the source select transistor SST2 not adjacent to the source line SL among the source select transistors SST1 and SST2 may be connected to the second source select line SSL2. In this case, capacitive coupling may not occur between the second source select line SSL2 and the source line SL. Furthermore, a greater number of source select lines than the illustrated number of source select lines SSL1 and SSL2 may be included.

[0101] One memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, one physical page (PG) can store one logical page (LPG) of data. One logical page (LPG) of data can include the same number of data bits as the number of cells included in one physical page (PG).

[0102] One memory cell can store two or more bits of data. In this case, one physical page PG can store two or more logical pages (LPG) of data.

[0103] Figure 7 is used to describe Figure 2 FIG. 1 is a diagram of a programming operation of a memory device.

[0104] exist Figure 7 In the embodiment, for ease of description, each of the plurality of memory cells is a multi-level cell (MLC) storing 2-bit data. However, the scope of the present disclosure is not limited thereto, and each of the plurality of memory cells may be a triple-level cell (TLC) storing 3-bit data or a quad-level cell (QLC) storing 4-bit data.

[0105] The program operation of the memory device 100 may include a plurality of program loops PL1 to PLn. That is, the memory device 100 may program selected memory cells to have a threshold voltage corresponding to any one of a plurality of program states by performing the plurality of program loops PL1 to PLn.

[0106] Each of the plurality of program loops PL1 to PLn may include a program step PGM Step of supplying a program voltage and a verification step Verify Step of determining whether a memory cell is programmed by applying a verification voltage.

[0107] The program step PGM Step included in each program loop may include a precharge period Precharge, a program period Program, and a discharge period Discharge.

[0108] The precharge period Precharge may be a period for precharging the source line and the select line. The memory device 100 may precharge the source line and the select line by applying a precharge voltage to the source line and the select line.

[0109] The programming period "Program" may be a period for programming a selected memory cell to have a threshold voltage corresponding to a programmed state. For example, the memory device 100 may apply a program voltage to a selected word line and a program pass voltage having a lower level than the program voltage to unselected word lines. Alternatively, the memory device 100 may apply a ground voltage corresponding to 0V to a selected bit line and a power supply voltage to unselected bit lines. Thus, the memory device 100 may cause the selected memory cell to have a threshold voltage corresponding to the programmed state.

[0110] The discharge period Discharge may be a period for discharging voltages applied to the word lines and the select line. The memory device 100 may discharge the voltages applied to the word lines and the select line by applying a ground voltage corresponding to 0V to the word lines and the select line.

[0111] Figure 8 is used to describe Figure 2A diagram illustrating the order in which memory cells included in a memory device are programmed.

[0112] Reference Figure 8 , showing an unselected memory cell string. A memory cell string may include a plurality of memory cells connected in series between a bit line BL and a source line SL. The memory cells may be connected to word lines, respectively. A drain select transistor may be connected between the memory cell and the bit line, and a source select transistor may be connected between the memory cell and the source line. The drain select transistor may be controlled by a drain select line, and the source select transistor may be controlled by a source select line.

[0113] For ease of description, a memory cell string is connected to eight word lines WL1 to WL8. Memory cells connected to the fifth to eighth word lines WL5 to WL8 are programmed memory cells, and memory cells connected to the first to fourth word lines WL1 to WL4 are pre-programmed memory cells. The memory cell string also includes a first source select line SSL1 adjacent to a source line SL and a second source select line SSL2 not adjacent to the source line SL.

[0114] In one embodiment, the programming operation can be performed sequentially from the eighth word line WL8 adjacent to the drain select line DSL to the first word line WL1 adjacent to the source select lines SSL1 and SSL2. This is referred to as a reverse sequence. In this case, during the precharge period, the memory device 100 can precharge the channels of the memory cell strings via the source lines SL. The memory device 100 can precharge unselected memory cell strings before applying the programming voltage to reduce disturbances during the programming operation. As the voltage level precharged to the source lines SL increases, disturbances can be further reduced.

[0115] Therefore, in an embodiment of the present disclosure, a memory device having a program operation speed with reduced interference influence by precharging a source line SL in two steps in a precharge period and a method of operating the memory device are provided.

[0116] In the following, reference will be made to Figure 9 A program operation method according to an embodiment of the present disclosure is described in detail.

[0117] Figure 9 is a waveform diagram for describing a method of operating a memory device according to an embodiment of the present disclosure.

[0118] For example, it can be Figure 1 and Figure 2 The memory device 100 performs Figure 9 For example, the memory device 100 may be Figure 2The control logic 130 includes a programming operation controller 131 to perform Figure 9 method.

[0119] exist Figure 9 , T0 to T4 represent programming steps included in a programming operation. The memory device 100 may perform a verification step after T4.

[0120] The program step may include a precharge period Precharge, a program period PGM, and a discharge period Discharge.

[0121] T0 to T2 may be a precharge period Precharge, T2 to T3 may be a programming period PGM, and T3 to T4 may be a discharge period Discharge.

[0122] exist Figure 9 In the embodiment, the memory device 100 is as shown in FIG. Figure 8 The program operation is performed sequentially in the reverse order from the word line adjacent to the drain select line to the word line adjacent to the source select line. Therefore, the memory cells connected to the unselected word lines located between the selected word line and the source select line may be memory cells for which the program operation is not performed. In addition, the memory cells connected to the unselected word lines located between the selected word line and the drain select line may be memory cells for which the program operation has already been performed.

[0123] exist Figure 9 In the embodiment of the present invention, the memory device 100 may include a first source select line connected to a source select transistor adjacent to the source line among the source select transistors. In this case, capacitive coupling may occur between the first source select line and the source line. Alternatively, the memory device 100 may include a second source select line connected to a source select transistor not adjacent to the source line among the source select transistors. Therefore, capacitive coupling may not occur between the second source select line and the source line.

[0124] From T0 to T1, the memory device 100 applies a precharge voltage Vpre to the source line SL. In an embodiment, the precharge voltage Vpre may be a voltage for pre-charging the source line SL or a selected line before applying the program voltage VPGM to reduce disturbances generated during a program operation.

[0125] In an embodiment, the memory device 100 may apply a ground voltage GND to a first source selection line UNSEL BLK_SSL1 while a precharge voltage Vpre is applied to the source line SL, wherein the first source selection line UNSEL BLK_SSL1 is connected to a source selection transistor adjacent to the source line among source selection transistors included in an unselected memory block among a plurality of memory blocks.

[0126] During a period T1 to T2, which is a reference time after the precharge voltage Vpre is applied to the source line SL, the memory device 100 may turn off the source line transistor connected to the source line SL. Thus, the memory device 100 may transition the source line SL, which has been precharged to the first voltage level, to a floating state by turning off the source line transistor connected to the source line SL. In an embodiment, the reference time may be the time required for the source line SL to be charged to a sufficient voltage by the precharge voltage Vpre applied to the source line SL. For example, the reference time may be the time required for the source line SL to be precharged to the first voltage level by the precharge voltage Vpre applied to the source line SL. Specifically, the reference time may be the time from T0 to T1.

[0127] In T1 to T2 , the memory device 100 applies a precharge voltage Vpre to a first source selection line UNSEL BLK_SSL1 connected to source selection transistors adjacent to the source line SL among source selection transistors included in an unselected memory block among a plurality of memories.

[0128] For example, during T1 to T2, the memory device 100 may apply a precharge voltage Vpre to the first source select line UNSEL BLK_SSL1, so that the source line SL is precharged to a second voltage level higher than the first voltage level. During T1 to T2, when the precharge voltage Vpre is applied to the first source select line UNSEL BLK_SSL1, the voltage level of the source line SL may increase due to a capacitive coupling phenomenon. In embodiments, the magnitude of the voltage level increased due to the capacitive coupling phenomenon may be determined based on a coupling ratio.

[0129] The memory device 100 may apply the precharge voltage Vpre to the first source selection line UNSEL BLK_SSL1 during T1 to T2 after a reference time has passed since the precharge voltage Vpre was applied to the source line SL. For example, the memory device 100 may apply the precharge voltage Vpre to the first source selection line UNSEL BLK_SSL1 that was in a ground state before T1 during T1 to T2 after a reference time has passed since the precharge voltage Vpre was applied to the source line SL.

[0130] Therefore, the memory device 100 can increase the voltage level charged in the source line SL through a capacitive coupling phenomenon by applying the precharge voltage Vpre to the first source select line UNSEL BLK_SSL1 adjacent to the source line SL after applying the precharge voltage Vpre to the source line SL. Therefore, the memory device 100 can reduce the disturbance generated during the programming operation.

[0131] During T0 to T2, the memory device 100 may apply a ground voltage GND to the word lines SEL BLK_SEL WL and SEL BLK_UNSEL WL connected to the memory cells included in the selected memory block among the plurality of memory blocks. For example, in the precharge period, the memory device 100 may apply a ground voltage GND to the word lines SEL BLK_SEL WL and SEL BLK_UNSEL WL connected to the memory cells included in the selected memory block.

[0132] In addition, during T0 to T2, the memory device 100 may apply a precharge voltage Vpre to a source select line SEL BLK_SSL connected to source select transistors included in a selected memory block among the plurality of memory blocks. For example, during the precharge period, the memory device 100 may apply a precharge voltage Vpre to the source select line SEL BLK_SSL connected to the source select transistors included in the selected memory block. During T0 to T2, in an embodiment, the precharge voltage Vpre may be applied to the source select line SEL BLK_SSL connected to the source select transistors included in the selected memory block, and a ground voltage GND may be applied to unselected source select lines (not shown) included in the selected memory block.

[0133] In addition, during T0 to T2, the memory device 100 may apply a ground voltage GND to a drain select line SEL BLK_DSL connected to the drain select transistors included in a selected memory block among the plurality of memory blocks. For example, during a precharge period, the memory device 100 may apply a ground voltage GND to the drain select line SEL BLK_DSL connected to the drain select transistors included in the selected memory block. Therefore, during the precharge period, the memory device 100 may apply a ground voltage GND to the drain select line SEL BLK_DSL connected to the drain select transistors included in the selected memory block, thereby precharging the channels of the memory cell strings using the voltage charged in the source line SL.

[0134] In addition, during T0 to T2, the memory device 100 may apply a ground voltage GND to a second source select line UNSEL BLK_SSL2 connected to source select transistors not adjacent to the source line SL among source select transistors included in unselected memory blocks among the plurality of memory blocks. For example, during a precharge period, the memory device 100 may apply a ground voltage GND to the second source select line UNSEL BLK_SSL2.

[0135] Therefore, the memory device 100 can block the connection between the source line SL and the memory cell strings included in the unselected memory block by applying the ground voltage GND to the second source select line UNSEL BLK_SSL2. In addition, the memory device 100 can freely control the precharge voltage Vpre applied to the first source select line UNSEL BLK_SSL1 by blocking the connection between the memory cell strings and the source line SL.

[0136] In T2 to T3 , the memory device 100 may provide a program voltage to the selected memory block.

[0137] For example, after precharging the source line SL to a second voltage level higher than the first voltage level by the precharge voltage Vpre applied to the first source select line UNSEL BLK_SSL1 , the memory device 100 may provide a program voltage to the selected memory block.

[0138] Specifically, during T2 to T3 after the precharge voltage Vpre is applied to the first source select line UNSEL BLK_SSL1, the memory device 100 may apply the program voltage VPGM to the selected word line SELBLK_SEL WL connected to the memory cells included in the selected memory block. Furthermore, during T2 to T3, the memory device 100 may apply a pass voltage Vpass having a level lower than the program voltage VPGM to the unselected word lines SEL BLK_UNSEL WL connected to the memory cells included in the selected memory block. Thus, the memory device 100 may cause the selected memory cells to have a threshold voltage corresponding to a programmed state.

[0139] In addition, during the period T2 to T3, the memory device 100 can apply a precharge voltage Vpre to the first source selection line UNSEL BLK_SSL1 connected to the source selection transistors adjacent to the source line SL among the source selection transistors included in the unselected memory, and apply a ground voltage GND to the second source selection line UNSEL BLK_SSL2 connected to the source selection transistors not adjacent to the source line SL among the source selection transistors included in the unselected memory block.

[0140] In addition, during T2 to T3, the memory device 100 may apply a ground voltage GND to a source selection line SEL BLK_SSL connected to a source selection transistor included in a selected memory block, and apply a drain selection voltage VDSL to a drain selection line SEL BLK_DSL connected to a drain selection transistor included in a selected memory block. Applying the ground voltage GND to the source selection line SEL BLK_SSL and applying the drain selection voltage VDSL to the drain selection line SEL BLK_DSL may be used to achieve the desired effect as described with reference to FIG. Figure 8 The program operations are sequentially performed in reverse order as described from a word line adjacent to the drain select line SEL BLK_DSL (eg, the eighth word line WL8 ) to a word line adjacent to the source select line SEL BLK_SSL (eg, the first word line WL1 ).

[0141] In T3 to T4 , the memory device 100 may provide a discharge voltage to the selected memory block.

[0142] For example, during T3 to T4 after the program voltage VPGM is supplied to the selected memory block, the memory device 100 may supply a discharge voltage to the selected memory block. In an embodiment, the discharge voltage may be a ground voltage GND for discharging word lines SEL BLK_SEL WL and SEL BLK_UNSEL WL connected to memory cells included in the selected memory block to 0V.

[0143] according to Figure 9 In accordance with an embodiment of the present disclosure, the memory device 100 may precharge the voltage of the source line SL in two steps during the precharge period of a programming step. Specifically, the memory device 100 may apply a precharge voltage Vpre to the source line SL and then apply a precharge voltage Vpre to the first source select line UNSEL BLK_SSL1 adjacent to the source line SL. Consequently, the source line SL may be precharged to a high voltage level through capacitive coupling between the source line SL and the first source select line UNSEL BLK_SSL1.

[0144] Figure 10 is used to describe Figure 2 The control logic included in the programming operation controller is a block diagram of the configuration.

[0145] exist Figure 10 In the embodiment, the memory device 100 may include a memory cell array 110, a row decoder 121, a voltage generator 122, and a program operation controller 1000. The memory cell array 110, the row decoder 121, and the voltage generator 122 may be respectively connected to a reference Figure 2The memory cell array 110, row decoder 121, and voltage generator 122 described above are configured and operated in the same manner. The program operation controller 1000 may instruct Figure 2 The programming operation controller 131.

[0146] Programming operation controller 1000 may be included in reference Figure 2 The control logic 130 is described.

[0147] Reference Figure 10 , the program operation controller 1000 may include a precharge voltage control signal generator 1010 , a source selection line controller 1030 , and a source line controller 1050 .

[0148] The precharge voltage control signal generator 1010 may generate a programming voltage control signal instructing to generate a plurality of voltages used in the programming step. For example, the precharge voltage control signal generator 1010 may generate a precharge voltage control signal OPSIG (precharge) for generating precharge-related voltages of various levels used in the precharge period, and may provide the generated precharge voltage control signal OPSIG (precharge) to the voltage generator 122. The voltage generator 122 generates various precharge-related voltages Vop used in the precharge period according to the precharge voltage control signal OPSIG (precharge), and may provide the generated precharge-related voltage Vop to the row decoder 121.

[0149] The source line controller 1050 may control a precharge voltage applied to a source line. Specifically, the source line controller 1050 may apply a precharge voltage SL (precharge) to a source line of the memory cell array 110 .

[0150] The source select line controller 1030 may control the voltage applied to the source select line. Specifically, the source select line controller 1030 may provide a source select line control signal SSL (precharge) for applying a precharge voltage to the source select line to the row decoder 121. The row decoder 121 may provide the precharge-related voltage Vop generated by the voltage generator 122 to the memory cell array 110 based on the source select line control signal SSL (precharge).

[0151] Figure 11 is used to describe Figure 1 Figure 1. Memory controller diagram.

[0152] Reference Figure 1 and Figure 11 , the memory controller 200 may include a processor 220 , a RAM 230 , an error correction circuit 240 , a ROM 260 , a host interface 270 , and a flash memory interface 280 .

[0153] The processor 220 may control the overall operation of the memory controller 200. The RAM 230 may be used as a buffer memory, a cache memory, an operating memory, etc. of the memory controller 200.

[0154] The ROM 260 may store various information necessary for the memory controller 200 to operate in the form of firmware.

[0155] The memory controller 200 may communicate with an external device (eg, the host 300 , an application processor, etc.) through the host interface 270 .

[0156] The memory controller 200 can communicate with the memory device 100 through the flash interface 280. The memory controller 200 can send commands CMD, addresses ADDR, control signals CTRL, etc. to the memory device 100 and receive data DATA through the flash interface 280. For example, the flash interface 280 can include a NAND interface.

[0157] Figure 12 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0158] Reference Figure 12 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0159] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control the read operation, write operation, erase operation, and background operation of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be connected to the memory device 2200. Figure 1 The memory controller 200 described in the embodiment of the present invention is identically implemented. The memory device 2200 can be implemented in the same manner as the memory controller 200 described in the embodiment of the present invention. Figure 2 The memory device 100 described is implemented identically.

[0160] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0161] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with the external device through at least one of the following communication standards: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined according to at least one of the above-mentioned various communication standards.

[0162] For example, the memory device 2200 may be composed of various nonvolatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque magnetic RAM (STT-MRAM).

[0163] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure memory cards such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MicroMMC, or eMMC), an SD card (SD, MiniSD, MicroSD, or SDHC), and a Universal Flash Storage (UFS).

[0164] Figure 13 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0165] Reference Figure 13 , SSD system 3000 includes a host 3100 and an SSD 3200. SSD 3200 exchanges signals SIG with host 3100 via signal connector 3001 and receives power PWR via power connector 3002. SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0166] According to an embodiment of the present disclosure, the SSD controller 3210 may execute a reference Figure 1 The functions of the memory controller 200 are described.

[0167] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined according to at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0168] The auxiliary power supply device 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply device 3230 can receive power PWR from the host 3100 and charge the power supply. When the power supply from the host 3100 is unstable, the auxiliary power supply device 3230 can provide power to the SSD 3200. For example, the auxiliary power supply device 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0169] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0170] Figure 14 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0171] Reference Figure 14 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0172] The application processor 4100 may drive components, an operating system (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, and the like that control components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0173] The memory module 4200 can be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (POP) and provided as one semiconductor package.

[0174] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0175] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can send the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented as a non-volatile semiconductor memory element such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 can be provided as a removable storage device (removable drive) such as a memory card of the user system 4000 and an external drive.

[0176] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with the reference Figure 1 The memory device 100 described in the foregoing description operates identically. The storage module 4400 may be used with reference to Figure 1 The described storage device 50 operates identically.

[0177] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or an interface for outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0178] CROSS-REFERENCE TO RELATED APPLICATIONS

[0179] This application claims priority from Korean Patent Application No. 10-2020-0082372, filed on Jul. 3, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A method of operating a memory device, the memory device comprising a plurality of memory blocks, each memory block comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected in series between a bit line and a source line, a plurality of source select transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain select transistors connected in series between the bit line and the plurality of memory cells, the method comprising the following steps: applying a precharge voltage to the source line; as well as The precharge voltage is applied to a first source select line to which source select transistors adjacent to the source line among source select transistors included in unselected memory blocks among the plurality of memory blocks are connected.

2. The method according to claim 1, wherein The step of applying the precharge voltage to the first source select line includes applying the precharge voltage to the first source select line after a reference time has elapsed from a time point when the precharge voltage is applied to the source line.

3. The method according to claim 2, wherein: The step of applying the precharge voltage to the first source selection line further includes the step of turning off a source line transistor connected to the source line after the reference time has elapsed.

4. The method according to claim 3, wherein: The step of applying the precharge voltage to the first source selection line further includes the step of applying a ground voltage to the first source selection line while applying the precharge voltage to the source line.

5. The method according to claim 4, wherein The step of applying the precharge voltage to the first source selection line further includes the step of applying the precharge voltage to the first source selection line in a ground state after the reference time has elapsed.

6. The method according to claim 5, further comprising the steps of: While the precharge voltage is applied to the source line and the first source select line, a ground voltage is applied to a second source select line connected to source select transistors not adjacent to the source line among the source select transistors included in the unselected memory block.

7. The method according to claim 1, further comprising the steps of: The precharge voltage is applied to a source selection line to which source selection transistors included in a selected memory block among the plurality of memory blocks are connected while the precharge voltage is applied to the source line and the first source selection line.

8. The method according to claim 7, further comprising the steps of: While the precharge voltage is applied to the source selection line to which the source selection transistors included in the selected memory block are connected, a ground voltage is applied to word lines connected to memory cells included in the selected memory block.

9. The method according to claim 8, further comprising the steps of: After applying the precharge voltage to the first source select line, a program voltage is applied to the selected memory block.

10. The method according to claim 9, further comprising the steps of: After the program voltage is supplied to the selected memory block, a discharge voltage is supplied to the selected memory block.

11. A memory device, comprising: a plurality of memory blocks, each memory block including a plurality of memory cell strings, each memory cell string including a plurality of memory cells connected in series between a bit line and a source line, a plurality of source select transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain select transistors connected in series between the bit line and the plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops, each program loop including a program step of supplying a program voltage to a selected memory block among the plurality of memory blocks and a verification step of verifying a program state of the selected memory block; as well as A programming operation controller configured to control the peripheral circuit to apply a precharge voltage to the source line in the programming step, and to apply the precharge voltage to a first source selection line connected to a source selection transistor adjacent to the source line among source selection transistors included in unselected memory blocks among the multiple memory blocks.

12. The memory device according to claim 11, wherein The program operation controller includes a program voltage control signal generator that generates a program voltage control signal instructing to generate a plurality of voltages used in the program step.

13. The memory device according to claim 12, wherein: The program operation controller further includes a source line controller that controls the precharge voltage applied to the source line.

14. The memory device according to claim 13, wherein: The program operation controller further includes a source selection line controller that controls a voltage applied to the source selection line connected to the plurality of source selection transistors.

15. A method of operating a memory device, the memory device comprising a plurality of memory blocks, each memory block comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected in series between a bit line and a source line, a plurality of source select transistors connected in series between the source line and the plurality of memory cells, and a plurality of drain select transistors connected in series between the bit line and the plurality of memory cells, the method comprising the steps of: applying a precharge voltage to the source line; as well as After the source line is precharged to a first voltage level, the precharge voltage is applied to a first source selection line connected to source selection transistors adjacent to the source line among source selection transistors included in unselected memory blocks among the plurality of memory blocks.

16. The method according to claim 15, wherein Applying the precharge voltage to the first source select line includes turning off a source line transistor connected to the source line after the source line is precharged to the first voltage level.

17. The method according to claim 16, wherein The step of applying the precharge voltage to the first source selection line further includes the step of applying a ground voltage to the first source selection line while applying the precharge voltage to the source line.

18. The method according to claim 17, wherein The step of applying the precharge voltage to the first source select line further includes the step of applying the precharge voltage to the first source select line in a ground state after the source line is precharged to the first voltage level.

19. The method according to claim 18, further comprising the steps of: While the precharge voltage is applied to the source line and the first source select line, a ground voltage is applied to a second source select line connected to source select transistors not adjacent to the source line among the source select transistors included in the unselected memory block.

20. The method according to claim 19, further comprising the steps of: After the source line is precharged to a second voltage level higher than the first voltage level, a program voltage is applied to a selected memory block among the plurality of memory blocks.

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