Memory bypass for error detection and correction

Abstract

This application relates to memory bypass for error detection and correction. A memory device can include error detection and correction circuitry for detecting and correcting errors in data read from a memory array of the memory device. To reduce read latency, the memory device can include bypass circuitry that enables it to transmit the data to the host device before or during error detection. If the memory device determines that the data is erroneous, the memory device can transmit a warning to the host device at the same time as or after transmitting the data. The memory device can perform error correction on the data and store corrected data in a register. Based on receiving the warning, the host device can issue one or more additional read commands to re-read the data from a memory bank or to read the corrected data from the register.

Description

[0001] Cross reference

[0002] The present application claims priority to U.S. Provisional Patent Application No. 63 / 046,876, titled “MEMORY BYPASS FOR ERROR DETECTION AND CORRECTION,” filed July 1, 2020, by Ballapuram et al., assigned to the assignee hereof and expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to memory bypass for error detection and correction. BACKGROUND

[0004] The following relates to one or more systems, and more specifically to memory bypass for error detection and correction.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically denoted by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To access information, a component can write or program a state in a memory device.

[0006] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, sulfide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory devices, such as FeRAM, can store their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0007] An apparatus is described. The apparatus can include a memory array, a control component coupled with the memory array and configured to cause the apparatus to receive a read command associated with reading data from the memory array from a host device, read the data from a bank of the memory array based on the read command, transmit the data to the host device based on reading the data, determine whether there is an error associated with reading the data, and based on determining that there is the error associated with reading the data, transmit a warning to the host device concurrently with transmitting the data to the host device.

[0008] An electronic device is described. The device can include a memory array, a first conductive path coupled with the memory array and configured to transmit data read from the memory array to a host device, an error detection component having an input coupled with the memory array and the first conductive path, the error detection component configured to receive the data read from the memory array, detect whether there is an error associated with the data read from the memory array, and generate a warning based on detecting that there is the error associated with the data, and a second conductive path coupled with the error detection component and configured to receive the warning from the error detection component and transmit the warning to the host device concurrently with the first conductive path transmitting the data to the host device.

[0009] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium can include instructions that, when executed by a processor of an electronic device, cause the electronic device to receive a read command associated with reading data from a memory array of the electronic device from a host device, read the data from a bank of the memory array based on the read command, transmit the data to the host device based on reading the data, determine whether there is an error associated with reading the data, and based on determining that there is the error associated with reading the data, transmit a warning to the host device concurrently with transmitting the data to the host device. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A diagram showing a system including a memory subsystem supporting memory bypass for error detection and correction in accordance with examples of this disclosure is presented.

[0011] Figure 2 An exemplary system or subsystem supporting memory bypass for error detection and correction in accordance with examples of this disclosure is illustrated.

[0012] Figure 3An exemplary system or subsystem that supports memory bypass for error detection and correction is illustrated in accordance with examples of this disclosure.

[0013] Figure 4 An exemplary timing diagram that supports memory bypass for error detection and correction is illustrated in accordance with examples of this disclosure.

[0014] Figure 5 An exemplary timing diagram that supports memory bypass for error detection and correction is illustrated in accordance with examples of this disclosure.

[0015] Figure 6 A block diagram of a memory device that supports memory bypass for error detection and correction is shown in accordance with examples of this disclosure.

[0016] Figure 7 A flow diagram illustrating one or more methods that support memory bypass for error detection and correction is shown in accordance with examples of this disclosure. DETAILED DESCRIPTION

[0017] Some memory devices can include on-die error detection and correction and other aspects for reducing a bit error rate associated with reading data from memory. For example, a memory device can include an error correction code (ECC) memory that has error detection and correction circuitry in a return data path to detect and correct data errors before the data is transmitted to, for example, a host device. This error detection and correction functionality can improve the bit error rate of the memory device but can add undesirable latency to read operations, including read operations for which data is determined to be free of any errors. That is, the latency associated with error detection and correction can be a fixed overhead incurred for every read operation, regardless of whether there are any errors. In some cases, the majority of the latency introduced by error detection and correction is incurred during the error correction process, not the error detection process.

[0018] As described herein, to reduce the latency associated with error detection and correction while maintaining a similar bit error rate, a memory device can include ECC bypass circuitry that enables the memory device to transmit data to a host device in parallel with performing error detection on the data, rather than waiting to send the data to the host device until the error detection and error correction are complete. If the error detection procedure determines that the data is erroneous, the memory device can transmit an indication (e.g., a warning) to the host device to inform the host that the data it received (or is currently receiving) is erroneous. The host device can then re-request the data from the memory device.

[0019] To implement this functionality, the memory device can read data from the memory array and provide the same data both to the data bus for transmission to the host device and to the error detection component to determine whether the data is in error. If the error detection component determines that the data is in error, the memory device can transmit an indication (e.g., a warning) to the host device to inform the host device that the data received by the host device is in error. Because the error detection process can be performed relatively quickly (e.g., with low latency), the memory device can be configured to transmit the indication (e.g., the warning) and the data at the same time (e.g., in parallel using different communication paths at least partially overlapping in time). Thus, the host device can receive the data and the warning (if present) at substantially the same time or at least partially overlapping in time.

[0020] If the error detection procedure determines that the data is in error, the memory device can perform an error correction procedure on the data to generate corrected data, and can store the corrected data in a register configured to store the corrected data. The host device can issue a read command to the memory device to read the corrected data from the register or to re-read the data from the memory array in response to receiving the indication (e.g., the warning) that the data it has received is in error. In some examples, the host device can use a different read command to read the corrected data from the register than was used to read the data from the memory array.

[0021] The techniques described herein can provide even more robust error detection and correction functionality while reducing read latency without significantly increasing the complexity of the memory controller. Moreover, because the existing paths through the error detection and correction circuitry can remain intact, the memory device can be configurable (e.g., via a mode register) to selectively disable ECC bypass such that the memory device performs error detection and correction on data before transmitting it to the host device. For example, disabling ECC bypass can be useful for applications in which the bit error rate is relatively high.

[0022] The features of the present disclosure are described first in the context of the Figures 1 to 3 described systems and subsystems. The features of the present disclosure are described in the context of the Figure 4 and 5 described timing diagrams. These and other features of the present disclosure are further illustrated by and described with reference to the apparatus diagrams and one or more flowcharts related to memory bypass for error detection and correction described with reference to Figure 6 and 7 The features of the present disclosure are described in the context of the apparatus diagrams and one or more flowcharts related to memory bypass for error detection and correction described with reference to

[0023] Figure 1Examples of a system 100 that supports memory bypass for error detection and correction in accordance with the examples disclosed herein are described. The system 100 can be included in an electronic device, such as a computer or a phone. The system 100 can include a host device 105 and a memory sub-system 110. The host device 105 can be a processor or a system on a chip (SoC) that interfaces with an interface controller 115 (e.g., a control component) and other components of an electronic device that includes the system 100. The memory sub-system 110 can store electronic information (e.g., digital information, data) for the host device 105 and provide access to the electronic information. The memory sub-system 110 can include the interface controller 115, a volatile memory 120, and a non-volatile memory 125. In some examples, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 can be included in the same physical package, such as a package 130. However, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 can be disposed on different respective dies (e.g., silicon dies).

[0024] Devices in the system 100 can be coupled through various conductive lines (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring) that can enable the transfer of information (e.g., commands, addresses, data) between devices. The conductive lines can make up channels, data buses, command buses, address buses, and the like.

[0025] The memory sub-system 110 can be configured to provide the benefits of the non-volatile memory 125 while maintaining compatibility with the host device 105 that supports protocols for different types of memory, such as the volatile memory 120 and other examples. For example, the non-volatile memory 125 can provide benefits such as non-volatility, higher capacity, or lower power consumption (e.g., relative to the volatile memory 120). However, the host device 105 can be incompatible with or ineffectively configured with various aspects of the non-volatile memory 125. For example, the host device 105 can support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory 125. To compensate for the incompatibilities between the host device 105 and the non-volatile memory 125, the memory sub-system 110 can be configured with the volatile memory 120, which can be compatible with the host device 105 and serve as a cache for the non-volatile memory 125. Thus, the host device 105 can use a protocol supported by the volatile memory 120 while benefiting from the advantages of the non-volatile memory 125.

[0026] In some examples, system 100 can be included in or coupled to a computing device, an electronic device, a mobile computing device, or a wireless device. The device can be a portable electronic device. For example, the device can be a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an Internet-connected device, or the like. In some examples, the device can be configured to communicate wirelessly with a base station or an access point. In some examples, a device associated with system 100 can be capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some examples, a device associated with system 100 can be referred to as user equipment (UE), a station (STA), a mobile terminal, or the like.

[0027] Host device 105 can be configured to interface with memory sub-system 110 using a first protocol supported by interface controller 115, such as low power double data rate (LPDDR). Thus, host device 105 can interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120 in some examples. In alternative examples, host device 105 can interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 can also interface with other components of an electronic device that includes system 100. Host device 105 can be or include a SoC, a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it can be a combination of these types of components. In some examples, host device 105 can be referred to as a host.

[0028] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Thus, interface controller 115 can facilitate transfer of data between various subcomponents, such as between host device 105, at least some of volatile memory 120, or non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol and can interface with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0029] The non-volatile memory 125 can be configured to store digital information (e.g., data) including for an electronic device of the system 100. Accordingly, the non-volatile memory 125 can include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some examples, the memory cells can be or include FeRAM cells (e.g., the non-volatile memory 125 can be FeRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a second protocol that is different than a first protocol used between the interface controller 115 and the host device 105. In some examples, the non-volatile memory 125 can have a longer latency for access operations than the volatile memory 120. For example, retrieving data from the non-volatile memory 125 can take more time than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 can take more time than writing data to the volatile memory 120. In some examples, the non-volatile memory 125 can have a smaller page size than the volatile memory 120, as described herein.

[0030] The volatile memory 120 can be configured to operate as a cache for one or more components (e.g., the non-volatile memory 125). For example, the volatile memory 120 can store information (e.g., data) including for an electronic device of the system 100. Accordingly, the volatile memory 120 can include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some examples, the memory cells can be or include DRAM cells (e.g., the volatile memory can be DRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a first protocol used between the interface controller 115 and the host device 105.

[0031] In some examples, the volatile memory 120 can have a shorter latency for access operations than the non-volatile memory 125. For example, retrieving data from the volatile memory 120 can take less time than retrieving data from the non-volatile memory 125. Similarly, writing data to the volatile memory 120 can take less time than writing data to the non-volatile memory 125. In some examples, the volatile memory 120 can have a larger page size than the non-volatile memory 125. For example, the page size of the volatile memory 120 can be 2 kilobytes (2 kB) and the page size of the non-volatile memory 125 can be 64 bytes (64B) or 128 bytes (128B).

[0032] Although the non-volatile memory 125 can be a higher density memory than the volatile memory 120, accessing the non-volatile memory 125 can take longer than accessing the volatile memory 120 (e.g., due to different architectures and protocols, among other reasons). Thus, operating the volatile memory 120 as a cache can reduce latency in the system 100. As an example, a data access request from the host device 105 can be relatively quickly satisfied by retrieving the data from the volatile memory 120 (rather than from the non-volatile memory 125). To facilitate operating the volatile memory 120 as a cache, the interface controller 115 can include a plurality of buffers 135. The buffers 135 can be disposed on the same die as the interface controller 115 and can be configured to temporarily store data during one or more access operations (e.g., store and retrieve operations) to transfer between the volatile memory 120, the non-volatile memory 125, or the host device 105 (or any combination thereof).

[0033] An access operation can also be referred to as an access process or an access procedure and can involve one or more sub-operations performed by one or more components of the memory sub-system 110. Examples of access operations can include store operations in which data provided by the host device 105 is stored (e.g., written) into the volatile memory 120 or the non-volatile memory 125 (or both) and retrieve operations in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and transferred back to the host device 105.

[0034] To store data in the memory sub-system 110, the host device 105 can initiate a store operation (or “store process”) by transmitting a store command (also referred to as a store request, a write command, or a write request) to the interface controller 115. The store command can target a set of non-volatile memory cells in the non-volatile memory 125. In some examples, a set of memory cells can also be referred to as a portion of memory. The host device 105 can also provide data to be written to the set of non-volatile memory cells to the interface controller 115. The interface controller 115 can temporarily store the data in the buffer 135-a. After storing the data in the buffer 135-a, the interface controller 115 can transfer the data from the buffer 135-a to the volatile memory 120 or the non-volatile memory 125, or both. In a write-through mode, the interface controller 115 can transfer the data to both the volatile memory 120 and the non-volatile memory 125. In a write-back mode, the interface controller 115 can only transfer the data to the volatile memory 120.

[0035] In either mode, the interface controller 115 can identify a set of appropriate one or more volatile memory cells in the volatile memory 120 to store data associated with a store command. To do so, the interface controller 115 can implement a set-associative mapping in which each set (e.g., block) of one or more non-volatile memory cells in the non-volatile memory 125 can be mapped to a plurality of sets of volatile memory cells in the volatile memory 120. For example, the interface controller 115 can implement an n-way associative mapping that allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in the volatile memory 120. Accordingly, the interface controller 115 can manage the volatile memory 120 as a cache of the non-volatile memory 125 by referencing the n sets of volatile memory cells associated with a set of target non-volatile memory cells. As used herein, a "set" of objects can refer to one or more of the objects, unless otherwise described or noted. Although described with reference to a set-associative mapping, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mappings (e.g., direct mappings or associative mappings, among other examples).

[0036] After determining which n sets of volatile memory cells are associated with a set of target non-volatile memory cells, the interface controller 115 can store data in one or more of the n sets of volatile memory cells. In this way, subsequent retrieval commands for data from the host device 105 can be efficiently satisfied by retrieving the data from the lower latency volatile memory 120 (rather than from the higher latency non-volatile memory 125). The interface controller 115 can determine which of the n sets of volatile memory 120 to use to store data based on one or more parameters associated with the data stored in the n sets of volatile memory 120 (e.g., a validity of the data, a usage age, or a modification status). Accordingly, data can be stored in the volatile memory 120 entirely (e.g., in write-back mode) or partially (e.g., in write-through mode) by the store commands of the host device 105. To track the data stored in the volatile memory 120, the interface controller 115 stores a tag address for one or more sets of volatile memory cells (e.g., for each set of volatile memory cells) that indicates the non-volatile memory cell having data stored in a given set of volatile memory cells.

[0037] To retrieve data from the memory sub-system 110, the host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller 115. The retrieval command can target a set of one or more non-volatile memory cells in the non-volatile memory 125. After receiving the retrieval command, the interface controller 115 can check the requested data in the volatile memory 120. For example, the interface controller 115 can check the requested data in the n set of volatile memory cells associated with the set of target non-volatile memory cells. If one of the n set of volatile memory cells stores the requested data (e.g., stores data for the set of target non-volatile memory cells), the interface controller 115 can transfer the data from the volatile memory 120 to the buffer 135-a (e.g., in response to determining that one of the n set of volatile memory cells stores the requested data) so that it can be transmitted to the host device 105. The term “hit” can be used to refer to a situation in which the volatile memory 120 stores data requested by the host device 105. If the n set of one or more volatile memory cells does not store the requested data (e.g., the n set of volatile memory cells stores data for a set of non-volatile memory cells other than the set of target non-volatile memory cells), the interface controller 115 can transfer the requested data from the non-volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n set of volatile memory cells does not store the requested data) so that it can be transmitted to the host device 105. The term “miss” can be used to refer to a situation in which the volatile memory 120 does not store data requested by the host device 105.

[0038] In a miss case, after transferring the requested data to buffer 135-a, interface controller 115 can transfer the requested data from buffer 135-a to volatile memory 120 so that subsequent read requests for the data can be satisfied by volatile memory 120 rather than non-volatile memory 125. For example, interface controller 115 can store the data in one of n sets of volatile memory cells associated with a set of target non-volatile memory cells. But the n sets of volatile memory cells can already store other sets of non-volatile memory cells. So, to preserve this other data, interface controller 115 can transfer the other data to buffer 135-b so that it can be transferred to non-volatile memory 125 for storage. This process can be referred to as "eviction," and the data transferred from volatile memory 120 to buffer 135-b can be referred to as "victim" data. In some cases, interface controller 115 can transfer a subset of the victim data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 can transfer one or more subsets of victim data that have changed since the data was originally stored in non-volatile memory 125. Data that is not consistent between volatile memory 120 and non-volatile memory 125 (e.g., due to updates in one memory and not the other) can be referred to in some cases as "modified" or "dirty" data. In some examples (e.g., when the interface controller operates in a mode such as write-back mode), dirty data can be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0039] In some examples, non-volatile memory 206, volatile memory 204, or both, can include error detection and correction circuitry in their data path back to the host device (e.g., prior to transmission on data bus 232 or data bus 238-a, respectively), so that data read from such memory is checked for errors and corrected if possible before the data is transmitted to the host device. To reduce read latency, as described herein, non-volatile memory 206, volatile memory 204, or both, can include features that support bypassing the error detection and correction circuitry so that data read from such memory is transmitted to the host device in parallel with checking the data for errors.

[0040] Figure 2 An example of a memory sub-system 200 that supports memory bypass for error detection and correction in accordance with examples disclosed herein is described. Memory sub-system 200 can be an example of memory sub-system 110 with reference to Figure 1 The example memory sub-system 110 described. Thus, memory sub-system 200 can be used in the example system 100 with reference to Figure 1The host device interactions described. Memory sub-system 200 can include interface controller 202, volatile memory 204, and non-volatile memory 206, which can be, respectively, the reference Figure 1 The examples of interface controller 115, volatile memory 120, and non-volatile memory 125 described. Thus, interface controller 202 can represent the host device interface with volatile memory 204 and non-volatile memory 206, as referenced Figure 1 described. For example, interface controller 202 can operate volatile memory 204 as a cache for non-volatile memory 206. Operating volatile memory 204 as a cache can allow the sub-system to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support a different protocol than non-volatile memory 206.

[0041] In Figure 2 In some cases, memory sub-system 200 is one of a plurality of similar or identical sub-systems that can be included in an electronic device. Each sub-system can be referred to as a slice and in some examples can be associated with a respective lane of a host device.

[0042] Non-volatile memory 206 can be configured to operate as main memory (e.g., memory for long-term data storage) for a host device. In some cases, non-volatile memory 206 can include one or more arrays of FeRAM cells. Each FeRAM cell can include a selection component and a ferroelectric capacitor, and can be accessed by applying an appropriate voltage to one or more access lines (e.g., word lines, plate lines, and digit lines). In some examples, a subset of FeRAM cells coupled with an activated word line can be sensed, e.g., concurrently / simultaneously, without sensing all FeRAM cells coupled with the activated word line. Thus, a page size of a FeRAM array can be different from (e.g., smaller than) a DRAM page size. In the context of a memory device, a page can refer to memory cells in a row (e.g., a group of memory cells having a common row address), and a page size can refer to a number of memory cells or column addresses in a row or a number of column addresses accessed during an access operation. Alternatively, a page size can refer to a size of data handled by various interfaces. In some cases, different memory device types can have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0043] Smaller page sizes of FeRAM arrays can provide various efficiency benefits as individual FeRAM cells can require more power to read or write than individual DRAM cells. For example, smaller page sizes of FeRAM arrays can facilitate efficient energy usage as a smaller number of FeRAM cells can be activated when an associated change in information is small. In some examples, the page size of a FeRAM cell array can change dynamically (e.g., during operation of the FeRAM cell array), for example, depending on the nature of data and commands that utilize FeRAM operations.

[0044] While individual FeRAM cells can require more power to read or write than individual DRAM cells, FeRAM cells can maintain their stored logic state for extended periods of time in the absence of an external power source as the ferroelectric material in FeRAM cells can maintain a non-zero electric polarization in the absence of an electric field. Thus, inclusion of a FeRAM array in non-volatile memory 206 can provide efficiency benefits over volatile memory cells (e.g., DRAM cells in volatile memory 204) as it can reduce or eliminate the need to perform refresh operations.

[0045] Volatile memory 204 can be configured to operate as a cache of non-volatile memory 206. In some cases, volatile memory 204 can include one or more arrays of DRAM cells. Each DRAM cell can include a capacitor comprising a dielectric material to store an electric charge representing a programmable state. The memory cells of volatile memory 204 can be logically grouped or arranged into one or more memory banks (referred to herein as “banks”). For example, volatile memory 204 can include sixteen banks. The memory cells of a bank can be arranged in a grid or array of intersecting columns and rows, and each memory cell can be accessed or refreshed by applying appropriate voltages to the digit line (e.g., column line) and word line (e.g., row line) of that memory cell. The rows of a bank can be referred to as pages, and a page size can refer to the number of columns or memory cells in a row. As noted, the page size of volatile memory 204 can be different (e.g., greater) than the page size of non-volatile memory 206.

[0046] The interface controller 202 can include various circuitry for interfacing (e.g., communicating) with other devices, such as a host device, volatile memory 204, and non-volatile memory 206. For example, the interface controller 202 can include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus port 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces can support the conveyance of information using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 can support information conveyed using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 can support information conveyed using a second protocol. Thus, the various bus interfaces coupled with the interface controller 202 can support different data quantities or data rates.

[0047] The data bus interface 208 can be coupled with the data bus 260, the transactional bus 222, and the buffer circuitry 224. The data bus interface 208 can be configured to transmit and receive data via the data bus 260 and to control information (e.g., acknowledgements / negative acknowledgements) or metadata via the transactional bus 222. The data bus interface 208 can also be configured to transfer data between the data bus 260 and the buffer circuitry 224. The data bus 260 and the transactional bus 222 can be coupled with the interface controller 202 and the host device such that conductive paths are established between the interface controller 202 and the host device. In some examples, the pins of the transactional bus 222 can be referred to as data mask inversion (DMI) pins. Although shown as having one data bus 260 and one transactional bus 222, there can be any number of data buses 260 and any number of transactional buses 222 coupled with the one or more data bus interfaces 208.

[0048] The C / A bus interface 210 can be coupled with the C / A bus 226 and the decoder 228. The C / A bus interface 210 can be configured to transmit and receive commands and addresses via the C / A bus 226. The commands and addresses received via the C / A bus 226 can be associated with data received or transmitted via the data bus 260. The C / A bus interface 210 can also be configured to transmit commands and addresses to the decoder 228 such that the decoder 228 can decode the commands and relay the decoded commands and associated addresses to the command circuitry 230.

[0049] The data bus interface 212 can be coupled with a data bus 232 and memory interface circuitry 234. The data bus interface 212 can be configured to transmit and receive data via the data bus 232, which can be coupled with the non-volatile memory 206. The data bus interface 212 can also be configured to transfer data between the data bus 232 and the memory interface circuitry 234. The C / A bus interface 214 can be coupled with a C / A bus 236 and the memory interface circuitry 234. The C / A bus interface 214 can be configured to receive commands and addresses from the memory interface circuitry 234 and relay the commands and addresses to the non-volatile memory 206 (e.g., to a local controller of the non-volatile memory 206) via the C / A bus 236. The commands and addresses transmitted via the C / A bus 236 can be associated with data received or transmitted via the data bus 232. The data bus 232 and the C / A bus 236 can be coupled with the interface controller 202 and the non-volatile memory 206 such that a conductive path is established between the interface controller 202 and the non-volatile memory 206.

[0050] The data bus interface 216 can be coupled with a data bus 238 and memory interface circuitry 240. The data bus interface 216 can be configured to transmit and receive data via the data bus 238, which can be coupled with the volatile memory 204. The data bus interface 216 can also be configured to transfer data between the data bus 238 and the memory interface circuitry 240. The C / A bus interface 264 can be coupled with a C / A bus 242 and the memory interface circuitry 240. The C / A bus interface 264 can be configured to receive commands and addresses from the memory interface circuitry 240 and relay the commands and addresses to the volatile memory 204 (e.g., to a local controller of the volatile memory 204) via the C / A bus 242. The commands and addresses transmitted via the C / A bus 242 can be associated with data received or transmitted via the data bus 238. The data bus 238 and the C / A bus 242 can be coupled with the interface controller 202 and the volatile memory 204 such that a conductive path is established between the interface controller 202 and the volatile memory 204.

[0051] In addition to the buses and bus interfaces for communicating with coupled devices, the interface controller 202 can include circuitry for operating the non-volatile memory 206 as main memory and the volatile memory 204 as cache. For example, the interface controller 202 can include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0052] Command circuitry 230 can be coupled with buffer circuitry 224, decoder 228, cache management circuitry 244, and scheduler 248, among other components. Command circuitry 230 can be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry 230 can include logic 262 that processes command information (e.g., from a host device) and storage information from other components (e.g., cache management circuitry 244, buffer circuitry 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry 230 can also be configured to transfer address information (e.g., address bits) to cache management circuitry 244. In some examples, logic 262 can be a circuit configured to operate as a finite state machine (FSM).

[0053] Buffer circuitry 224 can be coupled with data bus interface 208, command circuitry 230, memory interface circuitry 234, and memory interface circuitry 234. Buffer circuitry 224 can include a set of one or more buffer circuits for at least some of the memory banks (if not every memory bank) of volatile memory 204. Buffer circuitry 224 can also include components (e.g., a memory controller) for accessing the set of buffer circuits. In one example, volatile memory 204 can include sixteen memory banks, and buffer circuitry 224 can include sixteen sets of buffer circuits. Each set of buffer circuits can be configured to store data from or for (or both from and for) a respective memory bank of volatile memory 204. As an example, the set of buffer circuits for bank 0 (BK0) can be configured to store data from or for (or both from and for) the first memory bank of volatile memory 204, and the buffer circuits for bank 15 (BK15) can be configured to store data from or for (or both from and for) the sixteenth memory bank of volatile memory 204.

[0054] Each set of buffer circuitry in buffer circuitry 224 can include a pair of buffers. A pair of buffers can include one buffer configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device (e.g., an open page data (OPD) buffer) and another buffer configured to store data for an eviction process caused by the access command (e.g., a victim page data (VPD) buffer). For example, the buffer circuit set of BK0 can include buffer 218 and buffer 220, which can be examples of buffers 135-a and 135-b, respectively. Buffer 218 can be configured to store BK0 data targeted by an access command from a host device. And buffer 220 can be configured to store data transferred from BK0 as part of an eviction process triggered by the access command. Each buffer in a buffer circuit set can be configured with a size (e.g., a storage capacity) corresponding to a page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2 kB, then the size of each buffer can be 2 kB. Thus, in some examples, the size of a buffer can be equal to the page size of volatile memory 204.

[0055] Cache management circuitry 244 can be coupled with command circuitry 230, engine 246, and scheduler 248, among other components. Cache management circuitry 244 can include a set of cache management circuits for one or more banks (e.g., each bank) of volatile memory. As an example, cache management circuitry 244 can include sixteen sets of cache management circuits for BK0 through BK15. Each set of cache management circuits can include two memory arrays that can be configured to store storage information for volatile memory 204. As an example, the set of cache management circuits for BK0 can include memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM valid (CDT-V) array), which can be configured to store storage information for BK0. In some examples, a memory array can also be referred to as an array or a buffer. In some cases, a memory array can be or include volatile memory cells, such as SRAM cells.

[0056] The stored information can include content information, validity information, or dirtiness information (or any combination thereof) associated with the volatile memory 204. The content information (which can also be referred to as tag information or address information) can indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) for a set of one or more volatile memory cells can indicate which set of one or more non-volatile memory cells currently has the data stored in the set of one or more volatile memory cells. The validity information can indicate whether the data stored in a set of volatile memory cells is actual data (e.g., data having an expected order or form) or placeholder data (e.g., data that is random or dummy, not having an expected or significant order). And the dirtiness information can indicate whether the data stored in a set of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data stored in a set of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirtiness information can indicate whether the data stored in a set of volatile memory cells has been updated in response to the data stored in the non-volatile memory 206.

[0057] The memory array 252 can include memory cells that store the stored information (e.g., content and validity information) for the associated memory bank (e.g., BK0) of the volatile memory 204. The stored information can be stored on a per-page basis (e.g., there can be respective stored information for each page of the associated non-volatile memory bank). The interface controller 202 can check for the requested data in the volatile memory 204 by referencing the stored information in the memory array 252. For example, the interface controller 202 can receive a retrieval command from the host device for data in a set of non-volatile memory cells in the non-volatile memory 206. The interface controller 202 can reference the stored information in the memory array 252 using a set of one or more address bits (e.g., a set of row address bits) that are targeted for the access request. For example, using the set-associative mapping, the interface controller 202 can reference the content information in the memory array 252 to determine which set of volatile memory cells (if any) stores the requested data.

[0058] In addition to storing content information for volatile memory cells, memory array 252 can also store validity information indicating whether data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, volatile memory cells in volatile memory 204 can initially store random data and continue to do so until the volatile memory cells are written with data from a host device or non-volatile memory 206. To keep track of which data is valid, memory array 252 can be configured to set a bit for each set of volatile memory cells when actual data is stored in the set of volatile memory cells. This bit can be referred to as a validity bit or a validity flag. Like content information, validity information stored in memory array 252 can be stored on a per-page basis. Thus, in some examples, each validity bit can indicate data validity stored in an associated page.

[0059] Memory array 254 can also be similar to memory array 252 and can also include memory cells that store validity information for a bank (e.g., BK0) of volatile memory 204 associated with memory array 252. However, in contrast to memory array 252 storing validity information on a per-page basis, validity information stored in memory array 254 can be stored on a sub-block basis. For example, validity information stored in memory cells of memory array 254 can indicate data validity for a subset of volatile memory cells in a set (e.g., a page) of volatile memory cells. As an example, validity information in memory array 254 can indicate validity of each subset (e.g., 64B) of data stored in a page of data in BK0 of volatile memory 204. Storing content information and validity information in memory array 252 on a per-page basis can allow interface controller 202 to quickly and efficiently determine whether there is a hit or miss of data in volatile memory 204. Storing validity information on a sub-block basis can allow interface controller 202 to determine which subsets of data to save in non-volatile memory 206 during the eviction process.

[0060] Each cache management circuit set can also include a pair of respective registers coupled with command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, a memory array for that cache management circuit set, and other components. For example, a cache management circuit set can include a first register (e.g., register 256, which can be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirtiness information) from memory array 252 or scheduler 248-b, or both. The cache management circuit set can also include a second register (e.g., register 258, which can be a victim page tag (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a, or both. The information in register 256 and register 258 can be transferred to command circuitry 230 and engine 246 to enable these components to make decisions. For example, command circuitry 230 can issue a command to read non-volatile memory 206 or volatile memory 204 based on content information from register 256.

[0061] Engine 246-a can be coupled with register 256, register 258, and scheduler 248. Engine 246-a can be configured to receive storage information from the various components and issue commands to scheduler 248 based on the storage information. For example, when interface controller 202 is in a first mode (e.g., a write-through mode), engine 246-a can issue a command to scheduler 248-b and, in response, scheduler 248-b initiates or facilitates transfer of data from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode (e.g., a write-back mode), engine 246-a can issue a command to scheduler 248-b and, in response, scheduler 248-b can initiate or facilitate transfer of data from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent eviction process.

[0062] Engine 246-b can be coupled with registers 258 and scheduler 248-a. Engine 246-b can be configured to receive storage information from registers 258 and issue commands to scheduler 248-a based on the storage information. For example, engine 246-b can issue a command to scheduler 248-a to initiate or facilitate a transfer of dirty data from buffer 220 to non-volatile memory 206 (e.g., as part of an eviction process). If buffer 220 holds a set of data (e.g., victim data) transferred from volatile memory 204, engine 246-b can indicate which subset(s) of the set of data in buffer 220 (e.g., which 64B) should be transferred to non-volatile memory 206.

[0063] Scheduler 248-a can be coupled with various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. The commands issued by scheduler 248-a can be based on commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled with various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. The commands issued by scheduler 248-b can be based on commands from command circuitry 230 or engine 246-a, or both.

[0064] Memory interface circuitry 234 can communicate with non-volatile memory 206 via one or more of data bus interface 212 and C / A bus interface 214. For example, memory interface circuitry 234 can prompt C / A bus interface 214 to relay commands issued by memory interface circuitry 234 to a local controller in non-volatile memory 206 via C / A bus 236. And memory interface circuitry 234 can transfer data to or receive data from non-volatile memory 206 via data bus 232. In some examples, the commands issued by memory interface circuitry 234 can be supported by non-volatile memory 206 but not volatile memory 204 (e.g., the commands issued by memory interface circuitry 234 can be different than the commands issued by memory interface circuitry 240).

[0065] Memory interface circuitry 240 can communicate with volatile memory 204 via one or more of data bus interface 216 and C / A bus interface 264. For example, memory interface circuitry 240 can prompt C / A bus interface 264 to relay commands issued by memory interface circuitry 240 to a local controller of volatile memory 204 via C / A bus 242. And memory interface circuitry 240 can transmit data to or receive data from volatile memory 204 via one or more data buses 238. In some examples, commands issued by memory interface circuitry 240 can be supported by volatile memory 204 but not by non-volatile memory 206 (e.g., commands issued by memory interface circuitry 240 can be different than commands issued by memory interface circuitry 234).

[0066] Components of interface controller 202 can together operate non-volatile memory 206 as main memory and volatile memory 204 as a cache. This operation can be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from a host device.

[0067] In some examples, interface controller 202 can receive a store command from a host device. The store command can be received via C / A bus 226 and transferred to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command can include or be accompanied by address bits targeting a memory address of non-volatile memory 206. Data to be stored can be received via data bus 260 and transferred to buffer 218 via data bus interface 208. In a write-through mode, interface controller 202 can transfer data to both non-volatile memory 206 and volatile memory 204. In a write-back mode, interface controller 202 can transfer data only to volatile memory 204. In either mode, interface controller 202 can first check whether volatile memory 204 has memory cells available to store data. To do so, command circuitry 230 can reference memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets (e.g., n pages) of volatile memory cells associated with the memory address are empty (e.g., storing random or invalid data). In some cases, a set of volatile memory cells in volatile memory 204 can be referred to as a line or cache line.

[0068] If one of the n groups of associated volatile memory cells is available to store information, the interface controller 202 can transfer data from the buffer 218 to the volatile memory 204 for storage in that group of volatile memory cells. But if none of the groups of associated volatile memory cells is empty, the interface controller 202 can initiate an eviction process to make room for the data in the volatile memory 204. The eviction process can involve transferring old data (e.g., existing data) in the n groups of associated volatile memory cells to the buffer 220. Dirty information for the old data can also be transferred to the memory array 254 or the registers 258 for identification of a dirty subset of the old data. After the old data is stored in the buffer 220, the new data can be transferred from the buffer 218 to the volatile memory 204 and the old data can be transferred from the buffer 220 to the non-volatile memory 206. In some cases, a dirty subset of the old data is transferred to the non-volatile memory 206 and a clean subset (e.g., unmodified subset) is discarded. The dirty subset can be identified by the engine 204-b during the eviction process based on the dirty information transferred (e.g., from the volatile memory 204) to the memory array 254 or the registers 258.

[0069] In another example, the interface controller 202 can receive a retrieve command from the host device. The retrieve command can be received via the C / A bus 225 and transferred to the command circuitry 230 via one or more of the C / A bus interface 210 and the decoder 228. The retrieve command can include address bits targeting a memory address of the non-volatile memory 206. Before attempting to access the target memory address of the non-volatile memory 206, the interface controller 202 can check whether the volatile memory 204 stores data. To do so, the command circuitry 230 can reference the memory array 252 (e.g., using a group of memory address bits) to determine whether one or more of the n groups of volatile memory cells associated with the memory address stores the requested data. If the requested data is stored in the volatile memory 204, the interface controller 202 can transfer the requested data to the buffer 218 for transmission to the host device via the data bus 260.

[0070] If the requested data is not stored in volatile memory 204, interface controller 202 can retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Additionally, interface controller 202 can transfer the requested data from buffer 218 to volatile memory 204 so that the data can be accessed with lower latency during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 can first determine whether one or more of the n sets of associated volatile memory cells are available for storing the requested data. Interface controller 202 can determine the availability of the n sets of associated volatile memory cells by communicating with the associated cache management circuitry. If a set of associated volatile memory cells is available, interface controller 202 can transfer the data in buffer 218 to volatile memory 204 without performing an eviction process. Otherwise, interface controller 202 can transfer the data from buffer 218 to volatile memory 204 after performing an eviction process.

[0071] Memory sub-system 200 can be implemented in one or more configurations, including single-chip versions and multi-chip versions. Multi-chip versions can include one or more components of memory sub-system 200 on a chip separate from a chip that includes one or more other components of memory sub-system 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (as well as other components or combinations of components). For example, in one multi-chip version, respective separate chips can include each of interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, single-chip versions can include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0072] In some examples, volatile memory 204, non-volatile memory 206, or both, can include error detection and correction components configured to detect and correct errors in data read from a memory array of volatile memory 204 or non-volatile memory 206 before the data is transmitted to a host device. In some examples, each memory bank in volatile memory 204 or non-volatile memory 206 can include its own error detection and correction components. In some examples, volatile memory 204, non-volatile memory 206, or both, can include error detection and correction bypass circuitry (e.g., additional or alternative conductive paths) to enable data to be transmitted to a host device before it is error detected and corrected by the error detection and correction components, as described with reference to Figure 3 The error detection and correction bypass circuitry can reduce latency associated with read operations of volatile memory 204 and / or non-volatile memory 206.

[0073] Figure 3 Examples of a memory sub-system 300 that supports memory bypass for error detection and correction in accordance with the examples disclosed herein are described. The memory sub-system 300 can depict portions of the memory sub-systems 110, 200 described with reference to Figure 1 and 2 respectively. The memory sub-system 300 can include a memory array 305 and can be configured to read data from or write data to the memory array 305 based on commands received from a host device. In some examples, the memory array 305 can represent a portion of the volatile memory 204 (e.g., a bank or group of banks) or a portion of the non-volatile memory 206, as described with reference to Figure 2 for example.

[0074] The memory sub-system 300 can include an error detection component 310 and an error correction component 315. The error detection component 310 can be configured to perform an error detection procedure on data to detect errors in the data, and the error correction component 315 can be configured to perform an error correction procedure on the data to generate corrected data. In some examples, the error detection component 310 and the error correction component 315 can collectively implement single error correction, double error detection (SECDED) functionality or another type of error detection and correction.

[0075] The error detection component 310 and the error correction component 315 can be collectively referred to as error correction code (ECC) circuitry, as they can use block codes or convolutional codes to identify and correct errors in data. In some examples, each bank in the volatile memory 204 or the non-volatile memory 206 can be coupled with its own separate ECC circuitry (e.g., each bank can be associated with a separate error detection component 310 and error correction component 315). In various examples, one or more banks in the volatile memory 204 or the non-volatile memory 206 can be coupled with common ECC circuitry (e.g., the banks can be associated with one or more same error detection components 310 and error correction components 315). Some or all of the error detection components 310 and the error correction components 315 can be located within, for example, the non-volatile memory 206, the volatile memory 204, the interface controller 202, or any combination of these. In some examples, the error detection components 310 and the error correction components 315 can be implemented using some or all of the same circuitry or processing resources; that is, the error detection components 310 and the error correction components 315 can be implemented by the same logic circuitry.

[0076] Error detection component 310 and error correction component 315 can be included in a readback data path associated with memory array 305 (e.g., a communication path via which data read from memory array 305 is transmitted from memory array 305 to a host device). For example, error detection component 310 can be coupled with memory array 305 via conductive path 340 and can be configured to receive data read from memory array 305 and determine whether one or more errors are associated with the data read from memory array 305; e.g., determine whether the data is erroneous (e.g., is corrupted). In some instances, conductive path 340 can be configured to transmit up to 256 bits (32 bytes) in parallel.

[0077] Such data errors can be introduced when data is written to memory array 305 or when data is stored in memory array 305 or when data is read from memory array 305. Such data errors can be caused by, for example, electromagnetic interference, thermal degradation, or other undesirable phenomena. Moreover, in emerging memory systems, the introduction of new process technologies and manufacturing methods can result in increased sensitivity to process variations, which can result in a relatively low signal-to-noise ratio and correspondingly a higher bit error rate.

[0078] To avoid incurring latency associated with performing error detection and correction for each read operation prior to transmitting data to a host device, memory sub-system 300 can be configured to read data requested by a host device and transmit the data to the host device prior to or concurrently with performing error detection and correction. If memory sub-system 300 determines that the data is corrupted, memory sub-system can transmit an indication (which can otherwise be referred to as a warning) to the host device to notify the host device that the data it received (or is receiving) is corrupted.

[0079] For example, the error detection component 310 can be configured to determine whether there is an error associated with reading data from the host device and generate (e.g., produce, output) a warning in response to determining that there is an error associated with reading the data. In some examples, the error detection component 310 can be configured to generate the warning by generating a voltage signal whose value indicates whether there is an error, such as by outputting a first voltage to indicate an error and a second voltage to indicate that there is no error, for example, by generating a voltage pulse or one or more bits or bit stream or another type of warning signal or message. The memory sub-system 300 can be configured to transmit the warning generated by the error detection component 310 to the host device, such as using a conductive path 350 that can be coupled between the error detection component 310 and a pin 365 of the memory sub-system 300. The pin 365 can be configured to be coupled with the host device. In some examples, the pin 365 can be referred to as a data / mask invert (DMI) pin (e.g., a DMI pin specified in the LPDDR5 specification), which can be defined to indicate that data received from the memory sub-system 300 is inverted. That is, the memory sub-system 300 can reuse or share the DMI pin to transmit the warning to the host device, thereby potentially avoiding adding another pin for this purpose.

[0080] After determining that there is an error associated with reading data from the memory array 305, the error detection component 310 can provide the data read from the memory array 305 to the error correction component 315. The error correction component 315 can perform an error correction procedure to correct (or attempt to correct) the data received from the error detection component 310 to generate corrected data, and can store the corrected data in the ECC register 320. The ECC register 320 can be a 32-byte register, a 64-byte register, or a register of another size. In some examples, if the error detection component 310 determines that there is no error associated with reading the data, the error correction component 315 can store the data (e.g., read from the memory array 305) in the ECC register 320.

[0081] If the error detection component 310 determines that there is an error associated with the read data, the error detection component 310 can generate a warning, and the memory sub-system 300 can transmit the warning and the (error-ridden) data to the host device simultaneously, e.g., by transmitting the data using the conductive path 370 (which can be coupled with a data bus, such as the data bus 232, 238-a, or 238-b) and the warning in parallel with using the conductive path 350 and the pin 365. Thus, the host device can receive the warning simultaneously with receiving the error-ridden data (e.g., in parallel using different communication paths, at least partially overlapping in time). That is, the host device can receive the warning at the time the host device finishes receiving the data (e.g., before or at the time).

[0082] In some examples, the memory sub-system 300 can continue attempting to correct the data using the error correction component 315 and store the corrected data in the ECC register 320 after or in response to determining that there is an error associated with the read data.

[0083] The host device can transmit another read command to the memory sub-system to re-read the data from the memory array 305 in response to receiving the warning notifying the host device that the data it received is erroneous (e.g., by issuing a read command specifying the same memory address of the memory array 305 as the original read command). Additionally or alternatively, the host device can transmit a different read command to the memory sub-system to read the corrected data from the ECC register 320.

[0084] In some examples, the host device or the memory sub-system 300 can determine whether to re-read the data from the memory array 305 or read the corrected data from the ECC register 320 based on a size of the data, a size of the ECC register 320, or both.

[0085] For example, if the host device issues an initial read command specifying to read 64 bytes of data (e.g., the size of the data is 64 bytes), the memory sub-system 300 can read the data in two 32 byte portions in response to receiving the read command. That is, the memory sub-system can read a first 32 byte portion of the data, perform error detection and correction on the first portion of the data, and store the corrected data of the first portion of the data in the ECC register 320. Then, the memory sub-system can read a second 32 byte portion of the data, perform error detection and correction on the second portion of the data, and store the corrected data in the ECC register 320. If the size of the ECC register is 32 bytes, writing the corrected data of the second portion of the data to the ECC register overwrites the corrected data of the first portion of the data. In this case, if the host device receives a warning associated with the first 32 bit portion of the data, the memory sub-system 300 is unable to read the corrected data from the ECC register (as it has been overwritten by the second 32 bit portion) and instead must re-read the first portion of the data from the memory array 305.

[0086] In some examples, the host device can issue a second read command to re-read the data from the memory array or to read the corrected data from the ECC register. In some examples, the second read command indicates the location is within the memory array (e.g., by including a memory address) or the location is within the ECC register (e.g., by using a different read operation code or omitting the memory address or in some other way).

[0087] The memory sub-system 300 can determine the location from which to read the data based on receiving the second read command from the host device. The location can be a bank within the memory array (e.g., at the same location as the initial read command) or it can be within the ECC register (e.g., to read the corrected data from the ECC register). In some examples, the memory sub-system can read the data (or corrected data) from the memory array or from the ECC register based on determining the location.

[0088] In some examples, the memory sub-system can include a multiplexer 325 (e.g., switching circuitry or logic) for switching between transmitting data read from the memory array 305, which can be erroneous data, and corrected data read from the ECC register 320. That is, the memory sub-system 300 can determine, based on whether the memory sub-system 300 is receiving a first type of read command (e.g., a read command specifying a read operation to the memory array 305) or a second type of read command (e.g., a read command specifying a read operation to the ECC register 320), whether to use the multiplexer 325 to couple the conductive path 345 with the conductive path 370 or to couple the conductive path 360 with the conductive path 370. In some examples, the conductive path 345, the conductive path 360, and / or the conductive path 370 can be configured to transmit up to 32 bytes of data in parallel.

[0089] In some examples, it can be desirable to selectively disable the ECC bypass path described above and perform detection and correction on data read from the memory array 305 before transmitting the data to the host device. For example, in applications where the bit error rate is high or where the memory sub-system implements ECC logic on a per-bank group or per-channel basis, retry bandwidth (e.g., the bandwidth required to re-read data from the memory array 305 or the ECC register 320) can impact the overall bandwidth of the system. To mitigate this impact on bandwidth, the ECC bypass path can be implemented as an optional feature that can be enabled as a configuration setting via the mode register 335. For example, the mode register 335 can be set to a first configuration setting (e.g., by the host device or by the memory sub-system 300) to enable the ECC bypass path and a second configuration setting to disable the ECC bypass path. In some examples, the mode register 335 can be coupled with the multiplexer 325 and can be used to control which data is provided to the data bus for output to the host device. If the ECC bypass is disabled, for example, then the mode register 335 can cause the multiplexer to select the conductive path 355 to transmit corrected data output by the error correction component 315 rather than selecting the conductive path 345 to bypass ECC and output data directly before error detection and correction. In some examples, the memory sub-system 300 can determine a configuration setting and can determine whether to transmit a warning based on the configuration setting. For example, if the configuration setting indicates that the ECC bypass is disabled, then the memory sub-system 300 can refrain from transmitting a warning even if the memory sub-system detects an error in the data.

[0090] Reference is made to Figure 4 and 5 The timing of various operations of the memory sub-system 300 is described in more detail.

[0091] Figure 4An example of a timing diagram 400 supporting memory bypass for error detection and correction in accordance with the examples disclosed herein is illustrated. The timing diagram 400 can depict the timing of signals that can be generated, transmitted, or received by a memory device including the memory sub-system 110, the memory sub-system 200, and / or the memory sub-system 300 during a 64-byte data read operation when an error is detected in a second 32-byte portion of data.

[0092] The timing diagram 400 depicts the voltage or content of various signals over time, including a clock signal 405, a command signal 410, a data signal 415, and a data mask invert signal 420.

[0093] The clock signal 405 can be an oscillating signal that can be used by a memory device to synchronize the timing of various operations. The clock signal 405 can be generated by clock circuitry that can include an oscillator or by another type of circuitry.

[0094] The command signal 410 can be a signal that represents or conveys a memory access command (e.g., a read command) received by a host device. In some cases, a command received from a host device can include a memory bank number to be accessed and a command opcode that indicates a type of command (e.g., a first or second type of read command, a write command, an activate command, etc.). In some examples, the command signal 410 can be received by a memory device from a host device on a command and address bus (C / A bus), such as the C / A bus 226.

[0095] The data signal 415 can be a signal that represents or expresses data communicated between a memory device and a host device (e.g., data read from a memory bank or register of a memory device). In some cases, the data signal 415 can be transmitted on a data bus of a memory device, such as (for example) the data bus 232 or the data bus 238a. In some examples, the data bus can be a DQ bus of a memory device.

[0096] The data mask invert signal 420 can be a signal present at a pin of a memory device (e.g., a DMI pin) that is used to indicate whether the data of the data signal 415 is inverted (e.g., has an opposite polarity or order) and can also be used to indicate whether there is an error associated with reading data from a memory device. That is, the data mask invert signal 420 can represent a voltage at a pin of a memory that in turn can represent a warning generated by a memory device.

[0097] At time ti, the memory device can receive a first type of read command (RD16) from the host device. The first type of read command can indicate that the memory device read 64 bytes of data from the memory device's bank 0 (BK0) at an address of the memory device. The memory device can respond to receiving the first type of read command by performing two 32-byte read operations to read the requested 64 bytes of data, and can provide the two 32-byte data quantities to the memory controller in an order that can be specified by a value of column address bit 0, C0 (e.g., C0 = 1).

[0098] After reading the first 32 bytes of data, the memory device can determine (e.g., using an error detection component) that there is no error associated with reading the requested data of the first 32 bytes; that is, the data of the first 32 bytes is correct (e.g., free of errors, uncorrupted).

[0099] Between times t2 and t3, which can occur after a read latency tRL has elapsed from receiving the first type of read command, the memory device can transmit the requested data of the first 32 bytes to the host device. Because the memory device has determined that there is no error associated with reading the requested data of the first 32 bytes, the memory device can not generate a warning indicating an error (e.g., the memory device can refrain from generating a warning). That is, the voltage at the DMI pin between t2 and t3 can remain at the first value to indicate that there is no error in the data.

[0100] The memory device can read the second 32-byte portion of the requested data, and can determine (e.g., using an error detection component) that there is an error associated with reading the second 32-byte portion of the requested data.

[0101] Between times t4 and t5, the memory device can transmit the second 32 bytes of the requested data (e.g., the data with the error) on the data bus (e.g., on the DQ I / O bus) to the host device, and can generate a warning on the data mask inversion signal 420 by changing the voltage of the data mask inversion signal 420 to a second value (e.g., by driving a voltage pulse onto the DMI pin as a warning signal). The memory device can transmit the warning to the host device using the DMI pin simultaneously (e.g., in parallel) with transmitting the second 32 bytes of the requested data using the data bus.

[0102] In some examples, the memory device can transmit the warning and at least a portion of the data in parallel based on detecting a single rising or falling edge (e.g., falling edge 425) of the clock signal to synchronize the transmission of the warning with the data and to ensure that the warning reaches the host device before or at the same time as all of the data is received by the host device. Thus, in some examples, the host device can receive the warning at the same time as receiving at least a portion of the data of the second 32 bytes.

[0103] In response to receiving the warning, the host device can transmit a second type of read command (RDE) to the memory device to read the corrected data from the ECC register (e.g., ECC register 320). The second type of read command can be a command to read 32 bytes of data, and can include a second opcode different from the first type of read command, e.g., to cause the memory device to read the corrected data from the ECC register rather than re-read (original) data from the memory bank of the memory device. In some examples, for a 32 byte read, column address bit 0 (e.g., C0) can be used to specify the column address to be read (e.g., rather than specifying the order in which two 32 byte quantities of data can be returned to the memory controller, as for a 64 byte read command).

[0104] At time t6, the memory device can receive the second type of read command and can read the corrected data from the ECC register in response to receiving the second type of read command.

[0105] Between times t8 and t9, the memory device can transmit the corrected data to the host device (e.g., using one or more data buses, e.g., data buses 232, 238-a, 238-b, and / or 260). The memory device can not transmit a warning to the host device during this time period, as the memory device is transmitting the corrected data from the ECC register and can not perform error detection and correction on the data.

[0106] As previously discussed, the memory device can be able to process additional read commands to read corrected data from the ECC register interleaved with processing the second type of read command (RDE).

[0107] For example, at t7 (which can occur after a minimum column-to-column delay tCCD_S for accessing data from a memory bank in a different bank group), the memory device can receive a first type of read command (RD16) specifying a different memory bank (BK9) from which to read data. The memory device can read the data from the different memory bank in response to receiving the first type of read command and can begin transmitting the data to the host device at t9. Assuming that the error detection component determines that there are no errors associated with reading this data, the memory device can not transmit a warning associated with this data.

[0108] Figure 5 An example of a timing diagram 500 to support memory bypass for error detection and correction in accordance with the examples disclosed herein is illustrated. Timing diagram 500 can depict a case in which an error is detected in a first 32 byte portion of data for a 64 byte read operation, but not in a second 32 byte portion of data (as referenced Figure 4 An example of a timing diagram 500 to support memory bypass for error detection and correction in accordance with the examples disclosed herein is illustrated. Timing diagram 500 can depict a case in which an error is detected in a first 32 byte portion of data for a 64 byte read operation, but not in a second 32 byte portion of data (as referencedFigure 4 The same signal as described. In this case, the host device may not be able to... Figure 4 The reason why the corrected data is retrieved from the ECC register as shown in the example is because the second 32-byte portion of the requested data may have overwritten the contents of the ECC register.

[0109] As shown in timing diagram 400, timing diagram 500 depicts the voltage or content of various signals over time, including clock signal 505, command signal 510, data signal 515, and DMI signal 520, which can be compared with reference to... Figure 4 The corresponding signals described are the same or similar.

[0110] At time t1, the memory device may receive a first-type read command (RD16) from the host device. The first-type read command instructs the memory device to read 64 bytes of data from memory bank 0 (BK0) of the memory device at a specified address. The memory device may respond to receiving the first-type read command by performing two 32-byte read operations to read the requested 64 bytes of data.

[0111] After reading the first 32 bytes of data, the memory device may determine (e.g., using an error detection component) that an error associated with reading the first 32 bytes of requested data exists; that is, the first 32 bytes of data are corrupted. In response to determining the existence of an error associated with reading the first 32 bytes of requested data (e.g., the first 32 bytes are corrupted), the memory device may generate a warning indicating the error. The memory device may then transfer the erroneous data to an error correction component, which may correct (or attempt to correct) the data and store the corrected data in an ECC register (e.g., ECC register 320).

[0112] Between times t2 and t3, the memory device may transmit the first 32 bytes of requested data (e.g., erroneous data) to the host device on the data bus (e.g., on the DQ I / O bus), and may generate a warning on the DMI signal 520 by changing the voltage of the DMI signal 520 to a second value (e.g., by driving a voltage pulse onto the DMI pin as a warning signal). The memory device may transmit the warning signal to the host device using the DMI pin simultaneously with transmitting the first 32 bytes of requested data using the data bus. Therefore, in some instances, the host device may receive the warning simultaneously with receiving at least a portion of the second 32 bytes of data.

[0113] The memory device can continue to read a second 32-byte portion of the requested data, provide the second 32-byte portion of the requested data to the error detection component, and determine (e.g., using the error detection component) that there is no error associated with reading the second 32 bytes of the requested data. In response to determining that there is no error associated with reading the second 32 bytes of the requested data, the memory device can refrain from generating a warning, such as by maintaining the DMI signal 520 (e.g., the voltage at the DMI pin) at the first value. In some examples, the memory device can also provide the second 32-byte portion of data to the error correction component, which can store the second 32-byte portion of data in the ECC register without having to change (e.g., correct) the data (as the data was not corrupted), thereby overwriting the corrected data of the first 32-byte portion of data.

[0114] Between times t4 and t5, the memory device can transmit the second 32 bytes of the requested data to the host device (e.g., on the DQ I / O bus).

[0115] The host device can receive the first 32 bytes of data and the warning indicating that the first 32 bytes of data are in error, which can cause the host device to issue one or more read commands that attempt to re-read the first 32 bytes of data. However, because the error is in the first 32 bytes of a 64-byte read, the corrected data can not be available in the ECC register. In this case, the host device can issue a first read command (RD8) to re-read the 32 bytes of data in error from the memory array and a second type of read command (RDE) to read the 32 bytes of data that are corrected from the ECC register.

[0116] Thus, at time t5, the memory device can receive the first type of read command (RD8) from the host device, and in response, the memory device can re-read the first 32 bytes of data from the memory bank 0 (BK0) of the memory array. Again, the memory device can determine that there is an error associated with reading this 32 bytes of data, and can generate a warning.

[0117] Between times t7 and t9, the memory device can transmit the (error) data and the warning to the host device.

[0118] At time t8 (which can occur after a minimum column-to-column delay tCCD_L for accessing data from a memory bank in the same bank group), the memory device can receive the second type of read command (RDE) to read the corrected data from the ECC register. As Figure 5In some cases, the memory device can receive a second type of read command prior to completing the transmission of the erroneous data and the warning; i.e., the host device can issue the second type of read command prior to receiving the erroneous data and the warning transmitted in response to the first type of read command.

[0119] As previously discussed, the second type of read command (RDE) can include a second opcode that is different from the opcode of the first type of read command, e.g., to cause the memory device to read corrected data from the ECC register rather than re-reading (original) data from the memory bank of the memory device.

[0120] At time t10, in response to receiving the second type of read command from the host device, the memory device can read the corrected data from the ECC register and begin transmitting the corrected data to the host device.

[0121] Figure 6 A block diagram 600 of a memory device 605 that supports memory bypass for error detection and correction in accordance with the examples disclosed herein is shown. The memory device 605 can be a reference Figures 1 to 5 The memory device 605 can include a command component 610, a data transmission component 615, an error detection component 620, a warning transmission component 625, an error correction component 630, a corrected data storage component 635, a location determination component 640, a data read component 645, and a data write component 650. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0122] The command component 610 can receive a read command from a host device associated with reading data from a memory array. In some examples, the command component 610 can receive a second read command from the host device associated with reading data from the memory array after transmitting the data. In some cases, the second read command is a different command than the read command, and the second read command indicates that the location is within the register. In some examples, the command component 610 can receive a write command from the host device associated with writing first data to the memory array prior to receiving the read command.

[0123] The data transmission component 615 can transmit data to the host device based on the read data. In some examples, the data transmission component 615 can transmit second data to the host device. In some examples, transmitting the data to the host device includes transmitting the data to the host device on a first conductive path, and simultaneously transmitting the warning to the host device includes transmitting the warning to the host device by transmitting the warning to the host device on a second conductive path while transmitting the warning to the host device.

[0124] In some examples, the data transmission component 615 can identify a configuration setting prior to transmitting a warning to the host device, where transmitting the warning to the host device is based on identifying the configuration setting.

[0125] The error detection component 620 can determine whether there is an error associated with the read data. In some examples, the error detection component 620 can determine whether there is a second error associated with a re-read of the data based on re-reading the data from the bank of the memory array.

[0126] The warning transmission component 625 can transmit a warning to the host device concurrently with transmitting the data to the host device based on determining that there is an error associated with the read data. In some examples, the warning transmission component 625 can transmit a second warning to the host device concurrently with transmitting the second data based on determining that there is a second error associated with a re-read of the data.

[0127] The data read component 645 can read data from a bank of a memory array based on a read command. In some examples, the data read component 645 can read second data from a location based on determining the location.

[0128] The error correction component 630 can perform an error correction procedure on at least a portion of the data based on determining that there is an error associated with the read data and after transmitting the portion of the data to the host device to generate corrected data.

[0129] The corrected data storage component 635 can store the corrected data in a register.

[0130] The location determination component 640 can determine a location from which to read second data corresponding to the data based on a second read command. In some cases, the location is within the register, and reading the second data from the location includes reading the corrected data from the register. In some cases, the location is associated with the bank of the memory array, and reading the second data from the location includes reading the data from the bank of the memory array.

[0131] In some examples, the location determination component 640 can identify a size of the data based on receiving a second read command, where determining a location from which to read the data is based on the size of the data.

[0132] The data write component 650 can write first data to a memory array, where reading data includes reading a representation of the first data.

[0133] Figure 7A flow diagram illustrating one or more methods 700 that support memory bypass for error detection and correction in accordance with aspects of the present disclosure is shown. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by a memory device as described with reference to Figs. 1-6 by a command component 110 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0134] At 705, the memory device can receive a read command associated with reading data from the memory array from the host device. The operations of 705 can be performed according to the methods described herein. In some examples, aspects of the operations of 705 can be performed by a command component 110 as described with reference to Figs. 1-6 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0135] At 710, the memory device can read data from a bank of the memory array based on the read command. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by a data read component 120 as described with reference to Figs. 1-6 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0136] At 715, the memory device can transmit the data to the host device based on the read data. The operations of 715 can be performed according to the methods described herein. In some examples, aspects of the operations of 715 can be performed by a data transmission component 130 as described with reference to Figs. 1-6 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0137] At 720, the memory device can determine whether there is an error associated with the read data. The operations of 720 can be performed according to the methods described herein. In some examples, aspects of the operations of 720 can be performed by an error detection component 140 as described with reference to Figs. 1-6 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0138] At 725, the memory device can transmit a warning to the host device concurrently with transmitting the data to the host device based on determining that there is an error associated with the read data. The operations of 725 can be performed according to the methods described herein. In some examples, aspects of the operations of 725 can be performed by a warning transmission component 150 as described with reference to Figs. 1-6 executing instructions to control the functional elements of the memory device to perform the described functions. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0139] In some examples, the apparatuses described herein can perform one or more methods, such as the method 700. The apparatuses can include features, means, or instructions for receiving, from a host device, a read command associated with reading data from a memory array, reading the data from a bank of the memory array based on the read command, transmitting the data to the host device based on reading the data, determining whether there is an error associated with reading the data, and transmitting a warning to the host device based on determining that there is the error associated with reading the data, concurrent with transmitting the data to the host device.

[0140] Some examples of the method 700 and apparatuses described herein can further include operations, features, means, or instructions for determining that the error associated with reading the data can be present and performing an error correction procedure on the data to generate corrected data after transmitting at least a portion of the data to the host device, and storing the corrected data in a register.

[0141] Some examples of the method 700 and apparatuses described herein can further include operations, features, means, or instructions for receiving, from the host device after transmitting the data, a second read command associated with reading the data from the memory array, determining a location from which to read second data corresponding to the data based on the second read command, reading the second data from the location based on determining the location, and transmitting the second data to the host device.

[0142] In some examples of the method 700 and apparatuses described herein, the location can be within the register, and reading the second data from the location includes reading the corrected data from the register.

[0143] In some examples of the method 700 and apparatuses described herein, the second read command can be a different command than the read command, and the second read command indicates that the location can be within the register.

[0144] In some examples of the method 700 and apparatuses described herein, the location can be associated with the bank of the memory array, and reading the second data from the location includes reading the data from the bank of the memory array.

[0145] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for determining, based on re-reading the data from the bank of the memory array, whether a second error associated with the re-reading of the data can be present, and transmitting, to the host device, a second warning concurrently with transmitting the second data based on determining that the second error associated with the re-reading of the data can be present.

[0146] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for identifying a size of the data based on receiving the second read command, wherein determining the location from which to read the data can be based on the size of the data.

[0147] In some examples of the method 700 and the apparatus described herein, transmitting the data to the host device can include operations, features, means, or instructions for transmitting the data to the host device on a first conductive path, and wherein transmitting the warning to the host device is concurrently.

[0148] In some examples of the method 700 and the apparatus described herein, the register can be coupled with the first conductive path.

[0149] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for identifying a configuration setting prior to transmitting the warning to the host device, wherein transmitting the warning to the host device can be based on identifying the configuration setting.

[0150] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for receiving, from the host device prior to receiving the read command, a write command associated with writing first data to the memory array, and writing first data to the memory array, wherein reading the data includes reading a representation of the first data.

[0151] It should be noted that the methods described herein are possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0152] An apparatus is described. The apparatus can include a memory array, a first conductive path coupled with the memory array and configured to transfer data read from the memory array to a host device, an error detection component having an input coupled with the memory array and the first conductive path, the error detection component configured to receive the data read from the memory array, detect whether an error associated with the data read from the memory array is present, and generate a warning based on detecting that the error associated with the data is present, and a second conductive path coupled with the error detection component and configured to receive the warning from the error detection component and transfer the warning to the host device in parallel with the first conductive path transferring the data to the host device.

[0153] In some examples, the apparatus can further include an error correction component coupled with the error detection component and configured to correct at least one error in the data to generate corrected data, and a register coupled with the error correction component and configured to store the corrected data.

[0154] In some examples, the register can be coupled with the first conductive path for transferring the corrected data to the host device. In some examples, the first conductive path can comprise a 32-bit data bus configured to transfer at least a portion of the data to the host device. In some examples, the second conductive path can be coupled with a pin of the memory array and can be configured to provide the warning to the host device using the pin. In some examples, the pin can comprise a data mask / inversion (DMI) pin.

[0155] In some examples, the apparatus can further include clock circuitry configured to generate a clock signal for the memory array to synchronize operations of the memory array, where the memory array is configured to transfer the data and the warning in parallel based at least in part on detecting a single edge of the clock signal. In some examples, the first conductive path can be coupled with a first bank of the memory array.

[0156] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields, or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by one of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0157] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which the signal flow between the components is supported. Components are in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support signal flow between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) at any given time can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, signal flow between connected components can be interrupted at a time, for example, using one or more intermediate components such as switches or transistors.

[0158] The term "coupled" refers to a state of moving from an open circuit relationship between components in which signal cannot presently pass between the components through a conductive path to a closed circuit relationship between the components in which signal can pass between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signal to flow between the other components through a conductive path in which signal flow was not previously permitted.

[0159] The term "isolated" refers to a relationship between components in which signal cannot presently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components that are separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller implements a change that prevents signal from flowing between the components using a conductive path in which signal flow was previously permitted.

[0160] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) need not be absolute but is close enough to the intended characteristic to achieve the desired result.

[0161] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during initial formation or growth of the substrate.

[0162] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive material, such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerated) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor can be "turned off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0163] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "superior." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0164] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label in combination with a second reference label that distinguishes among different instances of that component. For example, a first instance of a component might be referred to as 102, and a second instance of that same type of component might be referred to as 102'. As will be appreciated, the use of the first reference label alone as a reference to a component can refer to any or all of the identical component in the various instances and / or designs of the component that are included within the scope of the description. Also, a lone reference label without a direct preceding colon can indicate that the reference label is used for identifying the component in any instance thereof driven with the reference label.

[0165] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields, or particles, or any combination thereof.

[0166] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0167] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, including in the claims, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0168] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0169] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not limited to the examples described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory array; and A control component, coupled to and configured to cause the device to: Receive a read command associated with reading data from the memory array from the host device; The data is read from the memory bank of the memory array, at least in part, based on the read command; Simultaneously with transmitting the first portion of the data to the host device, an indication of the error status of the first portion of the data is transmitted. and After transmitting the indication of the error status and the first portion of the data, and simultaneously transmitting the second portion of the data to the host device, a warning that an error exists associated with reading the second portion of the data is transmitted to the host device.

2. The device of claim 1, wherein the control component is further configured such that the device: At least in part based on determining the existence of the error associated with reading the second portion of the data and, after transmitting the second portion of the data to the host device, performing an error correction procedure on the second portion of the data to produce corrected data; and The corrected data is stored in a register.

3. The device of claim 2, wherein the control component is further configured such that the device: After transmitting the second portion of the data, a second read command associated with reading the second portion of the data from the memory array is received from the host device; The location from which to read second data corresponding to the second portion of the data is determined is at least in part based on the second read command; The second data is read from the location at least in part based on determining the location; and The second data is transmitted to the host device.

4. The device of claim 3, wherein the location is in the register, and reading the second data from the location includes reading the corrected data from the register.

5. The device of claim 4, wherein the second read command is a different command from the read command, and the second read command indicates the location within the register.

6. The device of claim 3, wherein the location is associated with the memory bank of the memory array, and reading the second data from the location includes reading the data from the memory bank of the memory array.

7. The device of claim 6, wherein the control component is further configured such that the device: The existence of a second error associated with the rereading of the second portion of the data is determined at least in part based on the second portion of the data being reread from the memory bank of the memory array; and At least in part based on the determination that a second error is associated with the rereading of the second portion of the data, a second warning is transmitted to the host device simultaneously with the transmission of the second data.

8. The device of claim 3, wherein the control component is further configured such that the device: The size of the second portion of the data is identified at least in part based on the receipt of the second read command, wherein determining the location from which the data is read is at least in part based on the size of the second portion of the data.

9. The device of claim 2, wherein the control component is configured such that the device transmits the second portion of the data to the host device via a first conductive path, and wherein the control component is configured such that the device transmits the warning to the host device simultaneously via a second conductive path.

10. The device of claim 9, wherein the register is coupled to the first conductive path.

11. The device of claim 1, wherein the control component is further configured such that the device: Before transmitting the warning to the host device, configuration settings are identified, wherein transmitting the warning to the host device is at least in part based on identifying the configuration settings.

12. The device of claim 1, wherein the control component is further configured such that the device: Receive a write command associated with writing first data to the memory array from the host device before receiving the read command; and The first data is written to the memory array, wherein reading the data includes reading a representation of the first data.

13. An electronic device comprising: Memory array; A first conductive path, coupled to the memory array and configured to transmit data read from the memory array to a host device; An error detection component having an input coupled to the memory array and the first conductive path, the error detection component being configured to: Receive the data read from the memory array. Detect whether there are any errors associated with the data read from the memory array, and A warning is generated based on the detection of the error associated with the data; An error correction component coupled to the input of the error detection component and the register, the error correction component being configured to correct at least one error in the data to generate corrected data and transmit the corrected data to the register; and A second conductive path, coupled to the error detection component and configured to receive the warning from the error detection component and transmit the warning to the host device in parallel with the first conductive path, transmits the data to the host device.

14. The electronic device of claim 13, further comprising: The register is coupled to the error correction component and configured to store the corrected data.

15. The electronic device of claim 14, wherein the register is coupled to the first conductive path for transmitting the calibrated data to the host device.

16. The electronic device of claim 13, wherein the first conductive path includes a 32-bit data bus configured to transmit at least a portion of the data to the host device.

17. The electronic device of claim 13, wherein the second conductive path is coupled to a pin of the memory array and configured to use the pin to provide the warning to the host device.

18. The electronic device of claim 17, wherein the pin includes a data mask / invert DMI pin.

19. The electronic device according to claim 13, further comprising: A clock circuit system configured to generate a clock signal for the memory array to synchronize the operation of the memory array, wherein the memory array is configured to transmit the data and the warning in parallel, at least in part based on a single edge that detects the clock signal.

20. The electronic device of claim 13, wherein the first conductive path is coupled to a first storage cell of the memory array.

21. A non-transitory computer-readable medium storing code, said code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following: Receive a read command associated with reading data from the memory array of the electronic device from the host device; The data is read from the memory bank of the memory array, at least in part, based on the read command; Simultaneously with transmitting the first portion of the data to the host device, an indication of the error status of the first portion of the data is transmitted. and Simultaneously with transmitting the second portion of the data to the host device, a warning of an error associated with reading the second portion of the data is transmitted to the host device.

22. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part based on determining the existence of the error associated with reading the second portion of the data and, after transmitting the second portion of the data to the host device, performing an error correction procedure on the second portion of the data to produce corrected data; and The corrected data is stored in the registers of the memory array.

23. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After transmitting the second portion of the data, a second read command associated with reading the second portion of the data from the memory array is received from the host device; The location in the memory array from which the second data corresponding to the second portion of the data is read is determined, at least in part, based on the second read command; The second data is read from the location at least in part based on determining the location; and The second data is transmitted to the host device.

24. The non-transitory computer-readable medium of claim 23, wherein the location is within the register of the memory array, and reading the second data from the location includes reading the corrected data from the register.

25. The non-transitory computer-readable medium of claim 24, wherein the second read command is a command different from the read command, and the second read command indicates the location within the register of the memory array.

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