Nanometer structure field effect transistor device and method of forming the same

Abstract

The present disclosure relates to nanostructure field effect transistor devices and methods of forming the same. A method of forming a semiconductor device includes forming a first nanostructure over a first fin protruding above a substrate in a first device region of the semiconductor device; forming a second nanostructure over a second fin protruding above the substrate in a second device region of the semiconductor device, wherein the first and second nanostructures comprise a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first nanostructure and around the second nanostructure; forming a first hardmask layer around the first nanostructure in the first device region and around the second nanostructure in the second device region; after forming the first hardmask layer, removing the first hardmask layer from the second device region; after removing the first hardmask layer, increasing a first thickness of the dielectric material around the second nanostructure by performing an oxidation process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to nanostructure field effect transistor devices and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the features formed in integrated circuit devices. However, as the dimensions of features become smaller, other problems arise. SUMMARY

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming a first nanostructure over a first fin in a first device region of the semiconductor device, the first fin protruding above a substrate; forming a second nanostructure over a second fin in a second device region of the semiconductor device, the second fin protruding above a substrate, wherein the first and second nanostructures comprise a semiconductor material and extend parallel to a major upper surface of the substrate; forming a dielectric material around the first nanostructure and around the second nanostructure; forming a first hardmask layer around the first nanostructure in the first device region and around the second nanostructure in the second device region; removing the first hardmask layer from the second device region after forming the first hardmask layer; and increasing a first thickness of the dielectric material around the second nanostructure by performing an oxidation process after removing the first hardmask layer from the second device region.

[0005] According to another embodiment of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming a first nanostructure over a first fin and a second nanostructure over a second fin, wherein the first fin and the second fin protrude above a substrate, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; forming an interfacial dielectric material around the first nanostructure and around the second nanostructure; forming a first hard mask layer over the first fin but not over the second fin, wherein the first hard mask layer covers the interfacial dielectric material around the first nanostructure, wherein the interfacial dielectric material around the second nanostructure is exposed by the first hard mask layer; after forming the first hard mask layer, performing an oxidation process, wherein a thickness of the interfacial dielectric material around the second nanostructure increases after the oxidation process; and after performing the oxidation process, removing the first hard mask layer.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first fin and a second fin protruding above a substrate; a first nanostructure and a second nanostructure over the first fin and the second fin, respectively, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; a first interfacial dielectric layer around the first nanostructure and a second interfacial dielectric layer around the second nanostructure, wherein the second interfacial dielectric layer around the second nanostructure is thicker than the first interfacial dielectric layer around the first nanostructure; a gate dielectric layer on the first interfacial dielectric layer around the first nanostructure and on the second interfacial dielectric layer around the second nanostructure; and a gate electrode around the first nanostructure and around the second nanostructure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. FIG. 1 illustrates an example of a semiconductor device according to some embodiments.

[0008] Figure 1 An example of a nanosheet field effect transistor (NSFET) device in a three-dimensional view is shown according to some embodiments.

[0009] Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B are cross-sectional views of a nanowire field effect transistor device at various fabrication stages according to embodiments.

[0010] Figure 19A and Figure 19B are cross-sectional views of a nanowire field effect transistor device at fabrication stages according to embodiments.

[0011] Figure 20 is a flowchart of a method of forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific examples are described in the following description to provide a thorough description of embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature is formed in direct contact with the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and second feature can not be in direct contact.

[0013] Furthermore, spatially relative terms (for example, "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] According to some embodiments, a method of forming a semiconductor device includes forming a first nanostmcture (e.g., nanosheet or nanowire) over a first fin that protrudes above a substrate in a first device region of the semiconductor device; forming a second nanostmcture over a second fin that protrudes above the substrate in a second device region of the semiconductor device, wherein the first and second nanostmctures comprise a first semiconductor material and extend parallel to a major upper surface of the substrate. The method further includes forming an interface layer (e.g., gate oxide layer) around the first nanostmcture and around the second nanostmcture; forming a patterned hard mask layer in the first device region but not in the second device region; and performing an oxidation process to increase a first thickness of the interface layer in the second device region. Because the patterned hard mask layer shields the first device region from the oxidation process, a second thickness of the interface layer in the first device region is unchanged by the oxidation process or is increased by a lesser amount as compared to the first thickness of the interface layer in the second device region. The disclosed embodiments allow for forming gate oxide layers having different thicknesses in different device regions (e.g., logic device regions and I / O device regions) to achieve different performance goals, such as leakage current and power consumption.

[0015] Figure 1 An example of a nanostmcture field effect transistor (NSFET) device in a three-dimensional view is shown according to some embodiments. The NSFET device includes semiconductor fin structures (also referred to as fin structures) that protrude above a substrate 50, where each semiconductor fin structure includes a semiconductor fin 90 (also referred to as a fin) and a nanostmcture 54 overlying the semiconductor fin 90. A gate electrode 130 (e.g., metal gate) is disposed over the fin structures, and source / drain regions 112 are formed on opposite sides of the gate electrode 130. The nanostmctures 54 are disposed over the semiconductor fins 90 and between the source / drain regions 112. Isolation regions 96 are formed on opposite sides of the fin structures. A gate dielectric layer 122 is formed around the nanostmctures 54. The gate electrode 130 is over and around the gate dielectric layer 122.

[0016] Figure 1Reference cross-sections used in subsequent figures are also shown. Cross-section A-A is along the longitudinal axis of the gate electrode 130, and in a direction perpendicular to, for example, the direction of current flow between the source / drain regions 112 of the NSFET device. Cross-section B-B is perpendicular to cross-section A-A, and along the longitudinal axis of the semiconductor fin 90, and in a direction parallel to, for example, the direction of current flow between the source / drain regions 112 of the NSFET device. Cross-section C-C is parallel to cross-section B-B, and between two adjacent fin structures. Cross-section D-D is parallel to cross-section A-A, and extends through the source / drain regions 112 of the NSFET device. For clarity, subsequent figures refer to these reference cross-sections.

[0017] Figure 2 Figure 3A Figure 3B Figure 4A Figure 4B Figures 5A-5C Figures 6A-6C Figures 7A-7C Figure 8A Figure 8B Figure 9A Figure 9B Figure 10A Figure 10B Figure 11A Figure 11B Figure 12A Figure 12B Figure 13A Figure 13B Figure 14A Figure 14B Figure 15A Figure 15B Figure 16A Figure 16B Figure 17A Figure 17B Figure 18A and Figure 18B are cross-sectional views of a nanostructure field effect transistor (NSFET) device 100 at various fabrication stages, according to embodiments.

[0018] In Figure 2 ​​​​​​​​​​​​​​​​​​​​​​​​​​​​In some embodiments, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, e.g., a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, e.g., a multilayer substrate or a graded substrate. In some embodiments, the semiconductor material of the substrate 50 includes silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0019] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. In Figure 2 In particular embodiments, the layers formed of the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, and 54C. Figure 2 The number of layers shown formed of the first semiconductor material and the second semiconductor material are merely non-limiting examples. Other numbers of layers are also possible, and are fully intended to be included within the scope of the present disclosure.

[0020] In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming a channel region of a p-type FET, e.g., silicon germanium (Si x Ge 1-x where x is in the range of 0 to 1), and the second semiconductor material 54 is an epitaxial material suitable for forming a channel region of an n-type FET, e.g., silicon. In subsequent processing, the multilayer stack 64 (which can also be referred to as an epitaxial material stack) will be patterned to form the channel region of the NSFET. In particular, the multilayer stack 64 will be patterned and etched to form horizontal nanostmctures (e.g., nanosheets or nanowires), the resulting channel region of the NSFET including a plurality of horizontal nanostmctures.

[0021] A multilayer stack 64 can be formed by an epitaxial growth process, which can be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber is periodically exposed to a first set of precursors for selectively growing a first semiconductor material 52, and then exposed to a second set of precursors for selectively growing a second semiconductor material 54. The first set of precursors includes precursors for the first semiconductor material (e.g., silicon-germanium), and the second set of precursors includes precursors for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second set of precursors includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously flowing silicon precursors into the growth chamber and then periodically: (1) flowing germanium precursors into the growth chamber while growing the first semiconductor material 52; and (2) prohibiting the flow of germanium precursors into the growth chamber while growing the second semiconductor material 54. The periodic exposure can be repeated until a target number of layers are formed.

[0022] like Figure 2 As shown, substrate 50 has a first portion in a first device region 200 of NSFET device 100 and a second portion in a second device region 300 of NSFET device 100. In some embodiments, semiconductor devices (e.g., transistors) formed in the first device region 200 and the second device region 300 have the same type (e.g., p-type or n-type device), but the gate oxides of the transistors have different thicknesses to achieve different performance specifications. For example, the first device region 200 may be a logic device region, and the second device region 300 may be an input / output (I / O) device region, wherein the devices (e.g., transistors) formed in the I / O device region have a thicker gate oxide 120 (see example...). Figure 17B This results in lower leakage current (compared to devices formed in the logic device regions). As another example, both the first device region 200 and the second device region 300 are used to form logic devices, but the logic devices formed in the second device region 300 have a thicker gate oxide 120 to achieve lower leakage current and lower power consumption. This disclosure discloses various methods for modulating (e.g., changing) the thickness of the gate oxide in different device regions (e.g., 200 and 300) of the NSFET device 100.

[0023] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A and Figure 18B are cross-sectional views of the NSFET device 100 at subsequent fabrication stages according to embodiments. Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A and Figure 18A are cross-sectional views along cross-section B-B in Figure 1 . Figure 3B 、 Figure 4B 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B and Figure 18B are cross-sectional views along cross-section A-A in Figure 1 . Figure 5B 、 Figure 6B and Figure 7B are cross-sectional views along cross-section D-D in Figure 1 . The number of fins and the number of gate structures shown in the figures are non-limiting examples, and it is understood that other numbers of fins and other numbers of gate structures can also be formed. Throughout the discussion herein, figures having the same numbers but different letters are of the same item (e.g., Figure 10A and Figure 10B) show cross-sectional views of the NSFET device at the same processing stage but along different cross-sections.

[0024] Note that, for simplicity, in some subsequent figures, cross-sectional views (e.g., Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figures 5A-5C 、 Figures 6A-6C 、 Figures 7A-7C 、 Figure 8A 、 Figure 8B ) can be shown without specifying the device region (e.g., 200 or 300) for which the processing is the same. Additionally, Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A and Figure 18A are cross-sectional views along cross-section B-B of the fin in the first device region 200, the corresponding cross-sectional views along cross-section B-B of the fin in the second device region 300 are the same or similar, with differences between the first device region 200 and the second device region 300 described in this disclosure, if any.

[0025] Referring now to Figure 3A and Figure 3B , fin structures 91 are formed to protrude above the substrate 50. Each fin structure 91 includes a fin 90 and a layer stack 92 overlying the fin 90. The layer stack 92 and the fin 90 can be formed by etching a trench in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the fin 90 can be formed by the same etching process.

[0026] The fin structures 91 can be patterned by any suitable method. For example, one or more photolithography processes (including a double patterning process or a multiple patterning process) can be used to pattern the fin structures 91. In general, a double patterning process or a multiple patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns with, for example, smaller pitch than is obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern, for example, the fin structures 91.

[0027] In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. The mask 94 can be a single layer mask, or can be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B can each be formed from a dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A can be silicon oxide, and the second mask layer 94B can be silicon nitride. The mask 94 can be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. The mask 94 can then be used as an etch mask to etch the substrate 50 and the multi-layer stack 64. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multi-layer stack 64 forms a layer stack 92, and the patterned substrate 50 forms a fin 90, as shown in Figure 3A and Figure 3B Thus, in the illustrated embodiment, the layer stack 92 also includes alternating layers of the first semiconductor material 52 and the second semiconductor material 54, and the semiconductor fin 90 is formed from the same material as the substrate 50 (e.g., silicon).

[0028] Next, in Figure 4A and Figure 4B , a shallow trench isolation (STI) region 96 is formed over the substrate 50 and on opposite sides of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed over the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material to another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a FCVD process. An annealing process can be performed after the insulating material is formed.

[0029] In some embodiments, the insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surfaces of the substrate 50 and the fin structure 91, and then a fill material, such as the materials discussed above, is formed over the liner. In some embodiments, the liner is omitted.

[0030] Next, a removal process is applied to the insulating material to remove excess insulating material over the fin structures 91. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like can be utilized. The planarization process exposes the layer stack 92 such that the top surface of the layer stack 92 and the insulating material are flush after the planarization process is completed. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the layer stack 92 protrudes from between adjacent STI regions 96. The top of the fins 90 can also protrude from between adjacent STI regions 96. In addition, the top surface of the STI regions 96 can have a planar surface, a convex surface, a concave surface (e.g., dishing), or a combination thereof as shown. The top surface of the STI regions 96 can be made planar, convex, and / or concave by an appropriate etch. The STI regions 96 can be recessed using an acceptable etch process, such as an etch process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 90 and the layer stack 92). For example, a chemical oxide removal using an appropriate etchant such as dilute hydrofluoric acid (dHF) acid can be used.

[0031] Still referring to Figure 4A and Figure 4B A dummy gate dielectric 97 is formed over the layer stack 92 and over the STI regions 96. The dummy gate dielectric 97 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. In an embodiment, a layer of silicon is conformally formed over the layer stack 92 and over the top surface of the STI regions 96, and a thermal oxidation process is performed to convert the deposited silicon layer to an oxide layer as the dummy gate dielectric 97.

[0032] Next, in Figures 5A-5C , a dummy gate 102 is formed over the fin structures 91. To form the dummy gate 102, a dummy gate layer can be formed over the dummy gate dielectric 97. The dummy gate layer can be deposited over the dummy gate dielectric 97 and then planarized, for example, by CMP. The dummy gate layer can be an electrically conductive material and can be selected from a group including amorphous silicon, polysilicon, poly-silicon germanium (poly-SiGe), or the like. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art. The dummy gate layer can be made of other materials having a high etch selectivity with respect to the isolation regions 96.

[0033] A mask 104 is then formed over the dummy gate layer. The mask 104 can be formed of silicon nitride, silicon oxynitride, a combination thereof, or the like, and can be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer by acceptable etching techniques to form the dummy gates 102, and then to the dummy dielectric layer by acceptable etching techniques to form the dummy gate dielectric 97. The dummy gates 102 cover respective channel regions in the layer stack 92. The pattern of the mask 104 can be used to separate each dummy gate 102 from adjacent dummy gates. The dummy gates 102 can also have a length direction that is substantially perpendicular to a length direction of the fin structures 91. In some embodiments, the dummy gates 102 and the dummy gate dielectric 97 are collectively referred to as dummy gate structures.

[0034] Next, an inter-gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI regions 96, and the dummy gates 102. The insulating material can be silicon nitride, silicon carbon nitride, a combination thereof, or the like. In some embodiments, the inter-gate spacer layer 108 includes multiple sub-layers. For example, a first sub-layer (sometimes referred to as a gate seal spacer layer) can be formed by thermal oxidation or deposition, and a second sub-layer (sometimes referred to as a main inter-gate spacer layer) can be conformally deposited over the first sub-layer.

[0035] Figure 5B and Figure 5C respectively illustrate Figure 5A cross-sectional views of the NSFET device 100 in Figure 5A along cross-sections E-E and F-F. Cross-sections E-E and F-F correspond to cross-sections D-D and A-A, respectively, in Figure 1

[0036] Next, in Figures 6A-6C the inter-gate spacer layer 108 is etched by an anisotropic etching process to form the inter-gate spacers 108. The anisotropic etching process can remove horizontal portions of the inter-gate spacer layer 108 (e.g., portions over the STI regions 96 and the dummy gates 102), and remaining vertical portions of the inter-gate spacer layer 108 (e.g., along sidewalls of the dummy gates 102 and the dummy gate dielectric 97) form the inter-gate spacers 108.

[0037] Figure 6B and Figure 6C respectively illustrate Figure 6A cross-sectional views of the NSFET device 100 in Figure 6B ​In some embodiments, portions of the gate spacer layer 108 are shown as being disposed on the upper surface of the STI region 96 between adjacent fins 90. Because the anisotropic etch process discussed above can not completely remove the gate spacer layer 108 disposed between adjacent fins 90 due to the small distance between adjacent fins 90, those portions of the gate spacer layer 108 can remain. In other embodiments, the portions of the gate spacer layer 108 disposed on the upper surface of the STI region 96 between adjacent fins 90 are completely removed by the anisotropic etch process to form the gate spacers 108.

[0038] After the gate spacers 108 are formed, an implant of a lightly doped source / drain (LDD) region (not shown) can be performed. Impurities of an appropriate type (e.g., p-type or n-type) can be implanted into the exposed layer stack 92 and / or the fins 90. The n-type impurities can be any suitable n-type impurities, such as phosphorus, arsenic, antimony, etc., and the p-type impurities can be any suitable p-type impurities, such as boron, BF2, indium, etc. The lightly doped source / drain region can have an impurity concentration of about 10 15 cm -3 to about 10 16 cm -3 . An anneal process can be used to activate the implanted impurities.

[0039] Next, openings 110 (which can also be referred to as recesses) are formed in the layer stack 92. The openings 110 can extend through the layer stack 92 and into the fins 90. The openings 110 can be formed using any acceptable etching technique using, for example, the dummy gates 102 as an etch mask.

[0040] After the openings 110 are formed, a selective etch process is performed to recess the ends of the first semiconductor material 52 exposed by the openings 110 without substantially etching the second semiconductor material 54. After the selective etch process, recesses are formed in the first semiconductor material 52 such that the sidewalls of the first semiconductor material 52 are recessed from the corresponding sidewalls of the second semiconductor material 54. Thus, the recesses in the first semiconductor material 52 are also referred to as sidewall recesses.

[0041] Next, an inner spacer layer is formed (e.g., conformally) in the openings 110. The inner spacer layer also fills the sidewall recesses in the first semiconductor material 52 formed by the previous selective etch process. The inner spacer layer can be an appropriate dielectric material such as silicon carbon nitride (SiCN), silicon carbon nitride oxide (SiOCN), etc. formed by an appropriate deposition method such as PVD, CVD, ALD, etc. Next, an etch process such as an anisotropic etch process is performed to remove portions of the inner spacer layer outside the sidewall recesses in the first semiconductor material 52. The remaining portions of the inner spacer layer (e.g., the portions disposed within the sidewall recesses in the first semiconductor material 52) form inner spacers 55. Figure 6B and Figure 6C cross-sectional views of the NSFET device 100 in Figure 6A along cross-sections E-E and F-F in Figure 6A .

[0042] Next, in Figures 7A-7C , source / drain regions 112 are formed in the openings 110. In the illustrated embodiment, the source / drain regions 112 are formed from epitaxial material(s) and can thus also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the openings 110 to impart stress in the respective channel regions of the NSFETs formed to improve performance. The epitaxial source / drain regions 112 are formed such that each dummy gate 102 is disposed between respective adjacent pairs of epitaxial source / drain regions 112. In some embodiments, the gate spacers 108 are used to separate the epitaxial source / drain regions 112 from the dummy gates 102 by an appropriate lateral distance so that the epitaxial source / drain regions 112 do not short the subsequently formed gates of the resulting NSFETs.

[0043] The epitaxial source / drain regions 112 are epitaxially grown in the openings 110. The epitaxial source / drain regions 112 can include any acceptable material appropriate for n-type or p-type devices, for example. For example, when forming n-type devices, the epitaxial source / drain regions 112 can include a material that imparts tensile strain in the channel region such as silicon, SiC, SiCP, SiP, etc. Likewise, when forming p-type devices, the epitaxial source / drain regions 112 can include a material that imparts compressive strain in the channel region such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain regions 112 can have a surface that protrudes from the respective surface of the fin and can have a facet.

[0044] The epitaxial source / drain regions 112 and / or the fins can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions can be between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities used for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 112 can be doped in-situ during growth.

[0045] As a result of the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has facets that laterally extend outward beyond the sidewalls of the fins 90. In the illustrated embodiment, the adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed (see Figure 7B ). In other embodiments, the facets cause adjacent epitaxial source / drain regions 112 of the same NSFET to merge.

[0046] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain regions 112 and over the dummy gate 102 (e.g., conformally), and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed of silicon nitride using PECVD, although other dielectric materials (e.g., silicon oxide, silicon oxynitride, combinations thereof, etc.) and alternative techniques for forming the CESL 116 (e.g., low pressure CVD (LPCVD), PVD, etc.) can alternatively be used.

[0047] The first ILD 114 can be formed of a dielectric material, and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material used for the first ILD 114 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. Figure 7B and Figure 7C cross-sectional view of the NSFET device 100 of Figure 7A is shown, but along cross-sections E-E and F-F in Figure 7A , respectively.

[0048] Next, a contact etch stop layer (CESL) 116 is formed over the source / drain regions 112 and over the dummy gate 102 (e.g., conformally), and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed of silicon nitride using PECVD, although other dielectric materials (e.g., silicon oxide, silicon oxynitride, combinations thereof, etc.) and alternative techniques for forming the CESL 116 (e.g., low pressure CVD (LPCVD), PVD, etc.) can alternatively be used. Figure 8A and Figure 8BIn some embodiments, dummy gate 102 is removed by a planarization process such as CMP to planarize the top surfaces of first ILD 114 and CESL 116 with the top surfaces of dummy gate 102 and gate spacers 108. The planarization process can also remove mask 104 (see Figure 7A ) on dummy gate 102, and portions of gate spacers 108 and CESL 116 along the sidewalls of mask 104. After the planarization process, the top surfaces of dummy gate 102, gate spacers 108, CESL 116, and first ILD 114 are planar. Thus, the top surface of dummy gate 102 is exposed through first ILD 114.

[0049] Next, dummy gate 102 is removed in an etching step(s) so that recesses 103 (also referred to as gate trenches) are formed. In some embodiments, dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using reactive gas(es) that selectively etch dummy gate 102 without etching first ILD 114 or gate spacers 108. Each recess 103 exposes a channel region of an NSFET. Each channel region is disposed between an adjacent pair of epitaxial source / drain regions 112. During the removal of dummy gate 102, dummy gate dielectric 97 can act as an etch stop layer when etching dummy gate 102. Dummy gate dielectric 97 can then be removed after the removal of dummy gate 102. An etching process such as an isotropic etching process can be performed to remove dummy gate dielectric 97. In an embodiment, an isotropic etching process using etching gases including HF and NH3is performed to remove dummy gate dielectric 97. Figure 8B A cross-sectional view of NSFET device 100 along cross-section F-F is shown in Figure 8A .

[0050] Next, first semiconductor material 52 is removed to release second semiconductor material 54 in Figure 9A and Figure 9B . After the removal of first semiconductor material 52, second semiconductor material 54 forms a plurality of nanostructures 54 that extend horizontally (e.g., parallel to major upper surface 50U of substrate 50). Nanostructures 54 can be collectively referred to as channel regions 93 or channel layer 93 of the formed NSFET device 100. As Figure 9AAs shown, by removing the first semiconductor material 52, gaps 53 (e.g., empty spaces) are formed between the nanostructures 54. Gaps 53 are also formed between the lowermost nanostructures 54 and the top surface of the fin 90. In some embodiments, depending on, for example, the dimensions (e.g., size and / or aspect ratio) of the nanostructures 54, the nanostructures 54 are nanosheets or nanowires.

[0051] In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective (e.g., has a higher etch rate) to the first semiconductor material 52, such that the first semiconductor material 52 is removed without substantially etching the second semiconductor material 54. In some embodiments, an isotropic etching process is performed to remove the first semiconductor material 52. The isotropic etching process can be performed using an etching gas including F2and HF, and optionally using a carrier gas, which can be an inert gas, such as Ar, He, N2, combinations thereof, and the like. The isotropic etching process can include a first step to remove the first semiconductor material 52, and a second step after the first step to reshape the profile of the nanostructures 54.

[0052] Figure 9A A cross-sectional view of the NSFET device 100 along a longitudinal axis of the fin 90 (e.g., along a direction of current flow in the fin) is shown, and Figure 9B A cross-sectional view of the NSFET device 100 along a cross-section F-F that is a cross-section along a direction perpendicular to the longitudinal axis of the fin 90 and across a middle portion of the nanostructures 54 is shown. Note that, Figure 9B A first device region 200 (e.g., a logic device region) and a second device region 300 (e.g., an I / O device region) are shown. As Figure 9B As shown, each device region (e.g., 200, 300) has a plurality of fins 90, and each fin 90 has a plurality of nanostructures 54 overlying (e.g., above and vertically aligned with) the fin 90. The first device region 200 and the second device region 300 can be immediately adjacent to each other, or can be separated from each other, as Figure 9B shown by the divider 121 in

[0053] As Figure 9A shown, after the nanostructures 54 are formed, each nanostructure 54 has a dumbbell shape in a cross-section along a longitudinal axis of the fin 90, where the height TE (which is along the vertical direction) of the end portions (e.g., portions in physical contact with the source / drain regions 112) of the nanostructure 54 is greater than the height TM (which is along the vertical direction) of the middle portion of the nanostructure 54. Figure 9Athe middle portion (e.g., the portion between the ends) of the nanostructure 54. The difference between the height TE and the height T of the nanostructure 54 can be referred to as a sheet height gap of the nanostructure 54.

[0054] In some embodiments, the layers of the second semiconductor material 54 in the multi-layer stack 64 (see Figure 2 ) are formed to have substantially the same thickness, thus all the nanostructures 54 in the first device region 200 and the second device region 300 have substantially the same shape and size (e.g., TE, T) at the processing stages of Figure 9A and Figure 9B In some embodiments, the layers of the second semiconductor material 54 in the multi-layer stack 64 (see Figure 9A and Figure 9B In some embodiments, the upper surface and the lower surface of the middle portion of each nanostructure 54 are curved, e.g., curved towards a horizontal center axis of the nanostructure 54. In addition, in the cross-section of Figure 9B , each nanostructure 54 has a stadium shape (may also be referred to as a racetrack shape, an irregular quadrilateral shape, an elliptical shape, or a sausage body shape). In the cross-section of Figure 9B , the corners of each nanostructure 54 are rounded (e.g., curved). In some embodiments, at the processing stages of Figure 9A and Figure 9B , the height T is between about 3 nm to about 20 nm, the height TE is between about 3 nm to about 35 nm, and the difference between TE and T (e.g., the sheet height gap) is between about 0 nm to about 15 nm.

[0055] As feature sizes continue to shrink in advanced processing nodes, the distance between adjacent nanostructures 54 can become so small that it can be difficult to form a layer (e.g., a gate dielectric layer) around the nanostructures 54 in subsequent processing. By forming the nanostructures 54 in a dumbbell shape, the distance between adjacent nanostructures 54 is increased, thus making it easier to form, for example, the gate dielectric layer 122 (see Figure 11A and Figure 11B ) around the nanostructures 54. In addition, because the height T of the nanostructures 54 that form the channel region 93 of the NSFET device 100 is reduced, it is easier to control (e.g., turn on or off) the NSFET device 100 by applying a gate control voltage on the metal gate formed in subsequent processes.

[0056] Next, at the processing stages of Figure 10A and Figure 10BIn some embodiments, the interface layer 120 is formed on the surfaces of the nanostmctures 54 exposed by the gaps 53 and the recesses 103. The interface layer 120 can also be formed on the surfaces of the fins 90 exposed by the gaps 53. In some embodiments, the interface layer 120 is a dielectric material, and specifically an oxide layer formed by oxidizing the outer portions (e.g., surface portions) of the nanostmctures 54 (or fins 90), and thus can also be referred to as a gate oxide layer, an interface dielectric material, or a dielectric layer. In other words, in some embodiments, the interface layer 120 is an oxide of the second semiconductor material 54. Note that in the illustrated embodiments, the fins 90 and the second semiconductor material 54 include the same material (e.g., silicon), although in other embodiments the fins 90 and the second semiconductor material 54 can include different materials. The interface layer 120 (e.g., oxide layer) can be silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon germanium oxynitride (Si z Ge (1-z) O x N y ), etc.

[0057] In embodiments, to form the interface layer 120, chemical oxidation by a wet etching process is performed by oxidizing the outer portions of the nanostmctures 54 and the fins 90 using an oxidizing agent (e.g., SPM (a mixture of H2SO4 and H2O2), SC1 (a mixture of NH4OH and H2O2), or ozone deionized water (a mixture of O3 and deionized water)). In another embodiment, to form the interface layer 120, thermal oxidation is performed by treating (e.g., soaking) the nanostmctures 54 and the fins 90 in an oxygen-containing gas source, where the oxygen-containing gas source includes, for example, N2O, O2, a mixture of N2O and H2, or a mixture of O2 and H2. The thermal oxidation can be performed at a temperature between about 500 °C to about 1000 °C. Note that in the illustrated embodiments, the interface layer 120 is formed by converting (e.g., oxidizing) the outer portions of the nanostmctures 54 and the fins 90 into an oxide, and thus the interface layer 120 is selectively formed on the exposed surfaces of the nanostmctures 54 and the fins 90, and not formed on other surfaces (e.g., sidewalls of the inner spacers 55 and the gate spacers 108).

[0058] In some embodiments, the interface layer 120 around the nanostmctures 54 is conformal and has substantially the same uniform thickness in both the first device region 200 and the second device region 300 during the processing stages of Figure 10A and Figure 10B For example, in the processing stages of Figure 10BIn the interface layer 120, the top portion 120T (e.g., a portion on the top surface of the nanostructure 54), the bottom portion 120L (e.g., a portion on the bottom surface of the nanostructure 54), and the sidewall portion 120S (e.g., a portion on the sidewall of the nanostructure 54) of the interface layer 120 have substantially the same thickness, wherein the thickness is measured at the measurement location along a direction perpendicular to the outer surface of the nanostructure 54.

[0059] Next, in Figure 11A and Figure 11B In this process, a gate dielectric layer 122 is formed on the interface layer 120 (e.g., around the nanostructure 54) (e.g., conformally) along the sidewalls of the gate spacer 108 and along the upper surface of the first ILD 114. According to some embodiments, the gate dielectric layer 122 comprises silicon oxide, silicon nitride, or a multilayer thereof. In exemplary embodiments, the gate dielectric layer 122 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 122 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. For example, the high-k dielectric material may be HfO2, ZrO2, HfZrO, HfTiO, HfLaO, HfAlO, La-doped HfZrO (La:HfZrO), Al-doped HfZrO (Al:HfZrO), or Ti-doped HfZrO (Ti:HfZrO). The thickness of the gate dielectric layer 122 can be between about 8 angstroms and about 50 angstroms. Methods for forming the gate dielectric layer 122 may include molecular beam deposition (MBD), ALD, PECVD, etc. In this embodiment, the gate dielectric layer 122 is formed by ALD at a temperature between about 200°C and about 400°C.

[0060] Next, in Figure 12A and Figure 12BIn this process, a seed layer 124 (optional) is formed on the gate dielectric layer 122 (e.g., conformally). In some embodiments, the seed layer 124 is a dielectric film or a metal film (e.g., containing a metal film). In some embodiments, the dielectric film of the seed layer 124 is formed from: SiO2, high-k dielectric materials such as TiO2, Al2O3, La2O3, Ga2O3, In2O3, ZnO, Nb2O5, MgO, or Ta2O5, etc. In some embodiments, the metal film of the seed layer 124 is formed from: TiN, TiSiN, AlN, TiAlN, TaN, etc. The seed layer 124 can be formed by, for example, ALD or CVD. The thickness of the seed layer 124 can be between about 0 angstroms and about 30 angstroms. In some embodiments, the seed layer 124 is omitted. In some embodiments, the seed layer 124 helps to modulate oxidation behavior, for example, at the upper surface of the nanostructure 54, and control the thickness of the interface layer 120 during subsequent oxidation processes. In addition, the seed layer 124 can improve the thickness uniformity of the interface layer 120 at different vertical levels during subsequent oxidation processes.

[0061] Next, in Figure 13A and Figure 13B In this process, a first hard mask layer 126 is formed on a seed layer 124, or, if the seed layer 124 is omitted, on a gate dielectric layer 122. The first hard mask layer 126 is then patterned to form a patterned hard mask layer, thereby shielding the first device region 200 from subsequent oxidation processes. The first hard mask layer 126 may be formed of a dielectric material, a metallic material, or silicon. Examples of dielectric materials for the first hard mask layer 126 include TiO2, Al2O3, La2O3, Ga2O3, In2O3, ZnO, Nb2O5, MgO, and Ta2O5. Examples of metallic materials for the first hard mask layer 126 include TiN, TiSiN, AlN, and TiAlN. In some embodiments, the first hard mask layer 126 is formed of the same material as the seed layer 124. In other embodiments, the first hard mask layer 126 is formed of a different material than the seed layer 124. The first hard mask layer 126 may be formed by, for example, ALD or CVD. exist Figure 13A and Figure 13B In the example, the first hard mask layer 126 fills (e.g., fully fills) the gap 53 (see...). Figure 12A and Figure 12B The first hard mask layer 126 is lined with the sidewalls and bottom of the recess 103. The thickness of the first hard mask layer 126 can be about 5 angstroms or greater. The upper limit of the thickness of the first hard mask layer 126 can depend on, for example, the width of the recess 103.

[0062] Next, in Figure 14A and Figure 14BIn some embodiments, the patterned mask layer 127 is formed by forming a photoresist layer over the first device region 200 and the second device region 300. The photoresist layer is then patterned, removing portions of the photoresist layer disposed over the second device region 300. As shown in Figure 14B the first hardmask layer 126 in the second device region 300 is exposed by the patterned mask layer 127, and the first hardmask layer 126 in the first device region 200 is covered by the patterned mask layer 127. Note that Figure 14A a cross-section along the longitudinal axis of the fin 90 in the first device region 200 is shown, so the patterned mask layer 127 covers the first hardmask layer 126. Although not shown, one of skill in the art will readily understand that a cross-section along the longitudinal axis of the fin 90 in the second device region 300 is similar to Figure 14A but without the patterned mask layer 127.

[0063] Next, in Figure 15A and Figure 15B the first hardmask layer 126 in the second device region 300 is removed. As shown in Figure 15B the appropriate etching process can be performed to remove the exposed first hardmask layer 126 in the second device region 300, while the patterned mask layer 127 shields (e.g., protects) the first device region 200 from the etching process. The etching process can use an etchant that is selective (e.g., has a higher etch rate) to the material of the first hardmask layer 126. After the first hardmask layer 126 is removed, the patterned mask layer 127 (e.g., the patterned photoresist layer) can be removed by a suitable process such as ashing. Note that because the first hardmask layer 126 in the second device region 300 is removed, there is a gap 53 between, for example, adjacent nanostructures 54.

[0064] Next, in Figure 16A and Figure 16B a second hardmask layer 128 (which is optional) is formed on the first hardmask layer 126 in the first device region 200, and on the seed layer 124 in the second device region 300 (or on the gate dielectric layer 122 when the seed layer 124 is omitted). The second hardmask layer 128 can be formed of a dielectric material, a metallic material, or silicon. The second hardmask layer 128 can be formed of the same or similar material as the first hardmask layer 126 using the same or similar formation method, so details are not repeated. The thickness of the second hardmask layer 128 can be between about 0 Angstrom and about 50 Angstrom. In some embodiments, the second hardmask layer 128 is omitted.

[0065] In Figure 16A and Figure 16B In the illustrated embodiment, in the first device region 200, the first hard mask layer 126 completely fills the gaps between the nanostructures 54 and between the lowermost nanostructure 54 and the fin 90. Thus, the second hard mask layer 128 extends along the outer surface of the first hard mask layer 126 around the nanostructures 54. In the second device region 300, the second hard mask layer 128 extends along the outer surface of the seed layer 124, or along the outer surface of the gate dielectric layer 122 if no seed layer 124 is formed. Note that in the cross-sectional view of Figure 16B In the cross-sectional view of

[0066] Next, an oxidation process 129 is performed to increase the thickness of the interface layer 120 (e.g., gate oxide layer) around the nanostructures 54. Because the first device region 200 and the second device region 300 have different numbers of hard mask layers (the reduction of hard mask layers reduces the effect of the oxidation process on the nanostructures 54 / interface layer 120), the effect of the oxidation process on the interface layer 120 is different in the first device region 200 and the second device region 300, which results in different thicknesses of the interface layer 120 in the first device region 200 and the second device region 300. Details are discussed below.

[0067] In some embodiments, the oxidation process is a plasma process (also referred to as a plasma oxidation process) performed by processing the NSFET device 100 (e.g., the nanostructures 54) using a plasma of an oxygen-containing gas source. The oxygen-containing gas source can be, for example, oxygen gas (O2), nitrous oxide gas (N2O), a mixture of nitrous oxide gas (N2O) and nitrogen gas (N2), a mixture of oxygen gas (O2) and nitrogen gas (N2), a mixture of oxygen gas (O2) and an inert gas, or a mixture of nitrous oxide gas (N2O) and an inert gas, where the inert gas can be, for example, argon gas (Ar), or helium gas (He). The oxygen-containing gas source can be ignited into a plasma by, for example, a capacitively coupled plasma (CCP) system or an inductively coupled plasma (ICP) system, and then the nanostructures 54 are processed by the plasma. In some embodiments, the pressure of the plasma process is between about 1 mTorr and about 10 Torr, and the temperature of the plasma process is between room temperature and about 500 °C. In some embodiments, the duration of the plasma process is determined (e.g., adjusted) by the requirements (e.g., thickness) of the interface layer 120.

[0068] In some embodiments, the oxidation process is a thermal process (also referred to as a thermal oxidation process) performed by immersing the NSFET device 100 (e.g., the nanostructure 54) in an oxygen-containing gas source. In an example embodiment, the oxygen-containing gas source is ozone (O3) gas, and the ozone gas is supplied in contact with the NSFET device 100 to perform the thermal oxidation process. In some embodiments, the temperature of the thermal oxidation process is between room temperature and about 500 °C. In some embodiments, the duration of the plasma process is determined (e.g., adjusted) by the requirement (e.g., thickness) of the interface layer 120.

[0069] The oxidizer of the oxidation process (e.g., the plasma of the oxygen-containing gas source, or the oxygen-containing gas source) penetrates or diffuses through the layers (e.g., 128, 124, 122, 120) surrounding the nanostructure 54 in the second device region 300, and converts (e.g., oxidizes) the outer portion of the nanostructure 54 into an oxide of the material of the nanostructure 54, thereby increasing the thickness of the interface layer 120 in the second device region 300. Because the outer portion of the nanostructure 54 in the second device region 300 is converted into the oxide, the height of the nanostructure 54 (e.g., the remaining unoxidized portion of the semiconductor material of the nanostructure 54) in the second device region 300 is reduced, the details of which are discussed below with reference to Figure 17B .

[0070] Note that, compared to the nanostructure 54 in the second device region 300, the nanostructure 54 in the first device region 200 is shielded (covered) by more (e.g., thicker) hard mask layers (e.g., 126 and 128), and thus, the oxidizer of the oxidation process can not reach the nanostructure 54 in the first device region 200, or can be partially blocked by the hard mask layers. As a result, the thickness of the interface layer 120 surrounding the nanostructure 54 in the first device region 200 can remain unchanged, or can increase by a smaller amount compared to the thickness of the interface layer 120 in the second device region 300, before and after the oxidation process. For embodiments that omit the second hard mask layer 128, the different effects of the oxidation process on the interface layer 120 in the first device region 200 and the second device region 300 are similar to the discussion above, and thus are not repeated. In the following discussion, the interface layer 120 in the first device region 200 can also be referred to as the interface layer 120A, and the interface layer 120 in the second device region 300 can also be referred to as the interface layer 120B.

[0071] Next, in Figure 17A and Figure 17BIn some embodiments, after the oxidation process is completed, the second hard mask layer 128, the first hard mask layer 126, and the seed layer 124 are removed, and the gate dielectric layer 122 is exposed. In some embodiments, one or more etching processes can be performed to remove the second hard mask layer 128, the first hard mask layer 126, and the seed layer 124. The one or more etching processes can be selective such that the second hard mask layer 128, the first hard mask layer 126, and the seed layer 124 are removed without etching other materials of the NSFET device 100, such as the nanostructures 54. In some embodiments, the etching processes are performed using a suitable etchant, such as SC1, SC2 (a mixture of HC1, H202, and deionized water), or dilute hydrofluoric acid (dHF) acid.

[0072] In Figure 17B In some embodiments, the nanostructures 54 above the fins 90 are labeled as 54A, 54B, and 54C to distinguish the nanostructures 54 at different vertical levels (e.g., different distances from the major upper surface 50U of the substrate 50). As described above, after the oxidation process, the height of the nanostructures 54 in the second device region 300 is reduced. The height of the nanostructures 54 in the first device region 200 can remain unchanged, or can be reduced by a smaller amount compared to the height of the nanostructures 54 in the second device region 300.

[0073] In some embodiments, the oxidation process has different effects on the thickness of the interface layer 120 (e.g., 120A, 120B) at different vertical levels. In embodiments, the thickness (e.g., average thickness) of the interface layer 120B around the nanostructures 54 (e.g., 54A, 54B, and 54C) in the second device region 300 increases along the vertical direction Z in Figure 17B In some embodiments, the oxidation process has different effects on the thickness of the interface layer 120 (e.g., 120A, 120B) at different vertical levels. In embodiments, the thickness (e.g., average thickness) of the interface layer 120B around the nanostructures 54 (e.g., 54A, 54B, and 54C) in the second device region 300 increases along the vertical direction Z in

[0074] In some embodiments, the thickness of the interface layer 120 (e.g., 120A, 120B) around the nanostructure 54 (e.g., 54C, 54B, or 54A) can vary at different locations due to the anisotropy of the oxidation process. For example, a top portion 120T (e.g., a portion along the upper surface of the nanostructure 54) of the interface layer 120B can be thicker than a sidewall portion 120S (e.g., a portion along the sidewall of the nanostructure 54) of the interface layer 120B, and the sidewall portion 120S can be thicker than a bottom portion 120L (e.g., a portion along the lower surface of the nanostructure 54) of the interface layer 120B. In some embodiments, the difference between the thickness of the top 120T, sidewall portion 120S, and bottom 120L of the same nanostructure 54 in the second device region 300 can be between about 0 Angstrom and about 15 Angstrom. To this end, in the discussion herein, when the thickness of the interface layer 120 around a first nanostructure (e.g., 54C) is referred to as being thicker than the thickness of the interface layer 120 around a second nanostructure (e.g., 54A), it means that the average thickness (e.g., the average of the thicknesses of portions 120T, 120S, and 120L) of the interface layer 120 around the first nanostructure is thicker than the average thickness of the interface layer 120 around the second nanostructure. Additionally or alternatively, it can mean that a particular portion (e.g., 120T, 120S, or 120L) of the interface layer 120 around the first nanostructure is thicker than the same portion (e.g., 120T, 120S, or 120L) of the interface layer 120 around the second nanostructure.

[0075] In some embodiments, the height (e.g., T1, T2, T3) of the nanostructure 54 in the second device region 300 can decrease along the vertical direction Z in Figure 17B (e.g., T1 < T2 < T3), where the height is measured along the vertical direction Z between the upper and lower surfaces (of the unoxidized portion) of the nanostructure 54. For example, the height T1 of the nanostructure 54C is less than the height T3 of the nanostructure 54A because more surface portions of the nanostructure 54C are converted (e.g., oxidized) into the interface layer 120B. In the second device region 300, the difference between the heights of the nanostructures 54 at different vertical levels can be between about 0 nm and about 6 nm.

[0076] As described above, because the first device region 200 is shielded by the thicker hard mask layers (e.g., 128 and 126) during the oxidation process, the oxidation process has a reduced impact on the interface layer 120 in the first device region 200, or no impact on the interface layer 120 in the first device region 200 when the hard mask layers (e.g., 128 and 126) completely block the oxidizer of the oxidation process. As a result, the interface layer 120A at a particular vertical level (e.g., around the nanostmcture 54C) in the first device region 200 is thinner than the interface layer 120B at the same vertical level (e.g., around the nanostmcture 54C) in the second device region 300. Conversely, the height of the nanostmcture (e.g., 54C) at the particular vertical level in the first device region 200 is greater than the height of the nanostmcture (e.g., 54C) at the same vertical level in the second device region 300. Here, the phrase“same vertical level” is used to describe two nanostmctures (e.g., 54C) that have the same vertical distance from the substrate but are in different device regions (e.g., 200, 300), where the vertical distance is between the horizontal center axis of the nanostmcture and the major upper surface of the substrate. In some embodiments, the difference between the height of the nanostmctures 54 (e.g., at the same vertical level) in the first device region 200 and the second device region 300 is between about 0 nm and about 6 nm. In some embodiments, the difference between the thickness of the interface layers 120A and 120B (e.g., at the same vertical level) in the first device region 200 and the second device region 300 is between about 0 Angstrom and about 30 Angstrom. In some embodiments where the oxidation process has no impact on the interface layer 120 in the first device region 200, all of the nanostmctures 54 in the first device region 200 have the same height T, which is greater than the height of the nanostmctures 54 in the second device region 300 (e.g., T > T3 > T2 > T1), and the thickness of the interface layer 120A around all of the nanostmctures 54 in the first device region 200 has the same value, which is less than the minimum thickness of the interface layer 120B around all of the nanostmctures 54 in the second device region 300. In some embodiments, the sheet height gap of the nanostmctures 54 in the first device region 200 is less than the sheet height gap of the nanostmctures 54 in the second device region 300. In some embodiments, the difference between the sheet height gap of the nanostmctures 54 in the first device region 200 and the sheet height gap of the nanostmctures 54 in the second device region 300 is between about 0 nm and about 10 nm.

[0077] In some embodiments, the thickness of the gate dielectric layer 122 (e.g., along the sidewalls of the gate spacers 108 and along the nanostmctures 54) in the first device region 200 and the second device region 300 are substantially the same, with a difference between the thicknesses of between about 0 Angstrom and about 5 Angstrom. In some embodiments, the composition (e.g., atomic percentage of nitrogen and oxygen) of the sidewalls of the gate spacers 108 facing the recesses 103 in the first device region 200 and the second device region 300 are different, which can be due to a different amount of oxidizing agent reaching the gate spacers 108 during the oxidation process (e.g., due to a different number of hard mask layers used). For example, the oxidation process can change the composition of the gate spacers 108 from a nitride-rich composition to an oxygen-rich composition. As a result, after the oxidation process, the gate spacers 108 in the first device region 200 can have a higher atomic percentage of nitrogen and a lower atomic percentage of oxygen than the gate spacers 108 in the second device region 300, because the first device region 200 was shielded by thicker hard mask layers (e.g., 128 and 126) during the oxidation process. Additionally, in a subsequent etch process to remove the hard mask layers, the gate spacers 108 in the second device region 300 (which have a higher atomic concentration of oxygen) can be more susceptible to damage (e.g., etching) than the gate spacers 108 in the first device region 200, and thus, in the final product of the NSFET device 100, the thickness of the gate spacers 108 in the first device region 200 can be greater than the thickness of the gate spacers 108 in the second device region 300.

[0078] In addition to using different numbers of hard mask layers (e.g., 126, 128) for the first device region 200 and the second device region 300 to achieve different thicknesses of the interface layer 120 (e.g., 120A, 120B) (e.g., gate oxide layer), other methods for modulating (e.g., changing) the thickness of the interface layer 120 are possible. As an example, the seed layer 124 can be formed to have different thicknesses in the first device region 200 and the second device region 300. The seed layer 124 can be used as another hard mask layer to influence the thickness of the interface layer 120. For example, the seed layer 124 can help control the thickness of the top portion 120T of the interface layer 120. The seed layer 124 can also increase the thickness uniformity of the interface layer 120 at different vertical levels. To achieve different thicknesses of the seed layer 124, a first patterned mask layer (e.g., patterned photoresist layer) can be used to cover the first device region 200 while the seed layer 124 is formed to a first thickness in the second device region 300. Next, the first patterned mask layer is removed, and a second patterned mask layer can be formed to cover the second device region 300 while the seed layer 124 is formed to a second thickness in the first device region 200. Other methods for achieving different thicknesses of the seed layer 124 are possible and are fully intended to be included within the scope of the present disclosure. As another example of achieving different thicknesses of the interface layer 120, parameters of the oxidation process (e.g., temperature, flow rate, or RF power of the plasma process) can also be adjusted to achieve different thicknesses of the interface layer 120A / 120B in different device regions (e.g., 200 and 300). By allowing different device regions (e.g., 200, 300) to have different thicknesses of gate oxide 120, the leakage current and power consumption of different device regions can be adjusted to achieve different performance targets, thus allowing for improved performance and versatility in the design of the NSFET device 100.

[0079] Next, in Figure 18A and Figure 18BIn particular, the gate electrode 130 is deposited over and around the gate dielectric layer 122, and fills the gap 53 and the remaining portion of the recess 103. The gate electrode 130 can include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multilayers thereof. For example, although a single layer of the gate electrode 130 is shown, the gate electrode 130 can include any number of liner layers (e.g., barrier layers), any number of work function adjustment layers, and fill material. After forming the gate electrode 130, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 122 and the gate electrode 130 that are above the top surface of the first ILD 114. The remaining portions of the gate electrode 130, the remaining portions of the gate dielectric layer 122, and the interface layer 120 thus form a replacement gate for the resulting NSFET device 100. Each gate electrode 130, along with the corresponding interface layer 120 and gate dielectric layer 122, can be collectively referred to as a gate stack, a replacement gate structure, or a metal gate structure. Each gate stack extends over and around the corresponding nanostmcture 54.

[0080] As will be readily appreciated by one of ordinary skill in the art, additional processing can be performed to complete fabrication of the NSFET device 100, and thus the details are not repeated here. For example, a second ILD can be deposited over the first ILD 114. In addition, gate contacts and source / drain contacts can be formed through the second ILD and / or the first ILD 114 to electrically couple to the gate electrode 130 and the source / drain regions 112, respectively.

[0081] Figure 19A and Figure 19B is a cross-sectional view of a nanostmcture field effect transistor (NSFET) device 100A at certain fabrication stages according to embodiments. The NSFET device 100A can be formed by similar processing steps as the NSFET device 100, but the gate dielectric layer 122 is formed after the oxidation process and after the removal of the hard mask layers (e.g., 126, 128) and the seed layer 124. Figure 19A and Figure 19B shows a cross-sectional view of the NSFET device 100A during the oxidation process 129. The oxidation process is the same or similar to the oxidation process used for the NSFET device 100, and thus the details are not repeated. Note that the gate dielectric layer 122 has not yet been formed during the processing of Figure 19A and Figure 19B

[0082] In particular, to form the NSFET device 100A, the following processing is performed: Figure 2 , Figure 3A , Figure 3B , Figure 4A ,​ Figure 4B 、 Figures 5A-5C 、 Figures 6A-6C 、 Figures 7A-7C 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B the processing steps in Figure 11A and Figure 11B are skipped. Next, the processing steps in Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B are performed, but without forming the gate dielectric layer 122. Next, the oxidation process of Figure 19A and Figure 19B is performed. Next, the hard mask layer (e.g., 128, 126) and the seed layer 124 are removed to expose the interface layer 120, and the gate dielectric layer 122 is formed on the exposed interface layer 120 along the sidewalls of the gate spacers 108 and along the upper surface of the first ILD 114, as shown in Figure 17A and Figure 17B . Next, the gate electrode 130 is formed, as shown in Figure 18A and Figure 18B .

[0083] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, for the NSFET devices 100 and 100A, the second hard mask layer 128 is optional and can be omitted. Further, the seed layer 124 is optional and can be omitted. As another example, depending on the type of device formed (e.g., n-type or p-type device), the second semiconductor material 54 can be removed and the first semiconductor material 52 can be retained to form a nanostructure that serves as a channel region for the NSFET device formed. In embodiments where the first semiconductor material 52 is retained to form a nanostructure, an internal spacer is formed in the sidewall recesses of the second semiconductor material 54 prior to removing the second semiconductor material 54, as will be readily understood by one of ordinary skill in the art.

[0084] Figure 20 A flowchart illustrating a method of fabricating a semiconductor device according to some embodiments is shown. It should be understood that the embodiment method shown in Figure 20 is merely an example of one of many possible embodiment methods. Those of ordinary skill in the art will recognize many changes, alternatives, and modifications. For example, steps can be added, removed, replaced, rearranged, or repeated as indicated by the arrows inFigure 20 each of the steps shown.

[0085] Referring to Figure 20 At block 1010, a first nanostructure is formed over a first fin and a second nanostructure is formed over a second fin, where the first fin and the second fin protrude above a substrate, where the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate. At block 1020, an interfacial dielectric material is formed around the first nanostructure and around the second nanostructure. At block 1030, a first hard mask layer is formed over the first fin but not over the second fin, where the first hard mask layer covers the interfacial dielectric material around the first nanostructure, where the interfacial dielectric material around the second nanostructure is exposed by the first hard mask layer. At block 1040, after forming the first hard mask layer, an oxidation process is performed, where after the oxidation process, a thickness of the interfacial dielectric material around the second nanostructure is increased. At block 1050, after performing the oxidation process, the first hard mask layer is removed.

[0086] Embodiments can achieve advantages. The disclosed embodiments allow gate oxides in different device regions of a semiconductor device to have different thicknesses. This allows devices with different performance targets (e.g., leakage current and power consumption) to be formed in different device regions of the same semiconductor device. The disclosed embodiments provide various ways to modulate gate oxide thickness in different device regions, such as by varying the number of hard mask layers, forming or not forming a seed layer 124, and adjusting oxidation process conditions. Advantages of forming a seed layer 124 include the ability to adjust the thickness of the gate oxide at the upper surface of the nanostructure 54, and improved thickness uniformity of the gate oxide at different vertical levels.

[0087] In an embodiment, a method of forming a semiconductor device includes: forming a first nanostructure over a first fin in a first device region of the semiconductor device, the first fin protruding above a substrate; forming a second nanostructure over a second fin in a second device region of the semiconductor device, the second fin protruding above the substrate, wherein the first and second nanostructures comprise a semiconductor material and extend parallel to a major upper surface of the substrate; forming a dielectric material around the first nanostructure and around the second nanostructure; forming a first hardmask layer around the first nanostructure in the first device region and around the second nanostructure in the second device region; after forming the first hardmask layer, removing the first hardmask layer from the second device region; and after removing the first hardmask layer from the second device region, increasing a first thickness of the dielectric material around the second nanostructure by performing an oxidation process. In an embodiment, a second thickness of the dielectric material around the first nanostructure remains unchanged before and after the oxidation process, or is increased less by the oxidation process than the first thickness of the dielectric material around the second nanostructure. In an embodiment, the dielectric material is an oxide of the semiconductor material. In an embodiment, the oxidation process converts an outer portion of the second nanostructure to the dielectric material, wherein the first hardmask layer shields the first nanostructure from the oxidation process. In an embodiment, performing the oxidation process includes: soaking the first and second nanostructures in a gas source comprising ozone. In an embodiment, the oxidation process is a plasma process. In an embodiment, performing the oxidation process includes: igniting a gas source to a plasma, wherein the gas source comprises oxygen, nitrous oxide gas, a mixture of nitrous oxide gas and nitrogen gas, a mixture of oxygen and nitrogen gas, a mixture of oxygen and an inert gas, or a mixture of nitrous oxide gas and an inert gas; and treating the first and second nanostructures with the plasma. In an embodiment, the method further includes: prior to forming the first hardmask layer, forming a high-k gate dielectric material on the dielectric material. In an embodiment, the method further includes: after forming the high-k gate dielectric material and prior to forming the first hardmask layer, forming a seed layer on the high-k gate dielectric material. In an embodiment, the method further includes: after removing the first hardmask layer from the second device region and prior to increasing the first thickness of the dielectric material, forming a second hardmask layer on the first hardmask layer in the first device region and around the second nanostructure in the second device region. In an embodiment, the method further includes: after increasing the first thickness of the dielectric material, removing the first hardmask layer from the first device region; and forming a gate electrode around the first nanostructure and around the second nanostructure. In an embodiment, the method further includes: after removing the first hardmask layer from the first device region and prior to forming the gate electrode, forming a high-k gate dielectric material around the first nanostructure and around the second nanostructure.

[0088] In an embodiment, a method of forming a semiconductor device includes forming a first nanostructure over a first fin and a second nanostructure over a second fin, wherein the first fin and the second fin protrude above a substrate, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; forming an interfacial dielectric material around the first nanostructure and around the second nanostructure; forming a first hardmask layer over the first fin but not over the second fin, wherein the first hardmask layer covers the interfacial dielectric material around the first nanostructure, wherein the interfacial dielectric material around the second nanostructure is exposed by the first hardmask layer; after forming the first hardmask layer, performing an oxidation process, wherein a thickness of the interfacial dielectric material around the second nanostructure increases after the oxidation process; and after performing the oxidation process, removing the first hardmask layer. In an embodiment, the method further includes, after removing the first hardmask layer, forming a gate electrode around the first nanostructure and around the second nanostructure. In an embodiment, the interfacial dielectric material is an oxide of the first semiconductor material, wherein the oxidation process converts an outer portion of the second nanostructure to the oxide of the first semiconductor material. In an embodiment, performing the oxidation process includes soaking the first nanostructure and the second nanostructure in an oxygen-containing gas source. In an embodiment, performing the oxidation process includes processing the first nanostructure and the second nanostructure using a plasma of the oxygen-containing gas source.

[0089] In an embodiment, a semiconductor device, comprising: a first fin and a second fin protruding above a substrate; a first nanostructure and a second nanostructure over the first fin and the second fin, respectively, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; a first interface dielectric layer around the first nanostructure and a second interface dielectric layer around the second nanostructure, wherein the second interface dielectric layer around the second nanostructure is thicker than the first interface dielectric layer around the first nanostructure; a gate dielectric layer on the first interface dielectric layer around the first nanostructure and on the second interface dielectric layer around the second nanostructure; a gate electrode around the first nanostructure and around the second nanostructure. In an embodiment, the first interface dielectric layer and the second interface dielectric layer comprise an oxide of the first semiconductor material. In an embodiment, individual ones of the first nanostructure have a first height measured between an upper surface of the individual first nanostructure distal to the substrate and a lower surface of the individual first nanostructure facing the substrate, and individual ones of the second nanostructure have a second height measured between an upper surface of the individual second nanostructure distal to the substrate and a lower surface of the individual second nanostructure facing the substrate, wherein the first height is greater than the second height, wherein the individual first nanostructure and the individual second nanostructure are the same vertical distance from the substrate.

[0090] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

[0091] Example 1 is a method of forming a semiconductor device, the method comprising: forming a first nanostructure over a first fin in a first device region of the semiconductor device, the first fin protruding above a substrate; forming a second nanostructure over a second fin in a second device region of the semiconductor device, the second fin protruding above a substrate, wherein the first nanostructure and the second nanostructure comprise a semiconductor material and extend parallel to a major upper surface of the substrate; forming a dielectric material around the first nanostructure and around the second nanostructure; forming a first hardmask layer around the first nanostructure in the first device region and around the second nanostructure in the second device region; after forming the first hardmask layer, removing the first hardmask layer from the second device region; and after removing the first hardmask layer from the second device region, increasing a first thickness of the dielectric material around the second nanostructure by performing an oxidation process.

[0092] Example 2 is the method of Example 1, wherein a second thickness of the dielectric material around the first nanostructure remains the same before and after the oxidation process, or is increased less than the first thickness of the dielectric material around the second nanostructure by the oxidation process.

[0093] Example 3 is the method of Example 1, wherein the dielectric material is an oxide of the semiconductor material.

[0094] Example 4 is the method of Example 3, wherein the oxidation process converts an outer portion of the second nanostructure to the dielectric material, wherein the first hardmask layer shields the first nanostructure from the oxidation process.

[0095] Example 5 is the method of Example 3, wherein performing the oxidation process comprises soaking the first nanostructure and the second nanostructure in a gas source comprising ozone.

[0096] Example 6 is the method of Example 3, wherein the oxidation process is a plasma process.

[0097] Example 7 is the method of Example 6, wherein performing the oxidation process comprises igniting a gas source into a plasma, wherein the gas source comprises oxygen, nitrous oxide gas, a mixture of nitrous oxide gas and nitrogen gas, a mixture of oxygen and nitrogen gas, a mixture of oxygen and an inert gas, or a mixture of nitrous oxide gas and an inert gas; and treating the first nanostructure and the second nanostructure with the plasma.

[0098] Example 8 is the method of Example 1, further comprising forming a high-k gate dielectric material on the dielectric material prior to forming the first hard mask layer.

[0099] Example 9 is the method of Example 8, further comprising forming a seed layer on the high-k gate dielectric material after forming the high-k gate dielectric material and prior to forming the first hard mask layer.

[0100] Example 10 is the method of Example 1, further comprising forming a second hard mask layer on the first hard mask layer in the first device region and around the second nanostructure in the second device region after removing the first hard mask layer from the second device region and prior to increasing the first thickness of the dielectric material.

[0101] Example 11 is the method of Example 1, further comprising removing the first hard mask layer from the first device region after increasing the first thickness of the dielectric material; and forming a gate electrode around the first nanostructure and around the second nanostructure.

[0102] Example 12 is the method of Example 11, further comprising forming a high-k gate dielectric material around the first nanostructure and around the second nanostructure after removing the first hard mask layer from the first device region and prior to forming the gate electrode.

[0103] Example 13 is a method of forming a semiconductor device, the method comprising: forming a first nanostructure over a first fin and forming a second nanostructure over a second fin, wherein the first fin and the second fin protrude above a substrate, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; forming an interface dielectric material around the first nanostructure and around the second nanostructure; forming a first hard mask layer over the first fin but not over the second fin, wherein the first hard mask layer covers the interface dielectric material around the first nanostructure, wherein the interface dielectric material around the second nanostructure is exposed by the first hard mask layer; after forming the first hard mask layer, performing an oxidation process, wherein a thickness of the interface dielectric material around the second nanostructure is increased after the oxidation process; and after performing the oxidation process, removing the first hard mask layer.

[0104] Example 14 is the method of Example 13, further comprising forming a gate electrode around the first nanostructure and around the second nanostructure after removing the first hard mask layer.

[0105] Example 15 is the method of example 13, wherein the interface dielectric material is an oxide of the first semiconductor material, wherein the oxidizing process converts an outer portion of the second nanostructure to the oxide of the first semiconductor material.

[0106] Example 16 is the method of example 15, wherein performing the oxidizing process comprises soaking the first and second nanostructures in an oxygen-containing gas source.

[0107] Example 17 is the method of example 13, wherein performing the oxidizing process comprises processing the first and second nanostructures using a plasma of an oxygen-containing gas source.

[0108] Example 18 is a semiconductor device comprising: a first fin and a second fin protruding above a substrate; a first nanostructure and a second nanostructure over the first fin and the second fin, respectively, wherein the first and second nanostructures comprise a first semiconductor material and extend parallel to a major upper surface of the substrate; a first interface dielectric layer around the first nanostructure and a second interface dielectric layer around the second nanostructure, wherein the second interface dielectric layer around the second nanostructure is thicker than the first interface dielectric layer around the first nanostructure; a gate dielectric layer on the first interface dielectric layer around the first nanostructure and on the second interface dielectric layer around the second nanostructure; and a gate electrode around the first nanostructure and around the second nanostructure.

[0109] Example 19 is the semiconductor device of example 18, wherein the first and second interface dielectric layers comprise an oxide of the first semiconductor material.

[0110] Example 20 is the semiconductor device of example 18, wherein individual ones of the first nanostructures have a first height measured between an upper surface of the individual first nanostructure distal from the substrate and a lower surface of the individual first nanostructure facing the substrate, and individual ones of the second nanostructures have a second height measured between an upper surface of the individual second nanostructure distal from the substrate and a lower surface of the individual second nanostructure facing the substrate, wherein the first height is greater than the second height, wherein the individual first and second nanostructures are the same vertical distance from the substrate.

Claims

1. A method for forming a semiconductor device, the method comprising: In a first device region of the semiconductor device, a first nanostructure is formed on a first fin, the first fin protruding above the substrate; In a second device region of the semiconductor device, a second nanostructure is formed on a second fin, the second fin protruding above the substrate, wherein the first nanostructure and the second nanostructure comprise semiconductor material and extend parallel to the main upper surface of the substrate; A dielectric material is formed around the first nanostructure and around the second nanostructure; A high-k gate dielectric material is formed on the dielectric material, wherein the dielectric constant of the high-k gate dielectric material is higher than that of the dielectric material. After forming the high-k gate dielectric material, a first hard mask layer is formed around the first nanostructure in the first device region and around the second nanostructure in the second device region, wherein the first hard mask layer fills the first empty space between adjacent first nanostructures and fills the second empty space between adjacent second nanostructures. After the first hard mask layer is formed, the first hard mask layer is removed from the second device region; After removing the first hard mask layer from the second device region, a second hard mask layer is formed on the first hard mask layer in the first device region and around the high-k gate dielectric material in the second device region, wherein the second hard mask layer in the second device region partially fills the space of the second void and leaves gaps between adjacent second nanostructures; and After the second hard mask layer is formed, an oxidation process is performed to increase the first thickness of the dielectric material surrounding the second nanostructure, wherein the second hard mask layer is in direct contact with the oxidant of the oxidation process during the oxidation process.

2. The method according to claim 1, wherein, The second thickness of the dielectric material surrounding the first nanostructure remains unchanged before and after the oxidation process, or is increased less by the oxidation process compared to the first thickness of the dielectric material surrounding the second nanostructure.

3. The method according to claim 1, wherein, The dielectric material is an oxide of the semiconductor material.

4. The method according to claim 3, wherein, The oxidation process converts the outer portion of the second nanostructure into the dielectric material, wherein the first hard mask layer and the second hard mask layer shield the first nanostructure from the effects of the oxidation process.

5. The method according to claim 3, wherein, Performing the oxidation process includes immersing the first nanostructure and the second nanostructure in a gas source including ozone.

6. The method according to claim 3, wherein, The oxidation process is a plasma process.

7. The method according to claim 6, wherein, Performing the oxidation process includes: The gas source is ignited into plasma, wherein the gas source includes oxygen, nitrous oxide gas, a mixture of nitrous oxide gas and nitrogen, a mixture of oxygen and nitrogen, a mixture of oxygen and an inert gas, or a mixture of nitrous oxide gas and an inert gas; and The first nanostructure and the second nanostructure are treated with the plasma.

8. The method according to claim 1, further comprising: After the high-k gate dielectric material is formed and before the first hard mask layer is formed, a conformal seed layer is formed on the high-k gate dielectric material, wherein the second hard mask layer is formed on the conformal seed layer in the second device region.

9. The method according to claim 1, further comprising: After increasing the first thickness of the dielectric material Remove the second hard mask layer; Remove the first hard mask layer from the first device region; as well as A gate electrode is formed around the first nanostructure and around the second nanostructure.

10. The method according to claim 9, wherein, The high-k gate dielectric material is formed after the removal of the second hard mask layer, after the removal of the first hard mask layer from the first device region, and before the formation of the gate electrode.

11. The method of claim 1, wherein, after the oxidation process, the first thickness of the dielectric material surrounding the second nanostructure increases along a first direction, wherein, The first direction is perpendicular to the main upper surface of the substrate and points from the substrate toward the second nanostructure.

12. The method according to claim 11, wherein, After the oxidation process, the second thickness of the dielectric material surrounding the first nanostructure is uniform and is less than the minimum first thickness of the dielectric material surrounding the second nanostructure.

13. A method of forming a semiconductor device, the method comprising: A first nanostructure is formed on a first fin, and a second nanostructure is formed on a second fin, wherein the first fin and the second fin protrude above the substrate, and wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to the main upper surface of the substrate; An interfacial dielectric material is formed around the first nanostructure and around the second nanostructure; A gate dielectric material is formed on the interface dielectric material, wherein the gate dielectric material includes a high-k dielectric material; After the gate dielectric material is formed, a first hard mask layer is formed on the first fin but not on the second fin, wherein the first hard mask layer extends along the gate dielectric material around the first nanostructure, wherein the interface dielectric material around the second nanostructure is exposed by the first hard mask layer, wherein the first hard mask layer fills the space between adjacent first nanostructures. After the first hard mask layer is formed, a second hard mask layer is formed on the first fin and the second fin, wherein the second hard mask layer extends along the first hard mask layer around the first nanostructure and along the gate dielectric material around the second nanostructure, wherein after the second hard mask layer is formed, there is an empty space between adjacent second nanostructures. After forming the second hard mask layer, an oxidation process is performed, wherein, after the oxidation process, the thickness of the interfacial dielectric material surrounding the second nanostructure is increased; and After performing the oxidation process, the first hard mask layer and the second hard mask layer are removed.

14. The method of claim 13, further comprising: After removing the first hard mask layer and the second hard mask layer, a gate electrode is formed around the first nanostructure and around the second nanostructure.

15. The method according to claim 13, wherein, The interface dielectric material is an oxide of the first semiconductor material, wherein the oxidation process converts the outer portion of the second nanostructure into an oxide of the first semiconductor material.

16. The method according to claim 15, wherein, Performing the oxidation process includes immersing the first nanostructure and the second nanostructure in an oxygen-containing gas source.

17. The method according to claim 13, wherein, Performing the oxidation process includes treating the first nanostructure and the second nanostructure using plasma containing an oxygen gas source.

18. A semiconductor device, comprising: The first and second fins protrude above the substrate; A first nanostructure and a second nanostructure are respectively located on the first fin and the second fin, wherein the first nanostructure and the second nanostructure comprise a first semiconductor material and extend parallel to the main upper surface of the substrate, and wherein, in a direction perpendicular to the main upper surface of the substrate, the height TE of the end of an individual nanostructure in the first nanostructure and the second nanostructure that is in solid contact with the source / drain region is greater than the height T of the middle portion of the nanostructure. A first interface dielectric layer and a second interface dielectric layer, the first interface dielectric layer being around the first nanostructure and the second interface dielectric layer being around the second nanostructure, wherein the second interface dielectric layer around the second nanostructure is thicker than the first interface dielectric layer around the first nanostructure. A gate dielectric layer, on the first interface dielectric layer surrounding the first nanostructure and on the second interface dielectric layer surrounding the second nanostructure; and A gate electrode is located around the first nanostructure and around the second nanostructure.

19. The semiconductor device according to claim 18, wherein, The first interface dielectric layer and the second interface dielectric layer comprise oxides of the first semiconductor material.

20. The semiconductor device according to claim 18, wherein, The first nanostructure has an individual first nanostructure having a first height measured between the upper surface of the individual first nanostructure away from the substrate and the lower surface of the individual first nanostructure facing the substrate, and the second nanostructure has an individual second nanostructure having a second height measured between the upper surface of the individual second nanostructure away from the substrate and the lower surface of the individual second nanostructure facing the substrate, wherein the first height is greater than the second height, and wherein the individual first nanostructure and the individual second nanostructure are at the same vertical distance from the substrate.

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