Phase selector and phase selection signal output method

Abstract

The present invention discloses a phase selector and a phase selection signal output method for improving the flexibility and portability of the phase selector. The phase selector includes a shift signal generating circuit, a shift circuit, and a phase selection circuit. The shift signal generating circuit counts the phase selection signal under the control of a phase shift flag signal, compares the resulting count signal with a shift count signal, and outputs a phase shift signal based on the comparison result, the phase shift flag signal, and the phase selection signal. The shift circuit changes the phase selection switch signal under the control of the phase shift signal. The phase selection circuit selects a data signal from n data signals with different phases as the phase selection signal based on the changed phase selection signal. Since the phase selection switch is changed under the control of the phase shift signal to select a data signal with a different phase as the phase selection signal, the flexibility and portability of the phase selector can be improved.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a phase selector and a phase selection signal output method. Background Art

[0002] Phase selectors with traditional structures can only implement phase selection once, or can only select a clock signal with a phase before or after a fixed phase, or can only respond to changes in a fixed phase difference. Therefore, phase selectors with traditional structures cannot meet the functional requirements of circuits with complex functions.

[0003] For example, in clock recovery and clock generation circuits, phase-locked loops (PLLs) require phase selection of multi-phase voltage-controlled oscillators to meet fractional frequency division and low jitter requirements. Some analog transistor-based circuit structures may be able to achieve slightly more complex logic requirements, but they typically suffer from large circuit scale, significant performance impacts of manufacturing processes, and numerous design flaws. Traditional phase selectors cannot meet these circuit requirements. Consequently, existing phase selectors lack flexibility and are difficult to port. Summary of the Invention

[0004] The present invention provides a phase selector and a phase selection signal output method, which are used to solve the problems in the prior art that the phase selector has poor flexibility and is not easy to transplant.

[0005] In a first aspect, an embodiment of the present invention provides a phase selector, comprising: a shift signal generating circuit, a shift circuit, and a phase selecting circuit;

[0006] The shift signal generating circuit is configured to count the phase selection signal under the control of the phase shift flag signal to obtain a count signal, compare the obtained count signal with the shift number signal, and output a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal;

[0007] The shift circuit is used to change the phase selection switch signal under the control of the phase shift signal;

[0008] The phase selection circuit is used to select a data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal, and output the selected data signal, wherein n is a positive integer.

[0009] In a possible implementation, the shift signal generating circuit includes a counting circuit, a counting comparison circuit, and a shift signal generating sub-circuit;

[0010] The counting circuit is used to count the phase selection signal under the control of the phase shift flag signal and output m counting signals;

[0011] The counting comparison circuit is used to compare the m counting signals and the m shift number signals, and output a shift number same signal indicating whether the m counting signals and the m shift number signals are the same;

[0012] The shift signal generating sub-circuit is used to perform a logic operation on the phase selection signal under the control of the shift number identical signal and the phase shift flag signal, and output the phase shift signal;

[0013] Wherein, m is a positive integer greater than 2.

[0014] In one possible implementation, the counting circuit includes a first inverter, m flip-flops, and an inverter combination;

[0015] The input end of the first inverter is used to input the phase shift flag signal, and the output end of the first inverter is connected to the R end of each trigger;

[0016] In each combination, the D terminal of the trigger is connected to the output terminal of the inverter, and the Q terminal of the trigger is connected to the input terminal of the inverter, for outputting m counting signals in sequence;

[0017] In the first combination, the CK terminal of the trigger is used to input the phase selection signal. In other combinations, the CK terminal of the trigger is connected to the output terminal of the inverter in the previous combination.

[0018] In a possible implementation, the counting and comparing circuit includes m XNOR gates and a first AND gate;

[0019] For each XEN-OR gate, the first input terminal of the XEN-OR gate is used to input a counting signal, the second input terminal of the XEN-OR gate is used to input a shift number signal corresponding to the counting signal, and the output terminal of the XEN-OR gate is connected to an input terminal of the first AND gate;

[0020] The output terminal of the first AND gate is used to output the signal having the same shift amount.

[0021] In a possible implementation, the shift signal generating subcircuit includes a voltage clamp high logic tiehi gate, a first flip-flop, a second flip-flop, and a second AND gate;

[0022] The output end of the tiehi gate is connected to the D end of the first trigger, and is used to output a first level;

[0023] The R terminal of the first flip-flop is used to input the shift number same signal, the CK terminal of the first flip-flop is used to input the phase shift flag signal, and the Q terminal of the first flip-flop is connected to the D terminal of the second flip-flop;

[0024] The R terminal of the second flip-flop is used to input a reset signal, the ck terminal of the second flip-flop is used to input the phase selection signal, and the Q terminal of the second flip-flop is connected to the first input terminal of the second AND gate;

[0025] The second input terminal of the second AND gate is used to input the phase selection signal, and the output terminal of the second AND gate is used to output the phase shift signal.

[0026] In one possible implementation, the shift circuit includes a third flip-flop, (n-1) fourth flip-flops, a second inverter, and a third inverter;

[0027] For the (n-1) fourth flip-flops, the D terminal of the first fourth flip-flop is connected to the output terminal of the third inverter for outputting the first selection switch signal, the Q terminal of the last fourth flip-flop is connected to the input terminal of the second inverter for outputting the last selection switch signal, and among the other fourth flip-flops, the Q terminal of the previous fourth flip-flop is connected to the D terminal of the next fourth flip-flop for sequentially outputting the selection switch signals, the R terminal of each fourth flip-flop is used to input a reset signal, and the CK terminal of each fourth flip-flop is used to input the phase shift signal;

[0028] The D terminal of the third trigger is connected to the output terminal of the second inverter, the Q terminal of the third trigger is connected to the input terminal of the third inverter, the R terminal of the third trigger is used to input the reset signal, and the CK terminal of the third trigger is used to input the phase shift signal.

[0029] In a possible implementation, the phase selection circuit includes m fourth inverters and m switches corresponding to each fourth inverter;

[0030] For each set of fourth inverters and switches, an input end of the fourth inverter is connected to the first control end of the switch for inputting a phase selection switch signal, and an output end of the fourth inverter is connected to the second control end of the switch;

[0031] The first end of the switch is used to input a data signal corresponding to the phase selection switch signal, and the second end of the switch is used to output the phase selection signal.

[0032] In a possible implementation, the switch includes a first switching tube and a second switching tube;

[0033] The control end of the first switching tube serves as the first control end of the switch, the first end of the first switching tube is connected to the first end of the second switching tube, and the second end of the first switching tube is connected to the second end of the second switching tube;

[0034] The control end of the second switching tube serves as the second control end of the switch.

[0035] In a second aspect, an embodiment of the present invention provides a phase selection signal output method, the method comprising:

[0036] Under the control of the phase shift flag signal, the phase selection signal is counted to obtain a count signal, and the obtained count signal is compared with the shift number signal, and a phase shift signal for controlling the phase shift is output according to the comparison result, the phase shift flag signal and the phase selection signal;

[0037] Under the control of the phase shift signal, changing the phase selection switch signal;

[0038] According to the changed phase selection signal, one data signal is selected from n data signals with different phases as the phase selection signal and output, wherein n is a positive integer greater than 2.

[0039] In one possible implementation, under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with the shift number signal, and outputting a phase shift signal for controlling the phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal, includes:

[0040] Under the control of the phase shift flag signal, counting the phase selection signal and outputting m counting signals;

[0041] comparing the m counting signals and the m shift number signals, and outputting a shift number same signal indicating whether the m counting signals and the m shift number signals are the same;

[0042] Under the control of the shift number same signal, the phase shift flag signal and the reset signal, performing a logic operation on the phase selection signal and outputting the phase shift signal;

[0043] Wherein, m is a positive integer greater than 2.

[0044] Embodiments of the present invention provide a phase selector and a phase selection signal output method, wherein the phase selector includes a shift signal generating circuit, a shift circuit, and a phase selection circuit. The shift signal generating circuit, under the control of a phase shift flag signal, counts the phase selection signal to obtain a count signal, compares the count signal with a shift number signal, and outputs a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal. The shift circuit, under the control of the phase shift signal, changes a phase selection switch signal. The phase selection circuit, based on the changed phase selection signal, selects a data signal from n data signals with different phases as the phase selection signal and outputs the signal, where n is a positive integer greater than 2. Because the phase selector can generate a phase shift signal for controlling phase shift, the phase selection switch can be changed under the control of the phase shift signal, thereby selecting data signals with different phases as the phase selection signal. Phase selection can be performed according to actual needs, and multiple phase selections can be achieved. The phase of the output phase selection signal is not fixed, thereby improving the flexibility and portability of the phase selector. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic structural diagram of a phase selector provided in an embodiment of the present invention;

[0047] Figure 2 A schematic structural diagram of another phase selector provided by an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of a counting circuit provided by an embodiment of the present invention;

[0049] Figure 4 A schematic diagram of a counting and comparison circuit provided by an embodiment of the present invention;

[0050] Figure 5 A schematic diagram of a shift signal generating sub-circuit provided by an embodiment of the present invention;

[0051] Figure 6 A schematic diagram of a shift circuit provided by an embodiment of the present invention;

[0052] Figure 7 A schematic diagram of a phase selection circuit provided by an embodiment of the present invention;

[0053] Figure 8 A schematic diagram of another counting circuit provided by an embodiment of the present invention;

[0054] Figure 9 A schematic diagram of another counting and comparison circuit provided by an embodiment of the present invention;

[0055] Figure 10 A schematic diagram of another shift signal generating sub-circuit provided by an embodiment of the present invention;

[0056] Figure 11 A schematic diagram of another shift circuit provided by an embodiment of the present invention;

[0057] Figure 12 A schematic diagram of another phase selection circuit provided by an embodiment of the present invention;

[0058] Figure 13 A schematic diagram of a timing signal provided by an embodiment of the present invention;

[0059] Figure 14 A schematic flow chart of a phase selection signal output method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described herein are merely some, rather than all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0061] In order to solve the technical problems of poor flexibility and difficulty in porting of phase selectors in the prior art, an embodiment of the present invention provides a phase selector that can accurately select the phase and respond to the phase change requirement within each clock cycle, so that the next output clock selects the signal of the next phase based on the phase at the end of the previous clock cycle. After several shift selections, the data signal with the target phase is selected, thereby improving the flexibility and portability of the phase selector.

[0062] like Figure 1 As shown, a phase selector provided by an embodiment of the present invention includes a shift signal generating circuit 101, a shift circuit 102 and a phase selection circuit 103;

[0063] The shift signal generating circuit 101 is configured to count the phase selection signal phase_mux under the control of the phase shift flag signal clk to obtain a count signal Q, compare the obtained count signal Q with the shift number signal num, and output a phase shift signal phase_shift for controlling phase shift based on the comparison result, the phase shift flag signal clk, and the phase selection signal phase_mux.

[0064] The shift circuit 102 is used to change the phase selection switch signal sel under the control of the phase shift signal phase_shift;

[0065] The phase selection circuit 103 is configured to select a data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal sel, and output the selected data signal, wherein n is a positive integer greater than 2.

[0066] In an embodiment of the present invention, a shift signal generating circuit, under the control of a phase shift flag signal, counts a phase selection signal to obtain a count signal, compares the count signal with a shift count signal, and outputs a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal. Under the control of the phase shift signal, the shift circuit changes a phase selection switch signal. Based on the changed phase selection signal, the phase selection circuit selects a data signal from n data signals with different phases as the phase selection signal and outputs the signal, where n is a positive integer greater than 2. Because the phase selector can generate a phase shift signal for controlling phase shift, the phase selection switch can be changed under the control of the phase shift signal, thereby selecting data signals with different phases as the phase selection signal. Phase selection can therefore be performed according to actual needs, and multiple phase selections can be achieved. Furthermore, the phase of the output phase selection signal is not fixed, thereby improving the flexibility and portability of the phase selector.

[0067] In the embodiment of the present invention, the phase selection signal output by the phase selection circuit is used as the input of the shift signal generating circuit, so that when there are multiple phase shift flag signal clk cycles requiring phase selection, the counting and shifting of the next clk cycle can be performed.

[0068] In a specific implementation, the shift signal generating circuit 101 may include a counting circuit 1011, a counting comparison circuit 1012 and a shift signal generating sub-circuit 1013. Figure 2 shown.

[0069] from Figure 2As can be seen from FIG, the counting circuit 1011 is used to count the phase selection signal phase_mux under the control of the phase shift flag signal clk, and output m counting signals Qm-1...Q1, Q0;

[0070] The counting circuit 1011 is used to count the phase selection signal phase_mux and output m counting signals Qm-1...Q1, Q0, where the phase shift flag signal clk is a periodic signal that starts phase shifting and is a relatively low-frequency signal; the phase selection signal phase_mux is a signal output by the phase selection circuit and has a higher frequency than the phase shift flag signal clk. The phase selection signal phase_mux is the output signal of the entire phase selector and is the final selection output result. If there are multiple phase shift flag signal clk cycles that require phase selection, the phase selection signal phase_mux serves as the input signal of the counting circuit 1011 to count and shift the next phase shift flag signal clk cycle, and so on.

[0071] When the phase shift flag signal clk is high, the counting of the number of cycles of the phase selection signal phase_mux and the phase selection action are started. The counting signals Qm-1...Q1, Q0 are counted from 0...00, up to 1...11, and converted to decimal, up to 2 m -1, after exceeding the maximum counting range, it returns to 0...00 and starts counting again. The number of counted bits and the number of bits to be shifted are both m, where m is any positive integer. When the phase shift flag signal clk is low, counting stops and the output signal remains unchanged.

[0072] The counting comparison circuit 1012 is used to compare the m counting signals Qm-1...Q1, Q0 and the m shift number signals num <m-1>……num <1> 、num <0> , outputting a shift number same signal representing whether the m counting signals and the m shift number signals are the same, where m is a positive integer.

[0073] Input m counting signals Qm-1...Q1, Q0 and m shift number signals num <m-1>……num <1> 、num <0> , output the same shift number signal num_same; among them, the shift number signal num <0> 、num <1> ……num <m-1>The number of phases that need to be moved is from the lowest bit to the highest bit. If counted in binary, the number of phases that need to be moved = 2 m-1 +……+2 1 +2 0 =2 m -1. If the m counting signals and the m shift number signals are the same, the output shift number same signal num_same is high, indicating that the number of shifts has reached the target number. If the m counting signals and the m shift number signals are different, the output shift number same signal num_same is low.

[0074] In an embodiment of the present invention, the counting signal and the shift number signal are in one-to-one correspondence. To determine whether the m counting signals and the m shift number signals are the same, that is, to determine whether each corresponding counting signal and the shift number signal are the same, if all corresponding counting signals and the shift number signals are the same, it means that the m counting signals and the m shift number signals are the same.

[0075] For example, there are 4 counting signals and 4 shift number signals, namely Q3, Q2, Q1, Q0 and num <3> 、num <2> 、num <1> 、num <0> , if Q3 and num <3> Same, Q2 and num <2> Same, Q1 and num <1> Same, Q0 and num <0> If they are the same, it means that the 4 counting signals and the 4 shift number signals are the same.

[0076] It should be noted that when the counting signal and the shift number signal are compared, the level signals are compared, such as high level and low level. If the corresponding counting signal and shift number signal are both high level or both low level, it means that the corresponding counting signal and shift number signal are the same.

[0077] The shift signal generating sub-circuit 1013 is used to perform a logic operation on the phase selection signal phase_mux under the control of the shift number identical signal num_same and the phase shift flag signal clk, and output a phase shift signal phase_shift.

[0078] The phase shift flag signal clk, the phase selection signal phase_mux and the shift number same signal num_same are input, and the phase shift signal phase_shift is output. That is, under the control of the phase shift flag signal clk and the shift number same signal num_same, the phase shift signal phase_shift is output according to the phase selection signal phase_mux, wherein the phase shift signal phase_shift is used to change the phase selection switch signal sel.

[0079] Specifically, when the phase shift flag signal clk is at a high level, if the number of cycles of the phase selection signal phase_mux is the same as the number of phases to be shifted, the shift number same signal num_same output by the counter comparison circuit 1012 is at a high level, indicating that the target number of shifts has been reached. The shift number same signal num_same controls the output phase shift signal phase_shift of the subsequent shift signal generation sub-circuit. When the number of cycles of the phase selection signal phase_mux has not yet reached the number of phases to be shifted, the phase shift signal phase_shift continuously flips from logic 0 to logic 1 and from logic 1 to logic 0. The flipping number is the number of phase shifts required within the phase shift flag signal clk period. Because the phase shift signal phase_shift is derived from a logical operation of the phase selection signal phase_mux, the flipping frequency of the phase shift signal phase_shift is the same as that of the phase selection signal phase_mux. When the number of cycles of the phase selection signal phase_mux reaches the number of phases to be shifted, the shift number same signal num_same causes the phase shift signal phase_shift to become 0, indicating the end of the shifting operation.

[0080] The shift circuit 102 is configured to change the phase selection switch signal sel under the control of the phase shift signal phase_shift.

[0081] Among them, the phase selection switch signal sel can be n, sel <0> 、sel <1> ……sel <n>, change the phase selection switch signal, that is, change sel <0> 、sel <1> ……sel <n>level signal.

[0082] Specifically, the phase shift signal phase_shift is used as the excitation signal of the shift circuit. When the phase shift signal phase_shift changes from logic 0 to logic 1, that is, from a low level to a high level, the output signal phase selection switch signal sel of the shift circuit changes from logic 0 to logic 1. <0> , sel <1> …sel <n>If changes occur, they will shift in sequence based on the last end.

[0083] For example, the last shift ended with sel <3> =1, the other sel signals are 0, if num <0> =0,num <1> =1, and the rest of the num signals are 0, indicating that in this shift, it is necessary to output the signal of the two phases behind the last output data signal. Then the phase shift signal phase_shift will produce two level flips, that is, there are two flip cycles. When the phase shift signal phase_shift changes from low level to high level for the first time, it will occur: sel <3> =0,sel <4> =1, the rest of sel is 0, when the phase shift signal phase_shift changes from low level to high level for the second time, sel will occur: <3> =0,sel <4> =0,sel <5> =1 and the rest of sel are 0, and the shift is completed.

[0084] It should be noted that the shifting in the embodiment of the present invention is performed sequentially rather than abruptly jumping from one phase to another, which can reduce jitter.

[0085] The phase selection circuit 103 is used to select a data signal from n data signals phase with different phases as the phase selection signal phase_mux according to the changed phase selection signal sel, and output it, where n is a positive integer greater than 2. That is, the phase selection circuit 103 inputs n phase selection switch signals sel <0> 、sel <1> ……sel <n>and n data signal phases <0> , phase <1> ,……phase <n>, output phase selection signal phase_mux.

[0086] Specifically, sel <0> 、sel <1> ……sel <n>As a switch to select the phase, the data signal phase <0> , phase <1> ,……phase <n>For data signals with different phases, it is necessary to select a multi-phase same-frequency signal. One phase selection switch corresponds to a data signal of one phase: when sel <0> =1, the output signal phase_mux of the phase selection module selects phase <0> As output, when sel <1> =1, the output signal phase_mux of the phase selection module selects phase <1> As output... when sel <n>=1, the output signal phase_mux of the phase selection module selects phase <n>As the output, the output is then used as the input signal for the next phase selection. When the next clk signal comes, the shift is counted again and a new phase is selected, thereby realizing the function of continuously selecting any phase.

[0087] As in the example above, when it is necessary to output the signal of the two phases after the last output data signal, if the last shift is ended by sel <3> =1, and the other sel signals are 0, then the last time phase_mux selected phase <3> As output, when the clk signal comes, the phase_mux selects phase from low level to high level for the first time in phase_shift <4> As output, phase_mux selects phase_shift from low to high for the second time. <5> As the output, so the phase_mux falls on the phase at the end of the shift <5> superior.

[0088] If sel <0> =sel <1> =…=sel <n>= 0, then phase_mux keeps the phase of the previous cycle unchanged. Because the phase selection switches correspond one-to-one to the data signals of different phases, their number is the same.

[0089] It should be noted that, in the phase selector provided by the embodiment of the present invention, at the initial moment, the phase selection signal selects a preset data signal in the data signal, such as the data signal phase <0> Specifically, it can be set according to the specific structure of the circuit.

[0090] The various circuits in the embodiments of the present invention are described below.

[0091] like Figure 3 FIG. 1 is a schematic diagram of a counting circuit provided by an embodiment of the present invention. The counting circuit 1011 includes a first inverter INV1, m flip-flops, and an inverter combination 10111;

[0092] The input end of the first inverter INV1 is used to input the phase shift flag signal clk, and the output end of the first inverter INV1 is connected to the R end of each flip-flop DFF;

[0093] In each combination, the D terminal of the flip-flop DFF is connected to the output terminal of the inverter INV, and the Q terminal of the flip-flop DFF is connected to the input terminal of the inverter INV, for sequentially outputting m counting signals Qm-1...Q1, Q0;

[0094] In the first combination, the CK terminal of the flip-flop DFF is used to input the phase selection signal phase_mux. In other combinations, the CK terminal of the flip-flop DFF is connected to the output terminal of the inverter INV in the previous combination.

[0095] like Figure 4 FIG. 1 is a schematic diagram of a counting and comparing circuit according to an embodiment of the present invention. The counting and comparing circuit 1012 includes m XNOR gates Y and a first AND gate AND1.

[0096] For each XENO gate, a first input terminal of the XENO gate is used to input a counting signal Q, a second input terminal of the XENO gate is used to input a shift number signal num corresponding to the counting signal, and an output terminal of the XENO gate is connected to an input terminal of the first AND gate AND1;

[0097] An output terminal of the first AND gate AND1 is used to output a shift number same signal num_same.

[0098] like Figure 5 , which is a schematic diagram of a shift signal generating sub-circuit provided by an embodiment of the present invention, wherein the shift signal generating sub-circuit 1013 includes a tiehi gate, a first flip-flop DFF1, a second flip-flop DFF2, and a second AND gate AND2;

[0099] The output end of the tiehi gate is connected to the D end of the first flip-flop DFF1, for outputting a first level;

[0100] The R terminal of the first flip-flop DFF1 is used to input the shift number same signal num_same, the CK terminal of the first flip-flop DFF1 is used to input the phase shift flag signal clk, and the Q terminal of the first flip-flop DFF1 is connected to the D terminal of the second flip-flop DFF2;

[0101] The R terminal of the second flip-flop DFF2 is used to input the reset signal rst, the CK terminal of the second flip-flop DFF2 is used to input the phase selection signal phase_mux, and the Q terminal of the second flip-flop DFF2 is connected to the first input terminal of the second AND gate AND2;

[0102] A second input terminal of the second AND gate AND2 is used to input the phase selection signal phase_mux, and an output terminal of the second AND gate phase_mux is used to output the phase shift signal phase_shift.

[0103] like Figure 6 , which is a schematic diagram of a shift circuit provided by an embodiment of the present invention, the shift circuit includes a third flip-flop DFF3, (n-1) fourth flip-flops DFF4, a second inverter INV2, and a third inverter INV3;

[0104] For the (n-1) fourth flip-flops DFF4, the D terminal of the first fourth flip-flop DFF4 is connected to the output terminal of the third inverter INV3, and is used to output the first selection switch signal sel <0> The Q end of the last fourth flip-flop DFF4 is connected to the input end of the second inverter INV2, and is used to output the last selection switch signal sel <n-1>In the other fourth flip-flops DFF4, the Q end of the previous fourth flip-flop DFF4 is connected to the D end of the next fourth flip-flop DFF4, and is used to sequentially output the selection switch signal sel <1> 、sel <2> ……sel <n-2>, the R terminal of each fourth flip-flop DFF4 is used to input the reset signal rst, and the CK terminal of each fourth flip-flop DFF4 is used to input the phase shift signal phase_shift;

[0105] The D terminal of the third flip-flop DFF3 is connected to the output terminal of the second inverter INV2, the Q terminal of the third flip-flop DFF3 is connected to the input terminal of the third inverter INV3, the R terminal of the third flip-flop DFF3 is used to input the reset signal rst, and the CK terminal of the third flip-flop DFF3 is used to input the phase shift signal phase_shift.

[0106] like Figure 7 , which is a schematic diagram of a phase selection circuit provided by an embodiment of the present invention, the phase selection circuit 103 includes m fourth inverters INV4 and m switches K corresponding to each fourth inverter INV4;

[0107] For each set of fourth inverters and switches, an input end of the fourth inverter INV4 is connected to the first control end of the switch K for inputting the phase selection switch signal sel, and an output end of the fourth inverter INV4 is connected to the second control end of the switch K;

[0108] The first end of the switch K is used to input the data signal phase corresponding to the phase selection switch signal sel, and the second end of the switch K is used to output the phase selection signal phase_mux.

[0109] In a specific implementation, the switch K may include a first switch tube M1 and a second switch tube M2;

[0110] The control end of the first switch tube M1 serves as the first control end of the switch K. The first end of the first switch tube M1 is connected to the first end of the second switch tube M2, and the second end of the first switch tube M1 is connected to the second end of the second switch tube M2.

[0111] The control end of the second switch tube M2 serves as the second control end of the switch K.

[0112] It should be noted that Figure 7 The sel<0:m-1> in the code represents sel <0> 、sel <1> 、sel <2> ……sel <m-1>, that is, there are m inverters, and similarly, there are m switches K.

[0113] For ease of understanding, the following description is given with reference to specific embodiments.

[0114] The following is a 3-bit binary counter, the maximum number of phases to be moved is 7, and the maximum number of phases to be selected is 8 (phase <0> ~phase <7> ) is used as an example to illustrate the embodiment of the present invention.

[0115] like Figure 8 FIG. 1 is a schematic diagram of a counting circuit according to an embodiment of the present invention. Figure 8 In the embodiment, the counting circuit 1011 includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a fifth flip-flop DFF5, a sixth flip-flop DFF6 and a seventh flip-flop DFF7, wherein the input terminal of the fourth inverter INV4 is input with the phase shift flag signal clk, the output terminal of the fourth inverter INV4 is connected with the R terminal of the fifth flip-flop DFF5, the R terminal of the sixth flip-flop DFF6 and the R terminal of the seventh flip-flop DFF7, the D terminal of the fifth flip-flop DFF5 is connected with the output terminal of the fifth inverter INV5 and the CK terminal of the sixth flip-flop DFF6, and the D terminal of the fifth flip-flop DFF5 is connected with the output terminal of the fifth inverter INV5 and the CK terminal of the sixth flip-flop DFF6. The CK terminal of FF5 inputs the phase selection signal phase_mux, the Q terminal of the fifth flip-flop DFF5 is connected to the input terminal of the fifth inverter INV5, and is used to output the counting signal Q0; the D terminal of the sixth flip-flop DFF6 is connected to the output terminal of the sixth inverter INV6 and the CK terminal of the seventh flip-flop DFF7, and the Q terminal of the sixth flip-flop DFF6 is connected to the input terminal of the sixth inverter INV6, and is used to output the counting signal Q1; the D terminal of the seventh flip-flop DFF7 is connected to the output terminal of the seventh inverter INV7, and the Q terminal of the seventh flip-flop DFF7 is connected to the input terminal of the seventh inverter INV7, and is used to output the counting signal Q2.

[0116] The counting circuit consists of four inverters and three D-type flip-flops, each connected end-to-end with an inverter to form a divide-by-two structure. The input signals to the counting circuit are the phase shift flag signal clk and the phase select signal phase_mux. The output signals are the counting signals Q2, Q1, and Q0, where Q2 is the most significant bit and Q0 is the least significant bit.

[0117] The principle of a 3-bit binary counter is to divide the frequency by two. The frequency of Q0 is half that of phase_mux, the frequency of Q1 is half that of Q0, and the frequency of Q2 is half that of Q1. clkb is the inverted version of clk and is connected to the reset terminals R of the three flip-flops. The reset terminals R of the three D flip-flops are all active high. When reset R is 1, the Q output of the D flip-flop is 0. That is, when clk = 1 (clkb = 0), the phase select signal phase_mux arrives (high), and counting begins. When clk = 0 (clkb = 1), Q2 = Q1 = Q0 = 0, and counting stops.

[0118] like Figure 9 FIG. 1 is a schematic diagram showing the structure of a counting and comparison circuit provided by an embodiment of the present invention. Figure 9 As shown, the counting comparison circuit may include a first XNOR gate Y1, a second XNOR gate Y2, a third XNOR gate Y3 and a three-input AND gate AND3, wherein the first input terminal of the first XNOR gate Y1 inputs the counting signal Q0, and the second input terminal of the first XNOR gate Y1 inputs the shift number signal num <0> The output end of the first XOR gate Y1 is connected to the first input end of the three-input AND gate AND3, the first input end of the second XOR gate Y2 inputs the counting signal Q1, and the second input end of the second XOR gate Y2 inputs the shift number signal num <1> The output end of the second XOR gate Y2 is connected to the second input end of the three-input AND gate AND3, the first input end of the third XOR gate Y3 inputs the counting signal Q2, and the second input end of the third XOR gate Y3 inputs the shift number signal num <2> The output end of the third XNOR gate Y3 is connected to the third input end of the three-input AND gate AND3, and the output end of the three-input AND gate AND3 is used to output the shift number same signal num_same.

[0119] The counting comparison circuit consists of three two-input XNOR gates and one three-input AND gate. The input signal of the counting comparison circuit is the shift number signal num <2> 、num <1> 、num <0> , counting signals Q2, Q1, Q0, the output signal is the shift number signal num_same. When the level of any bit of the shift number signal and the counting signal is different, it means that their values are not exactly the same. At this time, the XOR gate will output 0, and the output signal num_same is also 0. Only when each bit of the shift number signal and the counting signal is equal, that is, num <2> =Q2,num <1> =Q1,num <0> =Q0, indicating that the number of phase_mux cycles has reached the target shift number. The levels of each bit of the count signal and the shift number signal are the same. The outputs of the three XNOR gates are all 1, and the output num_same of the three-input NAND gate is 1.

[0120] It should be noted that the present invention only provides implementation plans of a counting circuit and a counting comparison circuit. In specific applications, the counter and counting comparison may be expanded according to actual needs, or other counting and counting comparison schemes may be used.

[0121] In this embodiment of the present invention, the shift signal generation circuit serves as a crucial intermediate link. Its windowing mechanism, along with the preceding counting circuit, counting and comparison circuit, and subsequent shift circuit, is crucial. The shift signal generation circuit determines when to begin phase shifting and how much to shift. The phase shift signal, phase_shift, is the key signal for initiating shift operations and phase selection.

[0122] like Figure 10 FIG. 1 is a schematic diagram of a structure of a shift signal generating sub-circuit provided by an embodiment of the present invention, Figure 10 It can be seen that the shift signal generating sub-circuit may include a tiehi gate, an eighth flip-flop DFF8, a ninth flip-flop DFF9 and a two-input AND gate AND4, wherein the output end of the tiehi gate is connected to the D end of the eighth flip-flop DFF8, the R end of the eighth flip-flop DFF8 is input with the shift number same signal num_same, the CK end of the eighth flip-flop DFF8 is input with the phase shift flag signal clk, the Q end of the eighth flip-flop DFF8 is connected to the D end of the ninth flip-flop DFF9, the R end of the ninth flip-flop DFF9 is input with the reset signal rst, the CK end of the ninth flip-flop DFF9 is input with the phase selection signal phase_mux, the Q end of the ninth flip-flop DFF9 is connected to the first input end of the two-input AND gate AND4, the second input end of the two-input AND gate AND4 is input with the phase selection signal phase_mux, and the output end of the two-input AND gate AND4 outputs the phase shift signal phase_shift.

[0123] The shift signal generation circuit consists of two D flip-flops, a tiehi gate, and a two-input AND gate. The tiehi gate always outputs a high level, tie_hi, which is fed into the D input of the eighth flip-flop DFF8. The reset terminal of the eighth flip-flop DFF8 is connected to the num_same signal output by the counter comparator circuit. When num_same is 0, the shift reset signal shift_rst remains the same as the clk signal. When num_same is 1, shift_rst becomes 0. The function of the eighth flip-flop DFF8 is to create a window for shifting. This window starts and ends when clk transitions from low to high and ends when num_same returns to 1.

[0124] The D input of the ninth flip-flop DFF9 is connected to shift_rst. Its reset terminal R is connected to the reset signal rst for the entire circuit. Its ck terminal is connected to the phase select signal phase_mux. The Q output of the ninth flip-flop DFF9 outputs the shift reset delay signal shift_rstd. The function of the ninth flip-flop DFF9 is to beat the shift reset signal shift_rst with the higher-frequency phase_mux, exposing the complete high-speed signal within the window created by the shift reset signal shift_rst and preventing errors in the number of shifted phases. Finally, a logical AND operation is performed on phase_mux and shift_rstd to generate the phase-shift signal phase_shift.

[0125] like Figure 11 FIG. 1 is a schematic diagram of a structure of a shift circuit provided by an embodiment of the present invention, Figure 11 As can be seen from the figure, the shift circuit may include a tenth flip-flop DFF10, an eleventh flip-flop DFF11, a twelfth flip-flop DFF12, a thirteenth flip-flop DFF13, a fourteenth flip-flop DFF14, a fifteenth flip-flop DFF15, a sixteenth flip-flop DFF16, a seventeenth flip-flop DFF17, an eighth inverter INV8 and a ninth inverter INV9, wherein the R terminal of each flip-flop inputs a reset signal rst, the CK terminal of each flip-flop inputs a phase shift signal phase_shift, the D terminal of the tenth flip-flop DFF10 is connected to the output terminal of the eighth inverter INV8, the Q terminal of the tenth flip-flop DFF10 is connected to the input terminal of the ninth inverter INV9, and the output terminal of the ninth inverter INV9 is connected to the D terminal of the eleventh flip-flop DFF11 for outputting a phase selection switch signal sel <0> The Q end of the eleventh flip-flop DFF11 is connected to the D end of the twelfth flip-flop DFF12 to output the phase selection switch signal sel <1> The Q end of the twelfth flip-flop DFF12 is connected to the D end of the thirteenth flip-flop DFF13 to output the phase selection switch signal sel <2> The Q terminal of the thirteenth flip-flop DFF13 is connected to the D terminal of the fourteenth flip-flop DFF14, and is used to output the phase selection switch signal sel <3> The Q terminal of the fourteenth flip-flop DFF14 is connected to the D terminal of the fifteenth flip-flop DFF15, and is used to output the phase selection switch signal sel <4> The Q terminal of the fifteenth flip-flop DFF15 is connected to the D terminal of the sixteenth flip-flop DFF16 to output the phase selection switch signal sel <5> The Q terminal of the sixteenth flip-flop DFF16 is connected to the D terminal of the seventeenth flip-flop DFF17 to output the phase selection switch signal sel <6> The Q terminal of the seventeenth flip-flop DFF17 is connected to the input terminal of the eighth inverter INV8, and is used to output the phase selection switch signal sel <7> .

[0126] Figure 11 The shift circuit in the example consists of eight D flip-flops and two inverters, which are connected end to end in a closed loop to achieve cyclic shifting. The ck terminal of all D flip-flops is connected to the phase shift signal phase_shift generated by the shift signal generating circuit, and the reset R terminal of all D flip-flops is connected to the reset signal rst of the entire circuit. The output signal generated by the shift circuit is the phase selection switch signal sel. <0> , sel <1> , sel <2> , sel <3> , sel <4> , sel <5> , sel <6> , sel <7> , control the corresponding phase signal as the output result.

[0127] like Figure 12 FIG. 1 is a schematic diagram of a phase selection circuit according to an embodiment of the present invention. Figure 12 It can be seen that the phase selection circuit may include eight inverters and eight switches. Each switch may be composed of a pair of complementary MOS tube transmission gates. Each pair of complementary MOS tube transmission gates is composed of a pmos tube and an nmos tube. The purpose of using complementary switches is to prevent the gate voltage of a single MOS tube from being less than the threshold voltage and being difficult to turn on.

[0128] The phase selection switch signal sel<0:7> is converted into the phase selection switch inverse signal selb<0:7> after passing through the inverter. The high and low levels of sel<0:7> and selb<0:7> are opposite, so the MOSFETs of the transmission switches can be controlled to turn on and off at the same time: when sel<0:7> is on, the MOSFETs of the transmission switches can be controlled to turn on and off at the same time. <0> =1, the rest sel=0, that is, selb <0> =0, otherwise selb=1, then sel <0> and selb <0> The pmos and nmos tubes of the first switch connected are turned on, and the other transmission gate switches are turned off. The phase selection signal phase_mux outputs the first phase data signal phase <0> When the other phase selection switch signals are high, sel, selb, and phase correspond to each other. The input of each switch is connected to the data signal phase<0:7> of a different phase, and the outputs of all switches are connected together to form the phase selection signal phase_mux. Only one switch is turned on at a time, so only one phase of the data signal is selected.

[0129] The following combination Figure 13 The timing diagram in Figures 8 to 12 The specific embodiment is described with reference to the circuit diagram of FIG.

[0130] Figure 13 For the above Figures 8 to 12 Corresponding signal timing diagram. phase <0> to phase <7> There are eight data signals with different phases. The reset signal rst of the entire circuit is low before the circuit works, that is, the controlled D flip-flop works normally. When the phase shift flag signal clk is high, the counter module starts counting. At the initial moment, the phase selection signal phase_mux selects phase <0> Signal. Shift number signal num at time T1 <2> num <1> num <0> =010, the phase selection signal phase_mux has the first rising edge, the counting signal Q2Q1Q0=001, at time T2 the phase selection signal phase_mux has the second rising edge, the counting signal Q2Q1Q0=010, at this time Q2=num <2> , Q1=num <1> , Q0=num <0> , the shift number same signal num_same = 1.

[0131] When clk is high, the shift reset signal shift_rst is high. When num_same=1, shift_rst is low. The shift reset delay signal shift_rstd is the result of one beat of shift_rst delay. The phase shift signal phase_shift generates two high levels at time T1 and time T2 respectively. After the shift module receives these two high levels, sel <1> At T1, it becomes 1, and phase_mux selects phase at T2. <1> , sel <2> At T2, it becomes 1, and phase_mux selects phase at T3. <2> , then sel <2> Keep the high level unchanged, phase_mux keeps phase <2> Output, waiting for the arrival of the next phase shift flag signal clk. At T4, the phase shift flag signal clk is low, and the counter module Q2Q1Q0 stops counting, which can save power consumption. At T5, the shift number signal num <2> num <1> num <0> =101, when the counting signal Q2Q1Q0 reaches 101, num_same=1, phase_shift generates 5 high levels at T5, T6, T7, T8, and T9 respectively. phase_mux selects phase at T6 <3> , select phase at T7 <4> , select phase in T8 <5> , select phase at T9 <6> , select phase at T10 <7> , then the phase selection switch signal sel <7> Keep it at 1, phase_mux keeps phase <7> At time T11, the phase shift flag signal clk is at a low level, and the counter module Q2Q1Q0 stops counting.

[0132] It should be noted that when the required shift number signal num <2> num <1> num <0> =000, the phase selection signal phase_mux maintains the previous phase output unchanged.

[0133] The shift circuit proposed in the present invention can shift cyclically. In the embodiment, the phase selection signal is shifted to the data of the next phase each time. If it is necessary to shift to the data of the previous phase, the number of shifts can be increased. For example, if the output result is to be shifted from phase <5> Move to phase <4> , you can phase <5> →phase <6> →phase <7> →phase <0> →phase <1> →phase <2> →phase <3> →phase <4> .

[0134] The phase selector provided by the present invention can achieve the function of continuously selecting any phase, that is, based on the phase at the end of the previous clock cycle, the next output clock increases any phase to achieve the purpose of accurately selecting the phase. The circuit structure is simple and the implementation method is flexible.

[0135] Based on the same inventive concept, an embodiment of the present invention further provides a phase signal selection method. The implementation of the method may refer to the implementation of the phase selector, and the repeated parts will not be repeated.

[0136] like Figure 14 As shown, a phase selection signal output method provided by an embodiment of the present invention includes the following steps:

[0137] S1401, under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with the shift number signal, and outputting a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal;

[0138] S1402, changing the phase selection switch signal under the control of the phase shift signal;

[0139] S1403 . Select one data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal, and output the selected data signal, where n is a positive integer greater than 2.

[0140] Optionally, under the control of the phase shift flag signal, counting the phase selection signal to obtain a count signal, comparing the obtained count signal with the shift number signal, and outputting a phase shift signal for controlling the phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal, includes:

[0141] Under the control of the phase shift flag signal, counting the phase selection signal and outputting m counting signals;

[0142] comparing the m counting signals and the m shift number signals, and outputting a shift number same signal indicating whether the m counting signals and the m shift number signals are the same;

[0143] Under the control of the shift number same signal, the phase shift flag signal and the reset signal, performing a logic operation on the phase selection signal and outputting the phase shift signal;

[0144] Wherein, m is a positive integer greater than 2.

[0145] Embodiments of the present invention provide a phase selector and a phase selection signal output method. Under the control of a phase shift flag signal, a shift signal generating circuit counts the phase selection signal to obtain a count signal, compares the count signal with a shift number signal, and outputs a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal. Under the control of the phase shift signal, the shift circuit changes a phase selection switch signal. Based on the changed phase selection signal, the phase selection circuit selects a data signal from n data signals with different phases as the phase selection signal and outputs it, where n is a positive integer greater than 2. Because the phase selector can generate a phase shift signal for controlling phase shift, the phase selection switch can be changed under the control of the phase shift signal, thereby selecting data signals with different phases as the phase selection signal. Phase selection can therefore be performed according to actual needs, and multiple phase selections can be achieved. Furthermore, the phase of the output phase selection signal is not fixed, thereby improving the flexibility and portability of the phase selector.

[0146] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A phase selector, characterized in that: include: shift signal generating circuit, shift circuit and phase selecting circuit; The shift signal generating circuit is configured to count the phase selection signal under the control of the phase shift flag signal to obtain a count signal, compare the obtained count signal with the shift number signal, and output a phase shift signal for controlling phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal; The shift circuit is used to change the phase selection switch signal under the control of the phase shift signal; The phase selection circuit is configured to select a data signal from n data signals with different phases as the phase selection signal according to the changed phase selection signal, and output the selected data signal, wherein n is a positive integer; Wherein, the shift signal generating circuit includes a counting circuit, a counting comparison circuit and a shift signal generating sub-circuit; The counting circuit is used to count the phase selection signal under the control of the phase shift flag signal and output m counting signals; The counting comparison circuit is used to compare the m counting signals and the m shift number signals, and output a shift number same signal indicating whether the m counting signals and the m shift number signals are the same; The shift signal generating sub-circuit is configured to perform a logic operation on the phase selection signal under the control of the shift number identical signal and the phase shift flag signal, and output the phase shift signal; Wherein, m is a positive integer greater than 2; The shift signal generating sub-circuit includes a voltage clamp high logic tiehi gate, a first flip-flop, a second flip-flop and a second AND gate; The output end of the tiehi gate is connected to the D end of the first trigger, and is used to output a first level; The R terminal of the first flip-flop is used to input the shift number same signal, the CK terminal of the first flip-flop is used to input the phase shift flag signal, and the Q terminal of the first flip-flop is connected to the D terminal of the second flip-flop; The R terminal of the second flip-flop is used to input a reset signal, the ck terminal of the second flip-flop is used to input the phase selection signal, and the Q terminal of the second flip-flop is connected to the first input terminal of the second AND gate; The second input terminal of the second AND gate is used to input the phase selection signal, and the output terminal of the second AND gate is used to output the phase shift signal.

2. The phase selector according to claim 1, wherein The counting circuit includes a first inverter, m flip-flops and an inverter combination; The input end of the first inverter is used to input the phase shift flag signal, and the output end of the first inverter is connected to the R end of each trigger; In each combination, the D terminal of the trigger is connected to the output terminal of the inverter, and the Q terminal of the trigger is connected to the input terminal of the inverter, for outputting m counting signals in sequence; In the first combination, the CK terminal of the trigger is used to input the phase selection signal. In other combinations, the CK terminal of the trigger is connected to the output terminal of the inverter in the previous combination.

3. The phase selector according to claim 1, wherein The counting and comparing circuit includes m XNOR gates and a first AND gate; For each XEN-OR gate, the first input terminal of the XEN-OR gate is used to input a counting signal, the second input terminal of the XEN-OR gate is used to input a shift number signal corresponding to the counting signal, and the output terminal of the XEN-OR gate is connected to an input terminal of the first AND gate; The output terminal of the first AND gate is used to output the signal having the same shift amount.

4. The phase selector according to claim 1, wherein: The shift circuit includes a third trigger, n-1 fourth triggers, a second inverter and a third inverter; For the n-1 fourth flip-flops, the D terminal of the first fourth flip-flop is connected to the output terminal of the third inverter for outputting the first selection switch signal, the Q terminal of the last fourth flip-flop is connected to the input terminal of the second inverter for outputting the last selection switch signal, and among the other fourth flip-flops, the Q terminal of the previous fourth flip-flop is connected to the D terminal of the next fourth flip-flop for sequentially outputting the selection switch signals, the R terminal of each fourth flip-flop is used to input a reset signal, and the CK terminal of each fourth flip-flop is used to input the phase shift signal; The D terminal of the third trigger is connected to the output terminal of the second inverter, the Q terminal of the third trigger is connected to the input terminal of the third inverter, the R terminal of the third trigger is used to input the reset signal, and the CK terminal of the third trigger is used to input the phase shift signal.

5. The phase selector according to claim 1, wherein: The phase selection circuit includes m fourth inverters and m switches corresponding to each fourth inverter; For each set of fourth inverters and switches, an input end of the fourth inverter is connected to a first control end of the switch for inputting a phase selection switch signal, and an output end of the fourth inverter is connected to a second control end of the switch; The first end of the switch is used to input a data signal corresponding to the phase selection switch signal, and the second end of the switch is used to output the phase selection signal.

6. The phase selector according to claim 5, wherein: The switch includes a first switching tube and a second switching tube; The control end of the first switching tube serves as the first control end of the switch, the first end of the first switching tube is connected to the first end of the second switching tube, and the second end of the first switching tube is connected to the second end of the second switching tube; The control end of the second switching tube serves as the second control end of the switch.

7. A phase selection signal output method, characterized in that: The method includes: Under the control of the phase shift flag signal, the phase selection signal is counted to obtain a count signal, and the obtained count signal is compared with the shift number signal, and a phase shift signal for controlling the phase shift is output according to the comparison result, the phase shift flag signal and the phase selection signal; Under the control of the phase shift signal, changing the phase selection switch signal; According to the changed phase selection signal, select a data signal from n data signals with different phases as the phase selection signal, and output the selected data signal, wherein n is a positive integer greater than 2; The method further comprises: counting the phase selection signal under the control of the phase shift flag signal to obtain a count signal, comparing the obtained count signal with the shift number signal, and outputting a phase shift signal for controlling the phase shift based on the comparison result, the phase shift flag signal, and the phase selection signal. Under the control of the phase shift flag signal, counting the phase selection signal and outputting m counting signals; comparing the m counting signals and the m shift number signals, and outputting a shift number same signal indicating whether the m counting signals and the m shift number signals are the same; Under the control of the shift number same signal, the phase shift flag signal and the reset signal, performing a logic operation on the phase selection signal and outputting the phase shift signal; Wherein, m is a positive integer greater than 2; The step of performing a logic operation on the phase selection signal under the control of the shift number same signal, the phase shift flag signal, and the reset signal to output the phase shift signal comprises: The shift signal generating sub-circuit performs a logic operation on the phase selection signal under the control of the shift number identical signal, the phase shift flag signal and the reset signal, and outputs the phase shift signal; Wherein, the shift signal generating sub-circuit includes a voltage clamp high logic tiehi gate, a first trigger, a second trigger and a second AND gate; The output end of the tiehi gate is connected to the D end of the first trigger, and is used to output a first level; The R terminal of the first flip-flop is used to input the shift number same signal, the CK terminal of the first flip-flop is used to input the phase shift flag signal, and the Q terminal of the first flip-flop is connected to the D terminal of the second flip-flop; The R terminal of the second flip-flop is used to input a reset signal, the ck terminal of the second flip-flop is used to input the phase selection signal, and the Q terminal of the second flip-flop is connected to the first input terminal of the second AND gate; The second input terminal of the second AND gate is used to input the phase selection signal, and the output terminal of the second AND gate is used to output the phase shift signal.

Images