Improved security and accuracy of data reading in non-volatile memory devices

Abstract

The present invention relates to systems and methods for improving the security and accuracy of data reads in a flash memory device associated with a system-on-chip. A method for improving the security and accuracy of data reads in a memory device associated with a host device or system-on-chip and comprising a memory array of memory cells is disclosed. The method comprises: storing data in a data memory cell; storing a memory address in a first memory cell in a spare area; storing an ECC in a second memory cell in the spare area; and comparing the contents of the first memory cell with the address of requested data. A memory device or assembly is also disclosed.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly to embodiments related to security and improved performance of data reads in non-volatile memory devices. Background Art

[0002] Memory devices are well known in the electronics field for storing and allowing access to digital information. Often, different types of semiconductor memory devices can be incorporated into more complex systems containing non-volatile memory components as well as volatile memory components, for example, in so-called system-on-chip (SoC) devices in which the aforementioned memory components are embedded.

[0003] However, today's demand for real-time operational systems, especially for automotive applications, requires SoCs to have increasingly higher performance and efficiency, and known solutions no longer meet these requirements, especially in terms of safety. Non-volatile memory can provide persistent data by retaining stored data when not powered on, and can include NAND flash memory, NOR flash memory, 3D XPoint memory, MRAM, STTRAM, and CBRAM, among others. NAND flash memory reduces erase and write times and requires less chip area per cell, thus allowing for greater storage density per bit and lower cost than NOR flash memory. However, the I / O interface of NAND flash memory does not provide random access to an external address bus. Instead, data must be read on a block-by-block basis, with typical block sizes ranging from hundreds to thousands of bits.

[0004] Flash memory devices are subject to temperature fluctuations, particularly elevated temperatures, during operation. This is primarily due to the fact that when the floating gate forming the memory is biased in the presence of elevated temperatures, it can reach energy levels sufficient to allow a jump into the channel, resulting in charge loss. In other technologies, such as charge trapping, elevated temperatures accelerate recombination, which can lead to loss of stored information. These issues impact the security and accuracy of data read from the memory device.

[0005] Furthermore, the interaction between the human body and electrical / electronic systems is increasing significantly in automotive applications, especially when managing safety-critical decisions that can have serious consequences for the driver's health. As these advanced safety systems evolve from passive to more active, encompassing predictive safety and even autonomous vehicle concepts, the automotive industry has and will continue to demand that stringent requirements be met, even for passengers, pedestrians, and other road users.

[0006] Managing these safety-critical decisions tends to increase the complexity of safety systems and the addition of software content. With this increased complexity comes an increased risk of systematic and / or random hardware failures.

[0007] There is a need to provide a flash memory device associated with a SoC device that provides improved security and correctness of data reading, thereby reducing the risk of failure. Summary of the Invention

[0008] In one aspect, the present disclosure relates to a non-volatile memory device comprising at least one memory cell array having associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises: a plurality of sub-arrays in the at least one array; a plurality of memory blocks in each sub-array; a plurality of memory rows in each memory block; and a plurality of extended pages in each memory row, each extended page comprising a set of data bits, address bits, and ECC bits.

[0009] On the other hand, the present disclosure relates to an apparatus comprising: a host device or a system on a chip (SoC); a memory component associated with the host device or the SoC; at least one memory cell array in the memory component having an associated decoding and sensing circuit system; a memory controller in the memory component; wherein the memory array comprises: a plurality of sub-arrays in the at least one array; a plurality of memory blocks in each sub-array, each memory block comprising a plurality of rows; a plurality of extended pages in each memory row, each extended page comprising a set of data bits, address bits, and ECC bits.

[0010] In another aspect, the present disclosure relates to a method for improving the security and correctness of data reading in a memory device, wherein the memory device is associated with a host device or a system on chip and includes a memory array of memory cells, the method comprising: storing data in a data memory cell; storing a memory address in a first memory cell in a spare area; storing an ECC in a second memory cell in the spare area; and comparing the content of the first memory cell with the address of the requested data.

[0011] In another aspect, the present disclosure relates to a method for improving the security of data reading in an independent memory device, wherein the memory device includes a memory cell array and is coupled to a SoC via a communication channel, the method comprising: defining an extended memory page, wherein the extended memory page includes data bits, address bits, and ECC bits; reading the extended memory page in the SoC; and comparing the address bits of the extended page read during reading with the requested address bits in the SoC to verify the correctness of the position of the data bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A schematic diagram of a system including a memory component associated with a controller that exchanges data, address, and control signals with the memory device is shown;

[0013] Figure 2 is a schematic diagram of a memory component according to the present disclosure;

[0014] Figure 3 is a schematic layout diagram of an example of a memory component according to various embodiments of the present disclosure;

[0015] Figure 4 is a schematic diagram of a memory block formed by a plurality of rows of a memory array according to one embodiment of the present disclosure;

[0016] Figure 5 is a schematic diagram of a set of address registers for a memory page in a memory component of the present disclosure;

[0017] Figure 6 is a block diagram illustrating stages of a method for improving security of data reading in a non-volatile memory device of the present disclosure;

[0018] Figure 7 is another block diagram illustrating stages of a method for improving security of data reading in a non-volatile memory device of the present disclosure. DETAILED DESCRIPTION

[0019] Several embodiments of the present disclosure relate to memory devices, systems including memory devices or components, and methods of operating memory devices or components, thereby avoiding potential issues with aging, temperature, and process drift during memory operation.

[0020] In one embodiment of the present disclosure, a new memory architecture is provided for improving security and performance during a data read phase in a non-volatile memory device.

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be disclosed, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is therefore not to be taken in a limiting sense.

[0022] When addressing a memory array, there may be one or more address translation layers that translate between logical addresses used by, for example, a host device, and physical addresses corresponding to locations in the memory array. The data state of each cell is determined by changes in the threshold voltage of the cell through programming of charge storage structures such as floating gates or trapping layers, or other physical phenomena.

[0023] Additionally, temperature variations within the same device can produce drifting readings known as the phantom temperature problem.

[0024] The drawbacks associated with such temperature variations have the effect of shifting the actual bit distribution detected by the sense amplifier relative to the ideal center value to which it has been programmed.

[0025] To give just one practical example, if the programming phase is performed at -40°C, it may be possible to read the result at 120°C and it may contain many errors. This is a real problem for all chips incorporated into automotive devices, where the increase in temperature during vehicle operation must be taken into account; moreover, the increase in temperature shifts or expands the distribution of good erased / programmed cells to the left and / or right (e.g., the threshold voltage is lowered and / or raised).

[0026] Therefore, the read phase of the memory device is mostly performed under environmental conditions similar to the original programming phase; the same is true for the erase phase.

[0027] Furthermore, temperature-induced drift is further increased due to device aging and frequent usage (e.g., in terms of write / erase cycles), and this problem can be particularly subtle for memory devices incorporated into system-on-chip autonomous vehicles.

[0028] Figure 1 An illustrative example of a system 10 incorporating a flash memory device 100 is shown. The system also includes a memory controller 101 coupled to the memory device 100.

[0029] Controller 101 is shown coupled to memory device 100 via a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus may be a wide double data rate (DDR) bus that is 64 bits and / or 128 bits wide.

[0030] More specifically, refer to Figure 2 , a non-volatile memory component or device 100 includes an array of flash memory cells 90 and circuitry positioned around the memory array, as described in more detail below. Coupling between the SoC structure 10 and the memory component 100 is achieved by interconnecting a plurality of corresponding pads or pins that face each other in a circuit layout that maintains the alignment of the pads even if the size of the memory component is modified.

[0031] In one embodiment of the present disclosure, the arrangement of the pads of the memory component has been implemented on the surface, in fact, on top of the array, of the memory component 100. More specifically, the pads are arranged on top of the array so that when the memory component 100 is inverted or flipped over, its pads face corresponding pads of the host or SoC structure 10.

[0032] The memory component 100 is manufactured according to the needs of the user within a range of values that can vary depending on the available technology, for example from at least 128 Mbits to 512 Mbits or even more, without any limitation to the rights of the applicant. More specifically, the proposed external architecture allows going beyond the limitations of current eFlash (i.e., embedded Flash technology) by allowing the integration of larger memories, such as 512 Mbits and / or 1 Gbit and / or more, depending on the memory technology and technology node.

[0033] The final configuration will be a face-to-face interconnected SoC / Flash array, where the sense amplifiers are connected to the SoC in a direct memory access configuration for user mode with high frequency access.

[0034] Direct memory access allows reducing the ultimate latency that an SoC may experience when reading data. Ultimate latency is also reduced by the block form factor, the distribution of sense amplifiers between blocks, the comparison thresholds in the sense amplifiers, and the selection of optimized paths.

[0035] To better understand the principles of the present disclosure, it should be noted that direct memory access is a feature of computing systems that allows certain hardware subsystems to access main system memory (usually volatile such as random access memory) independently of the CPU (central processing unit).

[0036] More specifically, DMA is used when the CPU is using the memory, and the DMA is usually occupied at a certain clock cycle of a read or write operation. Therefore, every time the I / O device accesses the memory, it takes a lot of time to input and / or output data to the memory.

[0037] The I / O device first initiates a transfer using the DMA controller, relinquishing control of the bus to the CPU, and the CPU then performs other operations while the transfer is in progress. Finally, the CPU receives an interrupt from the DMA controller when the operation is complete, so that the address bus or data bus can now be used by the I / O device for its internal operations. This feature is very useful any time the CPU cannot keep up with the rate at which data is being transferred, or when the CPU needs to perform work while waiting for a relatively slow I / O (input or output) data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards, and sound cards.

[0038] According to the present disclosure, DMA is used for intra-system data transfer in a multi-core processor. Compared to cores without DMA channels, cores with DMA channels can transfer data to and from memory components with less CPU overhead. Similarly, processing elements within a multi-core processor can transfer data to and from their local memory without consuming their processor time, thereby allowing computation and data transfer to proceed in parallel.

[0039] The present invention discloses a system and method for addressing direct memory access (DMA) operations and locating memory addresses to specific DMA flash memory arrays using boundary scan cells and sense amplifiers. In this regard, a modified JTAG cell structure is implemented to allow for an enlarged memory page to be read in direct access.

[0040] More specifically refer to Figure 2 , a main structure of the memory component 100 according to an embodiment of the present disclosure will be disclosed.

[0041] The memory component 100 includes at least the following: I / O circuits 5, a microsequencer 3, a memory cell array 90, a voltage and current reference generator 7, a charge pump 2 and a decoding circuit system 8 located at the periphery of the array or below the array, a read amplifier 9 and corresponding latches, and a command user interface, such as a CUI block 4.

[0042] Memory cell array 90 includes nonvolatile flash memory cells. These cells can be erased block by block, rather than one byte at a time. Each erasable block of memory includes multiple nonvolatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating the voltage and timing on the access and data lines.

[0043] To write and erase the memory cells of array 90, a dedicated logic circuit portion is provided, which includes a simplified Reduced Instruction Set Computer (RISC) controller or a modified finite state machine, or logic circuits for processing programming and erasing algorithms.

[0044] To read the memory cells of array 90, dedicated circuitry is provided, including an optimized read finite state machine or RISC to ensure high read performance, such as branch prediction, fetch / prefetch, and interrupt management. Error correction is left to the SoC 10; additional bits are provided to controller 101 to store any possible ECC syndromes associated with the page. ECC cells allow the host controller to understand whether data and address content have been corrupted. ECC also allows the host to correct received data. The host is responsible for repairing the data in memory based on the corrections performed in the received data.

[0045] The write and erase phases reported above are handled by a memory controller located inside the memory device, as the internal flash controller is not active in read operations driven by the host.

[0046] Now more specifically refer to Figure 3 For example, in one embodiment of the present disclosure, the memory array 90 is structured as a collection of sub-arrays 120. In this way, access time is significantly reduced and the overall throughput of the memory component is improved, given smaller sectors compared to known solutions.

[0047] This architecture is very scalable, and expanding and / or reducing the density of the final device is simply a matter of mirroring the subarrays and generating connections.

[0048] The host device or system on chip 10 typically includes more than one core, and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 1. Each sub-array 120 can access a corresponding channel to communicate with a corresponding core of the system on chip.

[0049] The host device's core can access the JTAG interface using internal pads. These pads are fast and can support the maximum frequency. However, these pads cannot manage analog voltages external to the flash array.

[0050] In an embodiment of the present disclosure, direct memory access (DMA) allows for reducing the resulting latency that a SoC may experience when reading data.

[0051] In order to overcome the problems of flash memory devices embedded in a system on chip and obtain very low initial latency and high throughput, a scalable, low-cost, efficient and reliable memory device and method have been designed, which involves completing data, address and ECC read operations through a DMA flash array, thereby ensuring that data must be read from exactly the same memory location as required by the controller.

[0052] Looking more closely at the internal structure of memory assembly 100, it should be noted that the architecture of array 90 is structured as a collection of sub-arrays 120, such as Figure 3 Shown schematically.

[0053] Each sub-array 120 is independently addressable within the memory device 100. Each sub-array 120 contains a plurality of memory blocks 160, such as Figure 3 and 4 Depicted.

[0054] In this way, with smaller sectors compared to known solutions, access times are significantly reduced and the overall throughput of the memory component is improved. Initial latency is reduced at the block level because the latency associated with the row and column lines, the read path, and external communications are optimized.

[0055] In the embodiments disclosed herein, the memory array 90 is configured to have a plurality of sub-arrays 120 that correspond at least to the number of cores, and therefore the number of corresponding communication channels, of the associated SoC 10. For example, at least four memory sub-arrays 120 are provided, one for each communication channel associated with a core of the SoC 10.

[0056] The host device or system on chip 10 typically includes more than one core, and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 100 .

[0057] Thus, in this embodiment, each sub-array 120 can access a corresponding channel to communicate with a corresponding core of the system on chip 10. The results of the memory blocks are driven directly to the SoC without the use of high power output buffers and optimization paths.

[0058] This architecture is very scalable, where expanding and / or reducing the density of the final device is simply a matter of mirroring the subarrays and generating connections or increasing the number of blocks per subarray, ie, the available density per core.

[0059] It should be further noted that each sub-array 120 includes an address register connected to a data buffer register, similar to the architecture used in DRAM memory devices.

[0060] Furthermore, in one embodiment of the present disclosure, each memory sub-array 120 is constructed in Figure 4 The memory block 160 is shown schematically.

[0061] Each independently addressable location of a block of each memory sub-array 90 addresses an extended page 150. Later on, the term "superpage" will be used to define several extended pages.

[0062] In other words, the 128-bit atomic page used in each sub-array 120 to populate the communication channels and SoC devices has been enlarged in this embodiment to contain the stored address and ECC.

[0063] As a non-limiting example, such an extended page 150 includes a string comprising: a first group of at least N bits, e.g., one hundred and twenty-eight (128) bits for I / O data exchange with the SoC device 10, plus at least a second group of M bits, e.g., twenty-four (24) address bits, and a final or third group of at least R bits, e.g., sixteen (16) ECC bits. The M address bits (twenty-four address bits in this example) are sufficient to address up to 2 gigabit of available memory space.

[0064] According to the present disclosure, the output of the sense amplifier SA prepares a double extended page at a time according to the size of the memory array, ie, a super page 150 including a plurality of bits given by a double combination of the above three sets of data bits, address bits, and ECC bits.

[0065] In the specific but non-limiting example disclosed herein, each extended page 150 contains at least 168 bits obtained by combining the above three groups of N+M+R=128+24+16 data bits, address bits and ECC bits, and each super page is formed by several extended pages, i.e., a group of 168×2 bits.

[0066] Just to give a non-limiting numerical example, each row of memory block 160 contains sixteen extended pages. Thus, the resulting row contains 2688 bits from the combination of sixteen independently addressable extended pages, or in other words, the combination of eight super pages, and each extended page contains 168 bits.

[0067] A first embodiment of the present disclosure is directed to a non-volatile memory device comprising at least one memory cell array with associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises:

[0068] - a plurality of sub-arrays in said at least one array;

[0069] - Multiple memory blocks in each sub-array;

[0070] - Multiple memory rows in each memory block;

[0071] - Multiple extended pages in each memory row, each extended page containing a set of data bits, address bits, and ECC bits to improve the security of data reading.

[0072] Another embodiment of the present disclosure is directed to a method for improving security and correctness of data reading in a memory device associated with a host device or a system on chip and including a memory array of memory cells, the method comprising:

[0073] - storing data in data memory cells;

[0074] - storing the memory address in a first memory cell of the spare area;

[0075] - storing the ECC in a second memory cell of the spare area;

[0076] - comparing the content of the first memory cell with the address of the requested data.

[0077] Figure 6 is a block diagram showing the stages of a method for improving the security of data reading in a non-volatile memory device of the present disclosure according to the above method. The method can be referred to as Figures 1 to 5 The memory devices or components described in further detail are implemented.

[0078] Further embodiments of the present disclosure relate to a method for improving security of data reading in a standalone memory device, the memory device including a memory cell array and coupled to a SoC via a communication channel, the method comprising:

[0079] - defining an extended memory page, wherein the extended memory page includes data bits, address bits and ECC bits;

[0080] - reading the extended memory page in the SoC;

[0081] - comparing the address bits of the extended page read during a read with the requested address bits in the SoC to verify the correctness of the location of the data bits.

[0082] Figure 7 is a block diagram showing the stages of a method for improving the security of data reading in a non-volatile memory device of the present disclosure according to the above method. The method can be referred to as Figures 1 to 5 The memory devices or components described in further detail are implemented.

[0083] According to one embodiment of the present disclosure, Figure 4 As shown, at least one virtual row 200 is associated with each block 160 of the memory sub-array 120 .

[0084] This dummy row 200 is located outside the address space of the memory array 90 and is used for optimization of read parameters, write parameters and erase parameters. In addition, this dummy row is used for erase robustness monitoring for good completion of modify operations and other purposes.

[0085] According to another embodiment, the dummy row of block 160 is provided in another block of memory sub-array 120 .

[0086] The presence of such a virtual row allows storing the reading parameters at an appropriate time and in a suitable manner to optimize further steps using monitoring operations.

[0087] Therefore, the main purpose of such a dummy row 200 is to keep track of parameters that may be used during the read and erase phases of the memory component 100 and / or to store some parameters for discovering a possible power loss.

[0088] Dummy row 200 contains a pattern known to controller 101 of memory device 100 .

[0089] Each memory block contains at least 256 rows, and each row contains sixteen extended pages of the aforementioned size. Each extended page contains at least 168 bits, which is a combination of data bits, address bits, and ECC bits. Therefore, each row of the memory array can contain up to sixteen double words, each of 32 bits, plus address bits and ECC bits for each page.

[0090] Just give a value, the extended page is formed by 128+16+24=168 bits, and each row of sixteen extended pages includes 168 * 16=2688 digits.

[0091] Thus, each row 135 of the memory block 160 contains at least sixteen pages, or in other words, a combination of eight extended pages, including the memory word plus corresponding address bits and corresponding ECC bits.

[0092] Obviously, another size can be chosen and the reported values are only for illustrative purposes of a non-limiting example. The result of the block is driven directly by the host device or SoC 10 without the need for high-power output buffers of known solutions and with an optimized path thanks to a modified and optimized JTAG interface.

[0093] The output of the sense amplifier SA is latched by internal circuitry of the read interface for each sub-array 120. The memory structure can be extended to allow multi-page reads while simultaneously shifting out already read pages.

[0094] As will be disclosed later, the sense amplifier SA is directly connected to the modified JTAG cell, so that the JTAG structure and the sense amplifier are integrated into a single circuit section. This allows the delay in propagating the output of the memory array to the SoC to be minimized.

[0095] As previously described, the sense amplifier 9 is internally preparing two pages of at least 128 bits plus address bits and ECC bits for a total of 168 bits, and while the first page is ready to be shifted, an additional read operation of the second page associated with the same address is internally performed.

[0096] This allows five to eight double words to be prepared, allowing the sense amplifier to perform an additional internal read operation to prepare the second half byte or second group of 168 bits if the system is constructed with two pages of 168 bits, which is typical in RTOS applications. This is why a double page of 2 × 128 bits plus the corresponding address bits and ECC bits was chosen.

[0097] This second portion of the four double words is transferred to the output of the flash array 90 using an additional enable signal (i.e., an internal clock signal or ADV signal) that transfers the content read at the sense amplifier stage to the host device or SoC device 10. The signal names are LOAD_DATA[0,1]... and there is no need to increment the address when using superpages.

[0098] The combined string of data cells+address cells+ECC cells allows the implementation of the entire security coverage of the communication channel according to the standard requirements of rule ISO 26262, since the host first corrects the data stream (if any) and then compares the sent address with the received address.

[0099] Furthermore, the ECC covers the entire bus communication (data cell + address cell), while the presence of the address cell provides confidence that the data came entirely from the location addressed by the controller, ie, if ADD == ADD0.

[0100] For testing of the memory component, a JTAG interface is used, allowing the reuse of test tools. The memory component of the present disclosure also includes JTAG logic including a JTAG interface.

[0101] In more detail, each memory array contains at least one JTAG interface that receives as input the standard JTAG signals: TMS, TCK, TDI and data from the memory page, e.g. Figure 5 According to an embodiment of the present disclosure, a flexible TDI signal is used. The flexibility is due to the fact that the number of parallel bits working as TDI depends on the selected register, i.e., instruction register, address register, or data register, etc.

[0102] This JTAG interface produces as output data, address, and control signals that are transferred to a memory address decoder and also to an internal Flash memory controller to perform modify, test, and verify operations.

[0103] The above features are particularly important for real-time operability systems used in automotive applications, where SoCs are required to have increasingly higher performance when exchanging data with memory arrays.

[0104] As these SoC devices become more complex, the risk of systematic and / or random hardware failures increases. To help ensure the highest safety standards and influence the development of safe automotive systems, the industry has released the latest automotive safety standard: ISO 26262.

[0105] In this respect, the solution proposed in this disclosure achieves the safety goals of the Automotive Safety Integrity Level (ASIL) requirements of the Original Equipment Manufacturers (OEMs). The level status achieved by the solution disclosed herein is at least level ASIL-D.

[0106] Due to the previously disclosed hardware solutions, the memory device of the present disclosure is implementing a method to allow the SoC to understand that the data content is read exactly from the address that the controller requested to read.

[0107] This approach is based on the following:

[0108] Storing data information in a flash memory cell, for example, in a flash memory cell in a data area;

[0109] storing the memory address in a flash memory cell, for example, in a first plurality of flash memory cells in a spare area;

[0110] further storing the ECC in the flash memory cells, for example, in a second plurality of flash memory cells in the spare area;

[0111] The contents of the first flash memory cell in the spare area are compared with the address requested by the host to access the data stored in the flash memory cell in the data area. In some embodiments, the host sends the requested address to the memory device or component for comparison. This method ensures the correctness of the read operation because:

[0112] The page is exactly the one being addressed;

[0113] The presence of ECC ensures that data and address content are corrected according to the error correction mechanism.

[0114] The implementation of the safety mechanisms described above helps achieve the target ASIL level, ie, D, for the memory device 100 .

[0115] Figure 5 FIG2 is a schematic diagram of a set of address registers for a memory page in the memory component of the present disclosure. More specifically, FIG2 is a schematic diagram indicating that address bits and ECC bits are also included in a channel or bus for communicating with a host or SoC device 10.

[0116] In other words, the read data buffer of the memory component 100 is accomplished in the following manner:

[0117] data;

[0118] address (stored to perform the comparison);

[0119] ECC (makes sure the data+address sent to the bus can be corrected in case of errors).

[0120] This solution allows improving the security of all communication exchanges from the memory component 100 to the associated SoC device 10 .

[0121] The disclosed architecture and method have at least several significant advantages. First, the system improves the security and accuracy of data reads between a host device and an associated memory device.

[0122] Secondly, the system automatically prevents any possible thermal drifts of the environment in which the memory device or the system in which the memory device is embedded.

[0123] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that arrangements intended to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of the various embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and not restrictive manner. Reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims together with the full scope of equivalents to which such claims are given.

Claims

1. A memory device comprising: a plurality of sub-arrays (120), wherein each sub-array is coupled to a respective bus or channel for communicating with a core or system-on-chip (SoC) of a host device via direct memory access; a plurality of memory blocks (160) in each sub-array of the plurality of sub-arrays; a plurality of memory rows (135) in each memory block of the plurality of memory blocks; as well as A plurality of extended pages (150) in each of the plurality of memory rows, wherein each of the plurality of extended pages comprises a set of data, an address, and an error correction code (ECC) covering the data and the address. 2 . The memory device of claim 1 , wherein each extended page of the plurality of extended pages is independently addressable.

3. The memory device of claim 1 , wherein each sub-array of the plurality of sub-arrays comprises an address register connected to a data buffer register; and Wherein the direct memory access is driven without a high power output buffer and includes the data, the address and the ECC.

4. The memory device of claim 1 , wherein each of the plurality of extended pages containing the set of data, the address, and the ECC comprises at least 128 data bits, at least 24 address bits, and at least 16 ECC bits; and Each memory block of the plurality of memory blocks includes at least 256 memory cell rows, and each memory row of the plurality of memory rows includes at least 16 extended pages.

5. A memory device comprising: decoding (8) and sensing (9) circuits; Memory controller (101); A memory cell array (90), wherein the memory cell array comprises: a plurality of sub-arrays (120), wherein each sub-array is coupled to a respective bus or channel for communicating with a core or system-on-chip (SoC) of a host device via direct memory access; a plurality of memory blocks (160) in each sub-array of the plurality of sub-arrays; a plurality of rows (135) in each memory block of the plurality of memory blocks; A plurality of extended pages (150) in each of the plurality of rows, wherein each of the plurality of extended pages comprises a set of data, an address, and an error correction code (ECC) covering the data and the address.

6. The memory device of claim 5, wherein each extended page of the plurality of extended pages is independently addressable.

7. The memory device of claim 5, wherein each memory block of the plurality of memory blocks contains at least 256 rows of memory cells, and each row of the memory block contains at least 16 extended pages. 8 . The memory device of claim 5 , wherein each of the plurality of extended pages including the group data, the address, and the ECC includes at least 168 bits.

9. The memory device of claim 5, wherein each of the plurality of extended pages containing the set of data, the address, and the ECC contains at least 128 data bits, at least 24 address bits, and at least 16 ECC bits.

10. The memory device of claim 5, further comprising a dummy row configured to: store parameters for discovering a possible power loss; and Contains a pattern known to the memory controller. The memory device of claim 10 , wherein the virtual row is located outside of an address space of a corresponding block.

12. The memory device of claim 5, wherein each of the plurality of sub-arrays comprises an address register connected to a data buffer register; and Wherein the direct memory access is driven without a high power output buffer and includes the data, the address and the ECC.

13. A method of operating a memory device according to claim 1 or claim 5, the method comprising: storing data in a memory cell array (90); storing a memory address in a first plurality of memory cells in a spare area; storing error correction codes (ECC) in a second plurality of memory cells in the spare area; as well as The contents of the first plurality of memory cells are compared to an address of the requested data.

14. The method of claim 13, wherein comparing the contents of the first plurality of memory cells to the address of the requested data comprises reading the first plurality of memory cells in the spare area to obtain the contents.

15. The method of claim 13, wherein the extended page comprises a string of a first group of 128 data bits, a second group of 24 address bits, and a third group of 16 ECC bits. The method of claim 13 , wherein the extended pages are independently addressable.

17. The method of claim 13, wherein a system on chip (SoC) device is coupled to the memory cell array in a direct memory access configuration.

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