Semiconductor structure, method of manufacturing a semiconductor structure, and electronic device

Abstract

The application discloses a semiconductor structure, a manufacturing method of the semiconductor structure and an electronic device. The semiconductor structure comprises a semiconductor substrate, a protruding structure on the semiconductor substrate, and a side wall on both sides of the protruding structure. The protruding structure comprises an upper part and a lower part which are not in contact with each other. The upper part of the side wall is located on the side wall of the upper part of the protruding structure. The lower part of the side wall and the upper part of the protruding structure have an air gap between the lower part of the protruding structure. The air gap greatly reduces the capacitance of the protruding structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device. Background Technology

[0002] Among the key characteristics of DRAM (Dynamic Random Access Memory), data sensing margin is closely related to bit line capacitance (CBL). As DRAM devices become increasingly smaller, bit line capacitance must be reduced to maintain the sensing margin of previous generations. The most significant factors determining bit line capacitance are the thickness and dielectric constant of the bit line sidewalls. To ensure sufficient sensing margin in a DRAM device, either bit line capacitance must be reduced or cell capacitance must be increased. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor structure, a method for manufacturing the semiconductor structure, and an electronic device. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0004] According to one aspect of the embodiments of this application, a semiconductor structure is provided, comprising:

[0005] Semiconductor substrate;

[0006] A protrusion structure located on the semiconductor substrate; the protrusion structure includes an upper portion and a lower portion that do not contact each other; and

[0007] The first sidewall is located on both sides of the protruding structure. The upper part of the first sidewall is located on the sidewall of the upper part of the protruding structure. There is an air gap between the lower part of the first sidewall, the upper part of the protruding structure, and the lower part of the protruding structure.

[0008] According to another aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided, comprising:

[0009] A semiconductor substrate is provided, the semiconductor substrate including a protrusion structure, the protrusion structure including a lower portion, a first sacrificial layer and an upper portion stacked sequentially from bottom to top;

[0010] A second sacrificial layer is formed on both sides of the protruding structure. The second sacrificial layer includes a connected vertical portion and a horizontal portion. The vertical portion is located on the lower sidewall of the protruding structure and is in contact with the first sacrificial layer. The upper end of the vertical portion is flush with the top surface of the first sacrificial layer. The horizontal portion is located on the semiconductor substrate.

[0011] A first sidewall is formed above the second sacrificial layer;

[0012] The first sacrificial layer and the second sacrificial layer are etched to form an air gap between the first sidewall, the upper portion of the protrusion structure, and the lower portion of the protrusion structure.

[0013] According to another aspect of the embodiments of this application, an electronic device is provided, including the semiconductor structure described above.

[0014] One aspect of the technical solution provided in this application embodiment may include the following beneficial effects:

[0015] The semiconductor structure provided in this application includes a semiconductor substrate and a protrusion structure located on the semiconductor substrate. The protrusion structure includes an upper part and a lower part that do not contact each other, and a first sidewall located on both sides of the protrusion structure. The upper part of the first sidewall is located on the sidewall of the upper part of the protrusion structure, and the lower part of the first sidewall, the upper part of the protrusion structure, and the lower part of the protrusion structure have an air gap. The air gap greatly reduces the capacitance of the protrusion structure.

[0016] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a semiconductor substrate and a plurality of protrusion structures on the semiconductor substrate according to an embodiment of this application is shown;

[0019] Figure 2 It shows in Figure 1A schematic diagram of the structure after the second oxide layer has been deposited on the structure shown;

[0020] Figure 3 It shows in Figure 2 A schematic diagram of the structure after a hard mask material layer has been coated on it;

[0021] Figure 4 It shows in Figure 3 The diagram shows the structure after a portion of the hard mask material layer has been removed.

[0022] Figure 5 It shows in Figure 4 A schematic diagram of the structure after removing a portion of the second oxide layer is shown.

[0023] Figure 6 It shows in Figure 5 The diagram shows the structure after removing the remaining portion of the hard mask material layer.

[0024] Figure 7 It shows in Figure 6 A schematic diagram of the structure after etching away and thinning the remaining portion of the second oxide layer;

[0025] Figure 8 It shows in Figure 7 The diagram shown is a schematic of the structure after the first nitride layer has been deposited on it.

[0026] Figure 9 It shows in Figure 8 A schematic diagram of the structure after etching the horizontal portion of the first nitride layer on the structure shown;

[0027] Figure 10 It shows in Figure 9 A schematic diagram of the structure after the third oxide layer has been deposited on the structure shown;

[0028] Figure 11 It shows that in relation to Figure 10 A schematic diagram of the structure after etching the corresponding protruding structure;

[0029] Figure 12 It shows in Figure 11 A schematic diagram of the structure formed after depositing a third silicon nitride layer on the structure shown;

[0030] Figure 13 It shows the relationship with Figure 12 A top view of the corresponding semiconductor structure;

[0031] Figure 14 A schematic diagram of the structure after an air gap is formed on the first part of the protruding structure is shown;

[0032] Figure 15 For along Figure 13 The cross-sectional view of the line containing the double-headed arrow a, which is perpendicular to both the fence and the protruding structure, shows a schematic diagram of the structure after an air gap is formed on the second part of the protruding structure.

[0033] Figure 16 It shows in Figure 15 A schematic diagram of the structure after the deposition of the second nitride layer on the structure shown;

[0034] Figure 17 For along Figure 13 The cross-sectional view, taken with the line containing the double-headed arrow b perpendicular to both the fence and the protruding structure, shows that... Figure 16 The diagram shows the structure after the unit contact element is formed on the structure shown. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0038] like Figure 14 As shown, one embodiment of this application provides a semiconductor structure, including:

[0039] Semiconductor substrate 1;

[0040] A protrusion structure 2 is located on a semiconductor substrate 1; the protrusion structure 2 includes an upper portion 2-1 and a lower portion 2-2 that do not contact each other;

[0041] The first sidewall 6' is located on both sides of the protruding structure 2. The upper part of the first sidewall 6' is located on the sidewall of the upper part 2-1 of the protruding structure 2. The lower part of the first sidewall 6' protrudes outward. There is an air gap 8 between the lower part of the first sidewall 6', the upper part 2-1 of the protruding structure 2 and the lower part 2-2 of the protruding structure 2.

[0042] like Figure 13 As shown, the semiconductor structure also includes several parallel gates 12, which intersect each other perpendicularly with the protrusion structure (in this embodiment, the protrusion structure is bit line 13); the protrusion structure includes a first part and a second part, the first part is located between two adjacent gates 12, and the second part is located below the gates 12 and in contact with the gates 12.

[0043] A gap 9 exists between the bottom surface of the first sidewall 6' and the semiconductor substrate 1, and the gap 9 is connected to the air gap 8. The gap 9 serves as the opening structure of the air gap 8.

[0044] like Figure 16 As shown, another embodiment of this application provides a semiconductor structure, including:

[0045] Semiconductor substrate 1;

[0046] A protrusion structure 2 is located on a semiconductor substrate 1; the protrusion structure 2 includes an upper portion 2-1 and a lower portion 2-2 that do not contact each other;

[0047] The first sidewalls 6' located on both sides of the protruding structure 2;

[0048] The second nitride layer 10 is located outside the first sidewall 6';

[0049] The upper portion of the first sidewall 6' is located on the upper sidewall of the protruding structure 2; the lower portion of the first sidewall 6' protrudes outward; an air gap 8 exists between the upper portion 2-1 and the lower portion 2-2 of the protruding structure 2 and the lower portion of the first sidewall 6'; a gap 9 exists between the bottom of the first sidewall 6' and the semiconductor substrate 1; this gap 9 is the opening of the air gap 8; a second nitride layer 10 covers the outer surface of the first sidewall 6', the top surface of the upper portion of the protruding structure 2, and the exposed portion of the top surface of the semiconductor substrate 1, and the bottom of the second nitride layer 10 extends into the gap 9, filling the gap 9 and thus sealing the opening of the air gap 8. A gap exists between the bottom surface of the upper portion and the top surface of the lower portion of the protruding structure 2, and the gap between the upper and lower portions of the protruding structure 2 is part of the air gap 8. The entire air gap 8 surrounds the lower portion of the protruding structure 2. The semiconductor structure also includes several parallel-arranged fences that intersect the protruding structures perpendicularly.

[0050] The protrusion structure 2 can be a gate or a bit line, for example, it can be a bit line of DRAM.

[0051] The semiconductor structure also includes a unit contact 11, which is disposed between two adjacent protrusions 2, and one end of the unit contact 11 is inserted into the semiconductor substrate 1.

[0052] The upper end of the first side wall 6' is flush with the upper end of the protruding structure 2. For example... Figure 15 As shown, another embodiment of this application provides a semiconductor structure, including:

[0053] Semiconductor substrate 1;

[0054] A protrusion structure 2 is located on a semiconductor substrate 1; the protrusion structure 2 includes an upper portion 2-1 and a lower portion 2-2 that do not contact each other;

[0055] The first sidewall 6' is located on both sides of the protruding structure 2. The upper part of the first sidewall 6' is located on the sidewall of the upper part 2-1 of the protruding structure 2. The lower part of the first sidewall 6' protrudes outward. There is an air gap 8 between the lower part of the first sidewall 6', the upper part 2-1 of the protruding structure 2 and the lower part 2-2 of the protruding structure 2.

[0056] Several parallel fences are arranged, with the fences and the protruding structure 2 intersecting each other perpendicularly.

[0057] The upper end of the first sidewall 6' is lower than the upper end of the protrusion structure 2. A gap 9 exists between the bottom surface of the first sidewall 6' and the semiconductor substrate 1, and this gap 9 is connected to an air gap 8. The semiconductor structure also includes a third nitride layer 14, which covers the semiconductor substrate 1, the protrusion structure 2, and the first sidewall 6', sealing the gap 9. The semiconductor structure of this embodiment is for… Figure 13 The fence shown is obtained through processing. The first sidewall 6' can be a nitride layer.

[0058] Another embodiment of this application provides a method for manufacturing a semiconductor structure, including:

[0059] like Figure 1 As shown, a semiconductor substrate 1 is provided, on which a protrusion structure 2 is included.

[0060] The semiconductor substrate 10 can be made of silicon. The protrusion structure 2 includes an upper portion 2-1, a lower portion 2-2, and a first oxide layer 2-3 located between the upper portion 2-1 and the lower portion 2-2. The upper portion 2-1 can be made of nitride; the lower portion 2-2 can be made of metal.

[0061] For example, protrusion structure 2 can be a bit line, and the upper part of the bit line electrode is not a SiN layer but an oxide layer. This oxide layer is used to construct part of the air gap sidewall.

[0062] like Figure 2As shown, a second oxide layer 4 is deposited. The second oxide layer 4 covers the sidewalls, top surface, and exposed portion of the top surface of the protrusion structure 2 and the semiconductor substrate 1. The second oxide layer 4 is in contact with both sides of the first oxide layer 2-3. The second oxide layer 4 and the first oxide layer 2-3 are used to construct the contour of the air gap. The first oxide layer 2-3 serves as the first sacrificial layer, and the second oxide layer 4 serves as the second sacrificial layer.

[0063] like Figure 3 As shown, a hard mask material layer 5 is coated. The hard mask material layer 5 covers the surface of the second oxide layer 4, and the top surface of the hard mask material layer 5 is higher than the top surface of the second oxide layer 4. The hard mask material is abbreviated as SOH, spin-on-hardmask.

[0064] like Figure 4 As shown, a portion of the hard mask material layer 5 is removed through an ashing process, so that the top surface of the remaining portion 5' of the hard mask material layer 5 is substantially flush with the top surface of the first oxide layer 2-3. The hard mask material layer is a type of dielectric layer.

[0065] like Figure 5 As shown, a portion of the second oxide layer 4 is etched away, so that the top surface of the remaining portion 4' of the second oxide layer 4 is substantially flush with the top surface of the first oxide layer 2-3. The oxide removal process can be either wet etching or dry etching.

[0066] like Figure 6 As shown, the remaining portion 5' of the hard mask material layer 5 is removed by an ashing process.

[0067] like Figure 7 As shown, the horizontal portion 4'-1 of the remaining portion 4' is etched and thinned. The vertical portion 4'-2 of the remaining portion 4' is used to form part of the outline of the air gap. The purpose of etching and thinning the horizontal portion 4'-1 of the remaining portion 4' is to make the air gap opening smaller, making the opening easier to seal. A dry etching process can be used to etch the oxide.

[0068] like Figure 8 As shown, the first structure obtained after the above steps (i.e. Figure 7 On the structure shown, a first nitride layer 6 is deposited. The first nitride layer 6 covers the structure obtained after the above steps.

[0069] like Figure 9As shown, the horizontal portion of the first nitride layer 6 is etched, exposing the horizontal portion 4'-1 of the second oxide layer 4. The remaining portion (i.e., the vertical portion) of the first nitride layer 6 forms the first sidewall 6'. The horizontal portion of the first nitride layer 6 includes a horizontal portion 6-1 located on the top surface of the upper portion 2-1 of the protrusion structure 2 and a horizontal portion 6-2 located on the horizontal portion of the remaining portion 4' of the second oxide layer 4. The nitride may be silicon nitride.

[0070] like Figure 10 As shown, a third oxide layer 7 is deposited, the top surface of which is substantially flush with the top surface of the upper portion 2-1 of the protrusion structure 2. The third oxide layer 7 fills the spaces between the bit line patterns. The oxide can be silicon dioxide. The third oxide layer 7 is formed to facilitate the formation of the gate in subsequent process steps.

[0071] like Figure 11 As shown, a trench 15 is formed on the semiconductor substrate 1 between each pair of adjacent protrusion structures 2. After obtaining... Figure 10 After the structure shown, as Figure 11 As shown, the first nitride layer 6 of the second portion is etched, so that the upper end of the first sidewall 6' of the formed second portion is lower than the upper end of the second portion of the protrusion structure 2, exposing the upper end of the protrusion structure 2. Figure 11 A third silicon nitride layer 14 is deposited on the structure shown, forming a structure as follows: Figure 12 As shown. Figure 13 The image shows the result obtained. Figure 12 The diagram shows a top view of the semiconductor structure following the previously shown structure. The third silicon nitride layer 14 serves as the fence 12. Several parallel fences 12 are formed through the above steps, with the fences 12 perpendicularly intersecting the protrusion structure 2. Bit lines 13 (in this embodiment, the protrusion structure is exemplified by a bit line) perpendicularly intersect the fences 12. Figure 13 As shown, the area 15 enclosed by bit line 13 and fence 12 is used to form unit contacts. Figure 13 In this configuration, the fences 12 are arranged horizontally, and the bit lines 13 are arranged vertically. The portion of the bit line 13 located between two adjacent fences 12 is called the first portion, and the portion of the bit line 13 that contacts the fence 12 is called the second portion. Each second portion is located between two adjacent first portions. The first and second portions are alternately arranged along the entire bit line 13. The top surface of the third silicon nitride layer 14 is higher than the upper end of the second portion of the protrusion structure 2. The fences are located above the second portions. The second portions are located below the fences 12 and are in contact with the fences 12.

[0072] After wet etching removes the first oxide layer 2-3 and the vertical portion 4'-2, the structure of the first portion is as follows: Figure 14 As shown, the structure of the second part is as follows: Figure 15As shown, an air gap 8 is formed, simultaneously opening the unit contact position. Since the third nitride layer 14 of the gate 12 is fixed to the bit line pattern, the structure outside the air gap is stable. (See diagram) Figure 14 As shown, the remaining portion 4' of the third oxide layer 7, the second oxide layer 4, and the first oxide layer 2-3 are etched away to form an air gap 8. A gap 9 exists between the first sidewall 6' and the semiconductor substrate 1. The gap 9 communicates with the air gap 8, serving as the opening of the air gap 8. The entire air gap 8 completely covers the lower portion 2-2 of the protrusion structure 2. The gap 9 serves as the opening structure of the air gap 8. The air gap 8 separates the upper portion 2-1 from the lower portion 2-2, surrounding the lower portion 2-2 from three directions: above, left, and right. The upper portion 2-1 is secured by the barrier 12 to ensure it does not collapse. During the fabrication of the air gap 8, before forming the barrier 12, the remaining portion 4' of the third oxide layer 7, the first oxide layer 2-3, and the second oxide layer 4 cannot be directly etched away to form the air gap, to avoid the upper portion 2-1 collapsing. A third oxide layer 7 is formed to facilitate the formation of the fence 12. After the fence 12 is formed, the oxide layer is etched to form an air gap 8. The fence 12 "grabs" the upper part 2-1, preventing the upper part 2-1 from being "suspended" above the lower part 2-2 and collapsing due to lack of support.

[0073] like Figure 16 As shown, the second structure obtained after the above operation steps (i.e. Figure 14 A second nitride layer 10 is deposited on the structure shown. The second nitride layer 10 completely covers the second structure. The bottom of the second nitride layer 10 extends into the void 9, sealing the void 9. The second nitride layer 10 serves as a second sidewall.

[0074] like Figure 17 As shown, trenches are formed on the semiconductor substrate 1 between two adjacent protrusion structures 2, and cell contacts 11 are deposited within the trenches. The top surface of the cell contact 11 is higher than the semiconductor substrate and lower than the top surface of the second nitride layer 10. The cell contact 11 is used to form capacitor contacts, and the cell contact can also be referred to as a memory node contact.

[0075] In this embodiment, Figure 13 Taking bit line 13 as an example, the protruding structure in the middle, bit line 13 and Figure 13 The second part of the fence 12 shown in the diagram, after being etched, results in the following structure: Figure 11 As shown, the upper end of the first side wall 6' is lower than the upper end of the upper part 2-1 of the protruding structure 2.

[0076] In this invention, the air gap opening is at the bottom, making it relatively easy to seal the opening.

[0077] In this embodiment, the etching of the oxide layer can be accomplished using either dry etching or wet etching processes.

[0078] Another embodiment of this application provides an electronic device including the semiconductor structure described above. This electronic device includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

[0079] The air gap surrounding the bit line electrode (the lower part of the protruding structure) minimizes the bit line capacitance. This disclosure provides an air gap sidewall structure that reduces the CBL limit and solves the structure dispersion problem. Another aspect that differs from the prior art is that the air gap sidewall is formed first, followed by the patterning process of the unit contacts and landing pads.

[0080] The air gap sidewalls surround the bit line electrodes, minimizing bit line capacitance. Controlling the thickness and height of the air gap during sidewall formation is relatively easy. As described in the process above, the oxide height can be determined by adjusting the SOH layer back etching process. However, to achieve the air gap structure surrounding the bit line electrodes, the oxide on the sides must be higher than the oxide on top of the electrodes. After removing the oxide to form the air gap, sealing the air gap opening is relatively easy. The air gap opening is located at the bottom of the air gap, facing outwards, and is thinner than the oxide deposition thickness, making sealing relatively simple. During the formation of the air gap sidewalls, no conductor is exposed, significantly improving electrical short-circuit performance. The air gap reduces bit line capacitance, thereby increasing the induction margin.

[0081] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0082] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a protrusion structure, the protrusion structure including a lower portion, a first sacrificial layer and an upper portion stacked sequentially from bottom to top; A second sacrificial layer is formed on both sides of the protruding structure. The second sacrificial layer includes a connected vertical portion and a horizontal portion. The vertical portion is located on the lower sidewall of the protruding structure and is in contact with the first sacrificial layer. The upper end of the vertical portion is flush with the top surface of the first sacrificial layer. The horizontal portion is located on the semiconductor substrate. A first sidewall is formed above the second sacrificial layer; The first sacrificial layer and the second sacrificial layer are etched to form an air gap between the first sidewall, the upper portion of the protrusion structure, and the lower portion of the protrusion structure; The formation of the first sidewall above the second sacrificial layer includes: A first nitride layer is deposited on the protruding structure and the second sacrificial layer; The first nitride layer is etched to form a first sidewall located on the upper sidewall of the protrusion structure and on the sidewall of the second sacrificial layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The formation of a second sacrificial layer on both sides of the protruding structure includes: A second oxide layer is deposited; the second oxide layer covers the semiconductor substrate and the protrusion structure. A dielectric layer is deposited over the entire semiconductor structure, wherein the top surface of the dielectric layer is higher than the top surface of the second oxide layer; The dielectric layer and the second oxide layer are successively etched back to be substantially flush with the top surface of the first sacrificial layer, and the second oxide layer is formed as the second sacrificial layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the first sidewall above the second sacrificial layer, the method further includes: The horizontal portion of the second sacrificial layer is thinned by etching.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before etching the first sacrificial layer and the second sacrificial layer, the method further includes forming a plurality of parallel fences, the extension direction of the fences being perpendicular to the extension direction of the protrusion structure.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The protruding structure includes a first part and a second part, the first part being located between two adjacent fences, and the second part being located below the fence and in contact with the fence.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The fences arranged in parallel include: The first nitride layer of the second portion of the protrusion structure is etched so that the upper end of the first sidewall of the second portion is lower than the upper end of the second portion; A third nitride layer is deposited on the second portion, the third nitride layer forming the fence; the third nitride layer covers the first sidewall of the second portion, the upper portion of the second portion, and the semiconductor substrate.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The etching of the first nitride layer to form a first sidewall located on the upper portion of the sidewall of the protrusion structure and on the second sacrificial layer includes: The first nitride layer of the first portion of the protrusion structure is etched so that the upper end of the first sidewall of the first portion is flush with the upper end of the protrusion structure; at the same time, the first nitride layer of the second portion of the protrusion structure is etched so that the upper end of the first sidewall is lower than the upper end of the protrusion structure.

8. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The method further includes: A second sidewall is deposited on the semiconductor substrate and the first sidewall of the first portion to seal the bottom opening structure of the air gap.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The method further includes: A trench is formed on the semiconductor substrate between the second portions of two adjacent protrusion structures; A unit contact is deposited within the trench, the top surface of which is higher than the semiconductor substrate and lower than the top surface of the second sidewall.

10. A semiconductor structure, characterized in that, It is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1-9; the semiconductor structure comprises: Semiconductor substrate; A protrusion structure located on the semiconductor substrate, the protrusion structure comprising an upper portion and a lower portion that do not contact each other; and The first sidewall is located on both sides of the protruding structure. The upper part of the first sidewall is located on the sidewall of the upper part of the protruding structure. There is an air gap between the lower part of the first sidewall, the upper part of the protruding structure, and the lower part of the protruding structure.

11. The semiconductor structure according to claim 10, characterized in that, The bottom surface of the first sidewall has an opening structure for the air gap between it and the semiconductor substrate.

12. The semiconductor structure according to claim 11, characterized in that, It also includes a second sidewall that covers the outer side of the first sidewall and the top surface of the protruding structure, and the bottom of the second sidewall extends into the air gap and seals the opening structure.

13. The semiconductor structure according to claim 12, characterized in that, It also includes a unit contact, which is disposed between two adjacent protrusions, with one end of the unit contact inserted into the semiconductor substrate.

14. The semiconductor structure according to claim 10, characterized in that, The protruding structure extends on the substrate along a first direction.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure also includes a plurality of fences, the extension directions of which are perpendicular to the first direction.

16. The semiconductor structure according to claim 15, characterized in that, The protruding structure includes a first part and a second part, the first part being located between two adjacent fences, and the second part being located below the fence and in contact with the fence.

17. The semiconductor structure according to claim 16, characterized in that, In the first part, the upper end of the first sidewall is flush with the upper end of the protruding structure.

18. The semiconductor structure according to claim 17, characterized in that, It also includes a third nitride layer, which covers the semiconductor substrate, the first sidewall, and the protrusion structure.

19. The semiconductor structure according to claim 16, characterized in that, In the second part, the upper end of the first sidewall is lower than the upper end of the protruding structure.

20. The semiconductor structure according to claim 10, characterized in that, The protruding structure is a gate or a bit line.

21. An electronic device comprising a semiconductor structure as claimed in any one of claims 10 to 20.

22. The electronic device according to claim 21, including a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

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