Semiconductor memory device and method of manufacturing the same

Abstract

The present application discloses a semiconductor memory device and a method of manufacturing the semiconductor memory device. A semiconductor memory device and a method of manufacturing the same may be provided herein. The semiconductor memory device may include: a stack including an interlayer insulating layer and a conductive pattern alternately stacked; and a channel structure penetrating the stack. Each channel structure may include: a channel layer vertically extending up to a height of an upper portion of at least one uppermost upper conductive pattern among the conductive patterns; a memory layer surrounding the channel layer and extending from a lower interlayer insulating layer up to a height of an intermediate portion of the upper conductive pattern; and a doped semiconductor pattern disposed above the channel layer and the memory layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to semiconductor memory devices and methods of manufacturing semiconductor memory devices, and more particularly, to 3D semiconductor memory devices and methods of manufacturing 3D semiconductor memory devices. Background Art

[0002] A semiconductor memory device is a device for storing data under the control of a host device such as a computer, a smart phone, etc. The semiconductor memory device may be classified as a volatile memory device or a non-volatile memory device.

[0003] A volatile memory device is a memory device configured to store data only while power is supplied thereto and to erase the data stored therein when power is supplied. The volatile memory device includes a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0004] A non-volatile memory device is a memory device configured not to erase data even when power is supplied, and includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc.

[0005] A semiconductor memory device includes memory cells capable of storing data. A 3D semiconductor memory device includes memory cells arranged in a 3D manner, thereby reducing the area occupied by the memory cells per unit area of the substrate.

[0006] In order to increase the integration degree in a 3D semiconductor memory device, the number of stacked memory cells may be increased. As the number of stacked memory cells increases, the operation reliability of the 3D semiconductor memory device may decrease. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a stack including an interlayer insulating layer and a conductive pattern stacked alternately; and a channel structure penetrating the stack. Each channel structure may include: a channel layer vertically extending up to a height of an upper portion of an uppermost upper conductive pattern among the conductive patterns; a memory layer surrounding the channel layer and extending from a lower interlayer insulating layer up to a height of a middle portion of the upper conductive pattern; and a doped semiconductor pattern disposed above the channel layer and the memory layer.

[0008] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a stack including an interlayer insulating layer and a conductive pattern alternately stacked; and a channel structure penetrating the stack. Each channel structure may include: a channel layer vertically extending up to a height of a part of at least one uppermost conductive pattern among the conductive patterns; a memory layer surrounding the channel layer and extending up to a height lower than an upper surface of the channel layer; and a doped semiconductor pattern disposed above the channel layer and the memory layer, the channel layer including a protrusion protruding with respect to the upper surface of the memory layer and extending into the doped semiconductor pattern.

[0009] Embodiments of the present disclosure may provide a method of manufacturing a semiconductor memory device. The method may include: forming a preliminary stack including an interlayer insulating layer and a sacrificial layer alternately stacked; forming a channel hole penetrating the preliminary stack; forming a memory layer extending along a sidewall of the channel hole; forming a channel layer extending along a surface of the memory layer; forming a core insulating layer along a surface of the channel layer, and thereby the core insulating layer filling the channel hole; etching the core insulating layer, the channel layer, and the memory layer disposed in an upper portion of the channel hole such that the channel layer has a protrusion protruding with respect to the core insulating layer and the memory layer; and forming a doped semiconductor pattern in the upper portion of the channel hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or there can be one or more intervening elements. Throughout the specification, like reference numerals refer to like elements.

[0011] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B are perspective views schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 4 is a perspective view illustrating a gate stack of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 5 is Figure 4 an enlarged cross-sectional view of the region A shown.

[0016] Figure 6It is a cross-sectional view illustrating a source layer and a channel structure according to an embodiment of the present disclosure.

[0017] Figure 7 It is a cross-sectional view illustrating a source layer and a channel structure according to an embodiment of the present disclosure.

[0018] Figure 8A 、 Figure 8B and Figure 8C , Figure 9A 、 Figure 9B and Figure 9C as well as Figure 10A 、 Figure 10B and Figure 10C It is a cross-sectional view illustrating a method of manufacturing a memory cell array according to an embodiment of the present disclosure.

[0019] Figure 11 It is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0020] Figure 12 It is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. Detailed Description

[0021] The specific structural descriptions or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are only used to describe the embodiments of the present disclosure. Embodiments consistent with the concept of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described in the specification or application.

[0022] Hereinafter, although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0023] Various embodiments of the present disclosure relate to a semiconductor memory device capable of improving operation reliability and a method of manufacturing the semiconductor memory device.

[0024] Figure 1 It is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0025] Referring to Figure 1 , the semiconductor memory device 10 may include a peripheral circuit PC and a memory cell array 20.

[0026] The peripheral circuit PC can control a programming operation for storing data in the memory cell array 20, a read operation for outputting the data stored in the memory cell array 20, and an erase operation for erasing the data stored in the memory cell array 20.

[0027] In an embodiment, the peripheral circuit PC can include a voltage generator 31, a row decoder 33, a control circuit 35, and a page buffer group 37.

[0028] The memory cell array 20 can include a plurality of memory blocks. The memory cell array 20 can be connected to the row decoder 33 through word lines WL, and can be connected to the page buffer group 37 through bit lines BL.

[0029] The control circuit 35 can control the peripheral circuit PC in response to a command CMD and an address ADD.

[0030] The voltage generator 31 can generate various operation voltages such as a pre-erase voltage, an erase voltage, a ground voltage, a programming voltage, a verification voltage, a pass voltage, and a read voltage for the programming operation, the read operation, and the erase operation under the control of the control circuit 35.

[0031] The row decoder 33 can select a memory block under the control of the control circuit 35. The row decoder 33 can apply an operation voltage to the word lines WL connected to the selected memory block.

[0032] The page buffer group 37 can be connected to the memory cell array 20 through the bit lines BL. During the programming operation, the page buffer group 37 can temporarily store data received from an input / output circuit (not shown) under the control of the control circuit 35. During the read operation or the verification operation, the page buffer group 37 can sense the voltage or current of the bit lines BL under the control of the control circuit 35. The page buffer group 37 can select the bit lines BL under the control of the control circuit 35.

[0033] Structurally, the memory cell array 20 can overlap with a part of the peripheral circuit PC.

[0034] Figure 2 is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0035] Refer to Figure 2 , the memory block can include a source layer SL and a plurality of cell strings CS1 and CS2 commonly connected to a plurality of word lines WL1 to WLn. The plurality of cell strings CS1 and CS2 can be connected to a plurality of bit lines BL.

[0036] Each of a plurality of cell strings CS1 and CS2 may include at least one source select transistor SST connected to a source layer SL, at least one drain select transistor DST connected to a bit line BL, and a plurality of memory cells MC1 to MCn connected in series between the source select transistor SST and the drain select transistor DST.

[0037] The gates of the plurality of memory cells MC1 to MCn may be connected to corresponding word lines among a plurality of word lines WL1 to WLn, and the plurality of word lines are stacked in a state where they are spaced apart from each other. The plurality of word lines WL1 to WLn may be disposed between a source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 may be spaced apart from each other at the same level.

[0038] The gate of the source select transistor SST may be connected to the source select line SSL. The gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0039] The source layer SL may be connected to the source of the source select transistor SST. The drain of the drain select transistor DST may be connected to a bit line corresponding to the drain of the drain select transistor DST.

[0040] The plurality of cell strings CS1 and CS2 may be classified into string groups respectively connected to two or more drain select lines DSL1 and DSL2. Cell strings connected to the same word line and the same bit line may be individually controlled by different drain select lines. In addition, cell strings connected to the same drain select line may be individually controlled by different bit lines.

[0041] According to an embodiment, the two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. The plurality of cell strings CS1 and CS2 may include a first cell string CS1 of a first string group connected to the first drain select line DSL1 and a second cell string CS2 of a second string group connected to the second drain select line DSL2.

[0042] Figure 3A and Figure 3B are perspective views schematically illustrating semiconductor memory devices 10A and 10B according to embodiments of the present disclosure.

[0043] Referring to Figure 3A and Figure 3B , each of the semiconductor memory devices 10A and 10B may include a peripheral circuit PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuit PC.

[0044] Each gate stack GST may include a source select line SSL, a plurality of word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 separated from each other by a first slit S1 in the same horizontal plane.

[0045] The source select line SSL and the plurality of word lines WL1 to WLn may extend in a first direction X and a second direction Y, and may be formed in a plate shape parallel to the upper surface of the substrate SUB. The first direction X may be the direction of the X-axis of the XYZ coordinate system, and the second direction Y may be the direction of the Y-axis of the XYZ coordinate system.

[0046] The plurality of word lines WL1 to WLn may be stacked in a third direction Z while being spaced apart from each other. The third direction Z may be the direction of the Z-axis of the XYZ coordinate system. The plurality of word lines WL1 to WLn may be disposed between the source select line SSL and the two or more drain select lines DSL1 and DSL2. In an embodiment, the third direction Z may be a vertical direction. In an embodiment, the first direction X may be a horizontal direction.

[0047] The gate stacks GST may be separated from each other by a second slit S2. With respect to the third direction Z, the first slit S1 may be formed shorter than the second slit S2, and may overlap with the plurality of word lines WL1 to WLn.

[0048] Each of the first slit S1 and the second slit S2 may extend in a linear shape, a Z-shape, or a wavy shape. The width of each of the first slit S1 and the second slit S2 may be changed differently according to a design rule.

[0049] Referring to Figure 3A , the source select line SSL according to an embodiment may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2.

[0050] The semiconductor memory device 10A may include: a source layer SL disposed between the peripheral circuit PC and the gate stack GST; and a plurality of bit lines BL spaced farther from the peripheral circuit PC than the source layer SL. The gate stack GST may be disposed between the source layer SL and the plurality of bit lines BL.

[0051] Referring to Figure 3B , the two or more drain select lines DSL1 and DSL2 according to an embodiment may be disposed closer to the peripheral circuit PC than the source select line SSL.

[0052] The semiconductor memory device 10B may include: a plurality of bit lines BL disposed between the peripheral circuit PC and the gate stack GST; and a source layer SL spaced farther from the peripheral circuit PC than the plurality of bit lines BL. The gate stack GST may be disposed between the plurality of bit lines BL and the source layer SL.

[0053] Referring again to Figure 3A and Figure 3B , the plurality of bit lines BL may be formed of various conductive materials. The source layer SL may include a doped semiconductor layer. According to an embodiment, the source layer SL may include an n-type doped silicon layer.

[0054] Although not shown in the drawings, the peripheral circuit PC may be electrically connected to the plurality of bit lines BL, the source layer SL, and the plurality of word lines WL1 to WLn through interconnects having various structures.

[0055] Figure 4 is a perspective view illustrating gate stacks GSTa, GSTb, and GSTc of a semiconductor memory device according to an embodiment of the present disclosure.

[0056] Referring to Figure 4 , each of the gate stacks GSTa, GSTb, and GSTc may include a first stack ST1 and a second stack ST2. The first stack ST1 and the second stack ST2 may be disposed between the source layer SLa and the plurality of bit lines BL.

[0057] The plurality of bit lines BL may overlap with the first stack ST1, and the second stack ST2 may be disposed between the first stack ST1 and the plurality of bit lines BL. The plurality of bit lines BL may overlap with the source layer SLa.

[0058] The first stack ST1 may include an interlayer insulating layer ILD1 and a first conductive pattern CP1 stacked alternately. The first conductive pattern CP1 may serve as a source select line SSL and the plurality of word lines WL1 to WLn.

[0059] The second stack ST2 may include a second conductive pattern CP2 and an interlayer insulating layer ILD2. The second conductive pattern CP2 may be disposed between the interlayer insulating layer ILD2 and the interlayer insulating layer ILD1 provided in the upper portion of the first stack ST1. The second conductive pattern CP2 and the interlayer insulating layer ILD2 are sequentially disposed on the first stack ST1, thereby overlapping with the first stack ST1. The second conductive pattern CP2 may serve as drain select lines DSL1 and DSL2. In an embodiment, as Figure 4 and Figure 5 shown, the second conductive pattern CP2 may be the uppermost conductive pattern among the conductive patterns.

[0060] The second stacked body ST2 can be penetrated by the first slit S1. The second conductive pattern CP2 of the second stacked body ST2 can be separated into drain select lines DSL1 and DSL2 through the first slit S1. According to an embodiment, each of the gate stacked bodies GSTa, GSTb, and GSTc can include a first drain select line DSL1 and a second drain select line DSL2 separated by the first slit S1.

[0061] The gate stacked bodies GSTa, GSTb, and GSTc can be separated from each other by the second slit S2, and each second slit S2 is formed deeper than the first slit S1. A spacer insulating layer SP can be formed on the sidewalls of each second slit S2, and a vertical structure 60 can be formed inside each second slit S2. According to an embodiment, the vertical structure 60 contacts the source layer SLa and can include a conductive material filling the inside of each second slit S2. The present disclosure is not limited thereto. According to an embodiment, the vertical structure 60 can include an insulating material.

[0062] The first stacked body ST1 and the second stacked body ST2 of each of the gate stacked bodies GSTa, GSTb, and GSTc can be penetrated by a plurality of channel structures CH. The plurality of channel structures CH can be arranged in a plurality of channel columns. The channel structures arranged in each channel column can include channel structures arranged in a straight line in the direction in which the bit line BL extends. According to an embodiment, the channel structures arranged in each channel column can include first channel structures CH11 and CH12 and second channel structures CH21 and CH22. The first channel structures CH11 and CH12 can be provided on one side of the first slit S1, and the second channel structures CH21 and CH22 can be provided on the other side of the first slit S1. In other words, the first slit S1 can be provided between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22.

[0063] According to an embodiment, the first channel structures CH11 and CH12 can extend to penetrate the first drain select line DSL1 and the first stacked body ST1. The second channel structures CH21 and CH22 can extend to penetrate the second drain select line DSL2 and the first stacked body ST1. Each of the second conductive pattern CP2, the second interlayer insulating layer ILD2, the first conductive pattern CP1, and the first interlayer insulating layer ILD1 can extend to surround the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22.

[0064] Each bit line BL can be electrically connected to any one of the first channel structures CH11 and CH12 and any one of the second channel structures CH21 and CH22 via a drain contact plug DCT.

[0065] Dummy channel structure DCH may be disposed between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22. The dummy channel structure DCH may penetrate the first stack ST1. The first slit S1 may overlap with the dummy channel structure DCH.

[0066] Each channel structure CH may include a core insulating layer CO, a doped semiconductor pattern DP, and a channel layer CL (see Figure 5 ). The dummy channel structure DCH may include a dummy core insulating layer CO′ and a dummy channel layer CL′.

[0067] The core insulating layer CO may be vertically formed at the center of each channel structure CH and may be surrounded by the first stack ST1. The doped semiconductor pattern DP may overlap with the core insulating layer CO and may be surrounded by the second conductive pattern CP2 and the second interlayer insulating layer ILD2. According to an embodiment, the doped semiconductor pattern DP may include an n-type doped silicon layer. The channel layer CL may extend along the sidewall of the core insulating layer CO. That is, the channel layer CL may be configured to surround the sidewall of the core insulating layer CO. The first end of the channel layer CL may have a protrusion extending into the doped semiconductor pattern DP. The second end of the channel layer CL may extend between the source layer SLa and the core insulating layer CO and may contact the source layer SLa. According to an embodiment, each of the channel layer CL and the dummy channel layer CL′ may include an undoped silicon layer. The space between the first end of the channel layer CL and the second conductive pattern CP2 may be filled with the doped semiconductor pattern DP.

[0068] The dummy memory layer ML′ may extend on the sidewall of the isolation insulating layer 50. The isolation insulating layer 50 may be disposed between the first drain selection line DSL1 and the second drain selection line DSL2. The isolation insulating layer 50 may fill the first slit S1 and may overlap with the dummy channel structure DCH. The dummy memory layer ML′ may include the same material layers as the memory layer ML.

[0069] Although not shown in the figure, an upper insulating layer penetrated by the drain contact plug DCT may be disposed between the second stack ST2 and the plurality of bit lines BL.

[0070] The sidewalls of each channel structure CH can be surrounded by a memory layer ML. The sidewalls of the dummy channel structure DCH can be surrounded by a dummy memory layer ML'. The memory layer ML can be configured to surround a portion of the sidewall of the second conductive pattern CP2. Accordingly, the lower sidewall of the second conductive pattern CP2 can be in contact with the memory layer ML, and the upper sidewall of the second conductive pattern CP2 can be in contact with the doped semiconductor pattern DP. In an embodiment, the lower sidewall of the second conductive pattern CP2 can be at a level that horizontally overlaps a portion of the memory layer, and the upper sidewall of the second conductive pattern CP2 can be at a level that horizontally overlaps a portion of the doped semiconductor pattern DP. For example, the lower sidewall of the second conductive pattern CP2 can be at a level that horizontally overlaps a portion of the memory layer, as Figure 5 shown. For example, the upper sidewall of the second conductive pattern CP2 can be at a level that horizontally overlaps a portion of the doped semiconductor pattern DP, as Figure 5 shown. Since the doped semiconductor pattern DP can be surrounded by at least a portion of the second conductive pattern CP2, a junction overlap region can be ensured at the channel under the drain select transistor. Accordingly, during an erase operation of the semiconductor memory device, a gate-induced drain leakage (GIDL) current generated at the channel under the drain select transistor can increase. The GIDL current can be generated due to a difference between an erase voltage applied to the bit line BL and a gate voltage applied to the second conductive pattern CP2.

[0071] A first barrier layer (not shown) can be disposed between the first stack ST1 and the memory layer ML and between the second conductive pattern CP2 and the memory layer ML.

[0072] Figure 5 is Figure 4 an enlarged cross-sectional view of region A shown.

[0073] Referring to Figure 5 , the memory layer ML can include a tunnel insulating layer TI and a data storage layer DL. The tunnel insulating layer TI can surround the sidewalls of the channel layer CL. The tunnel insulating layer TI can include an insulating material that enables charge tunneling. According to an embodiment, the tunnel insulating layer TI can include a silicon oxide layer. The data storage layer DL can surround the sidewalls of the tunnel insulating layer TI. The data storage layer DL can include a material layer capable of storing data. To this end, the data storage layer DL can be formed of a nitride layer that enables charge trapping. The present disclosure is not limited thereto, and the data storage layer DL can include a phase change material, nanodots, etc.

[0074] The memory layer ML may extend along the sidewalls of the first interlayer insulating layer ILD1 and the first conductive pattern CP1 to the height of the middle portion of the sidewall of the second conductive pattern CP2. That is, the memory layer ML may overlap with the middle portion of the sidewall of the second conductive pattern CP2. In an embodiment, the memory layer ML may overlap with a portion of the sidewall of the second conductive pattern CP2. In an embodiment, the memory layer ML may surround the channel layer CL and may extend to a height lower than the upper surface of the channel layer CL that contacts the doped semiconductor pattern DP, as Figure 5 shown. In an embodiment, a portion of the sidewall of the second conductive pattern CP2 overlaps with the memory layer ML, and the remaining portion of the sidewall of the second conductive pattern CP2 except for the portion overlapping with the memory layer ML overlaps with the doped semiconductor pattern DP.

[0075] The channel layer CL may surround the sidewall of the core insulating layer, and the channel layer CL may include a protrusion PT extending into the doped semiconductor pattern DP. Accordingly, a portion of the doped semiconductor pattern DP is disposed in the space between the second conductive pattern CP2 and the protrusion PT of the channel layer CL. That is, the channel layer CL may overlap with the upper portion of the sidewall of the second conductive pattern CP2. In an embodiment, the channel layer CL may overlap with a portion of the sidewall of the second conductive pattern CP2. In an embodiment, the height of the channel layer CL may be greater than the height at which the memory layer contacts the doped semiconductor pattern DP, as Figure 5 shown.

[0076] In the above embodiments, the memory layer ML has been described as extending to the height of the middle portion of the sidewall of the second conductive pattern CP2, the channel layer CL has been described as extending to the upper portion of the sidewall of the second conductive pattern CP2, and the upper portion of the sidewall of the second conductive pattern CP2 has been described as higher than the middle portion of the sidewall of the second conductive pattern CP2. However, the upper portion and the middle portion of the sidewall of the second conductive pattern CP2 are not limited to specific positions in the sidewall of the second conductive pattern CP2.

[0077] The first barrier insulating layer BI1 may surround the sidewall of the data storage layer DL. The first barrier insulating layer BI1 may extend along the sidewall of the doped semiconductor pattern DP. The first barrier insulating layer BI1 may be disposed along the sidewalls of the first conductive pattern CP1, the first interlayer insulating layer ILD1, the second conductive pattern CP2, and the second interlayer insulating layer ILD2. The first barrier insulating layer BI1 may include an oxide.

[0078] The first conductive pattern CP1 may surround the memory layer ML between the first interlayer insulating layers ILD1. The first conductive pattern CP1 may include a conductive material having a lower resistance than silicon. According to an embodiment, the first conductive pattern CP1 may include a metal layer.

[0079] A second blocking insulating layer BI2 may be further formed between the first conductive pattern CP1 and the first blocking insulating layer BI1. The second blocking insulating layer BI2 may include an insulating material having a higher dielectric constant than the first blocking insulating layer BI1. According to an embodiment, the second blocking insulating layer BI2 may include a metal oxide layer. According to an embodiment, the metal oxide may include an alumina layer. The second blocking insulating layer BI2 may extend along the surface between the first conductive pattern CP1 and the first interlayer insulating layer ILD1.

[0080] A second conductive pattern CP2 may surround the memory layer ML between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. In addition, the second conductive pattern CP2 may surround a portion of the doped semiconductor pattern DP between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. For example, a lower portion of the sidewall of the second conductive pattern CP2 may surround the memory layer ML, and an upper portion of the sidewall of the second conductive pattern CP2 may surround a portion of the doped semiconductor pattern DP. That is, the doped semiconductor pattern DP may overlap with an upper portion of the sidewall of the second conductive pattern CP2. In an embodiment, the doped semiconductor pattern DP may overlap with a portion of the sidewall of the second conductive pattern CP2.

[0081] The second conductive pattern CP2 may be used as a Figure 2 drain select line DSL connected to the gate of the drain select transistor DST as shown. In an embodiment, the channel layer CL may vertically extend up to the height of an upper portion of at least one uppermost conductive pattern (i.e., Figure 4 and Figure 5 CP2) among the conductive patterns. In an embodiment, the memory layer ML surrounds the channel layer CL and extends from a lower interlayer insulating layer (i.e., any one of the interlayer insulating layers ILD1 as shown in Figure 4 and Figure 5 ) to a height substantially equal to the middle portion of the upper conductive pattern (i.e., Figure 4 and Figure 5 CP2).

[0082] Figure 4 and Figure 5 The semiconductor memory device shown may be applied to the Figure 3A semiconductor memory device 10A shown. Figure 4 and Figure 5 The semiconductor memory device shown may be applied to the Figure 3B semiconductor memory device 10B shown after being turned upside down.

[0083] The channel layer CL may penetrate the memory layer ML and include a bottom surface in contact with the source layer SLa, asFigure 4 as shown. Embodiments of the present disclosure are not limited thereto.

[0084] Figure 6 is a cross-sectional view illustrating a source layer SLb and a channel structure CH according to an embodiment of the present disclosure. Figure 6 The structure shown can be applied to Figure 3A the semiconductor memory device 10A shown.

[0085] Referring to Figure 6 , the source layer SLb may include a first layer SL1 and a second layer SL2, or may include a first layer SL1, a second layer SL2, and a third layer SL3. The first layer SL1 may overlap with the first stacked body ST1. The second layer SL2 may be disposed between the first stacked body ST1 and the first layer SL1. The third layer SL3 may be disposed between the second layer SL2 and the first stacked body ST1.

[0086] Each of the first layer SL1, the second layer SL2, and the third layer SL3 may include a doped semiconductor layer. According to an embodiment, each of the first layer SL1, the second layer SL2, and the third layer SL3 may include n-type doped silicon.

[0087] The first stacked body ST1 may include an interlayer insulating layer ILD1 and a first conductive pattern CP1 that are alternately stacked, as described with reference to Figure 4 , and may be penetrated by the channel structure CH.

[0088] An end EP of the channel structure CH may penetrate the third layer SL3 and the second layer SL2, and may extend into the first layer SL1. According to an embodiment, a channel layer CL and a core insulating layer CO may penetrate the third layer SL3 and the second layer SL2, and may extend into the first layer SL1.

[0089] Each of the data storage layer DL and the tunnel insulating layer TI may be separated by the second layer SL2 into a first memory pattern ML1 and a second memory pattern ML2. The second layer SL2 protrudes toward the channel layer CL with respect to the first layer SL1 and the third layer SL3, and may be in contact with the channel layer CL. A first barrier insulating layer BI1 may be disposed so as to be in contact with a sidewall of the first memory pattern ML1. That is, the first barrier insulating layer BI1 may be disposed between the sidewall of the first memory pattern ML1 and the sidewalls of the third layer SL3, the interlayer insulating layer ILD1, and the first conductive pattern CP1. In addition, the first barrier insulating layer BI1 may be disposed so as to be in contact with the sidewall and the lower surface of the second memory pattern ML2. That is, the first barrier insulating layer BI1 may be disposed between the sidewall of the second memory pattern ML2 and the sidewall of the first layer SL1 and between the lower surface of the second memory pattern ML2 and the lower surface of the first layer SL1.

[0090] The first blocking insulating layer BI1, the data storage layer DL, and the tunnel insulating layer TI can extend from between the first stack ST1 and the channel layer CL to between the third stack SL3 and the channel layer CL. The data storage layer DL, the tunnel insulating layer TI, and the first blocking insulating layer BI1 of the second memory pattern ML2 can extend between the first stack SL1 and the channel layer CL.

[0091] The second blocking insulating layer BI2 can be disposed between the first blocking insulating layer BI1 of the first memory pattern ML1 and the first conductive pattern CP1.

[0092] Figure 7 is a cross-sectional view illustrating a source layer SLc and a channel structure CH according to an embodiment of the present disclosure. Figure 7 The structure shown can be applied to Figure 3B the semiconductor memory device 10B shown.

[0093] Referring to Figure 7 , the source layer SLc can overlap with the first stack ST1 and can include a doped semiconductor layer. According to an embodiment, the source layer SLc can include n-type doped silicon. The first stack ST1 can be disposed between the source layer SLc and the second stack ST2 described with reference to Figure 4 .

[0094] The first stack ST1 can include an alternating stack of a first interlayer insulating layer ILD1 and a first conductive pattern CP1, as described with reference to Figure 4 , and can be penetrated by the channel structure CH.

[0095] The end EP′ of the channel structure CH can penetrate the first blocking insulating layer BI1, penetrate the data storage layer DL and the tunnel insulating layer TI of the memory layer ML, and extend into the source layer SLc. According to an embodiment, the channel layer CL and the core insulating layer CO can extend into the source layer SLc. The portion of the channel layer CL that forms the end EP′ of the channel structure CH can be in contact with the source layer SLc.

[0096] Figures 8A to 8C , Figures 9A to 9C , and Figures 10A to 10C are cross-sectional views illustrating a method of manufacturing a memory cell array according to an embodiment of the present disclosure.

[0097] Figures 8A to 8C is a cross-sectional view illustrating a step of forming a preliminary stack 110 and a step of forming a channel structure that penetrates the preliminary stack 110 and is surrounded by a memory layer 130A.

[0098] Referring to Figure 8A, the step of forming the preliminary laminate 110 may include the step of alternately laminating the first interlayer insulating layer 101 and the sacrificial layer 103. Each sacrificial layer 103 may include a material having an etching selectivity with respect to the first interlayer insulating layer 101. According to an embodiment, the first interlayer insulating layer 101 may include silicon oxide, and the sacrificial layer 103 may include silicon nitride. Then, a second interlayer insulating layer 105 is formed on the uppermost laminated sacrificial layer 103. For example, the first interlayer insulating layer 101 and the sacrificial layer 103 are alternately laminated on a semiconductor substrate, and the second interlayer insulating layer 105 is laminated on the uppermost laminated sacrificial layer 103, thereby forming the preliminary laminate 110.

[0099] Then, a mask layer 121 is formed above the preliminary laminate 110. The mask layer 121 may include a nitride layer.

[0100] Referring to Figure 8B , the channel hole 125A may be formed by etching the mask layer 121 and the preliminary laminate 110. The channel hole 125A may penetrate the preliminary laminate 110. In the step of forming the channel hole 125A, dummy holes 125B penetrating the preliminary laminate 110 may be formed simultaneously with the channel hole 125A.

[0101] The mask layer 121 and the preliminary laminate 110 may be etched by using a photoresist pattern (not shown) formed by a photolithography process as an etching barrier to define the channel hole 125A and the dummy holes 125B. After the channel hole 125A and the dummy holes 125B are formed, the photoresist pattern may be removed.

[0102] Referring to Figure 8C , a memory layer ML covering the surfaces of the channel hole and the dummy holes and extending above the surface of the mask layer 121 may be formed. The memory layer ML may include a data storage layer and a tunnel insulating layer. Then, a channel layer CL may be formed along the surface of the memory layer ML.

[0103] After the channel layer CL is formed, the central regions of the channel hole and the dummy holes may be filled with a core insulating layer CO.

[0104] Figures 9A to 9C is an enlarged cross-sectional view and illustrates an embodiment of the steps of forming the memory layer ML, the channel layer CL, the core insulating layer CO, and the doped semiconductor pattern DP in the channel hole.

[0105] Referring to Figure 9A , forming Figure 8C The steps of forming the memory layer ML, the channel layer CL, and the core insulating layer CO shown may include the step of forming a first barrier insulating layer BI1 on the surface of each of the channel hole and the dummy holes. The first barrier insulating layer BI1 may include an oxide.

[0106] Then, a data storage layer DL and a tunnel insulating layer TI are sequentially formed along the surface of the first blocking insulating layer BI1, whereby a memory layer ML can be formed. The tunnel insulating layer TI may include an insulating material that enables charge tunneling. According to an embodiment, the tunnel insulating layer TI may include a silicon oxide layer. The data storage layer DL may include a material layer capable of storing data. To this end, the data storage layer DL may be formed of a nitride layer that enables charge trapping. The present disclosure is not limited thereto, and the data storage layer DL may include a phase change material, nanodots, etc.

[0107] Then, a channel layer CL may be formed along the surface of the tunnel insulating layer TI. The channel layer CL may include a silicon layer.

[0108] Then, a core insulating layer CO is formed along the surface of the channel layer CL. In this case, the core insulating layer CO may be formed to fill the inside of the channel hole. The core insulating layer CO may be formed by depositing an oxide layer using an atomic layer deposition (ALD) method. Then, an etch-back process may be performed on the core insulating layer CO such that the core insulating layer CO remains only inside the channel hole.

[0109] Referring to Figure 9B , the core insulating layer CO may be etched by a dry etching process such that the upper surface of the core insulating layer CO is positioned at a height corresponding to the middle portion of at least one of the uppermost sacrificial layers 103 among the sacrificial layers 103.

[0110] Then, the exposed channel layer CL may be etched such that the upper surface of the channel layer CL is positioned at a height corresponding to the upper portion of the uppermost sacrificial layer 103 among the sacrificial layers 103.

[0111] Then, the exposed tunnel insulating layer TI and the data storage layer DL may be sequentially etched such that the upper surface of the memory layer ML is positioned at a height corresponding to the middle portion of the uppermost sacrificial layer 103 among the sacrificial layers 103.

[0112] Accordingly, the channel layer CL has a protrusion PT that protrudes with respect to the upper surfaces of the memory layer ML and the core insulating layer CO. The protrusion PT extends up to a height corresponding to the upper portion of the uppermost sacrificial layer 103.

[0113] In accordance with Figure 9BIn the above-described embodiment, the exposed tunnel insulating layer TI and the data storage layer DL are sequentially etched such that the upper surface of the memory layer ML is positioned at a height corresponding to the middle portion of the sacrificial layer 103. However, according to another embodiment, an etching process may be performed such that only the tunnel insulating layer TI is etched to position the upper surface of the tunnel insulating layer TI at a height corresponding to the middle portion of the sacrificial layer 103, and such that the data storage layer DL remains at the sidewalls of the protrusion PT.

[0114] Referring to Figure 9C , a doped semiconductor layer is deposited on the entire structure including the memory layer ML, the protrusion PT of the channel layer CL, and the upper portion of the core insulating layer CO, and a planarization etching process is performed such that the mask layer is exposed, thereby forming a doped semiconductor pattern DP above the memory layer ML, the protrusion PT of the channel layer CL, and the core insulating layer CO. The doped semiconductor pattern DP may include an n-type doped silicon layer. The doped semiconductor pattern DP is formed between the protrusion PT and the first barrier insulating layer BI1 and in the space above the core insulating layer CO. Accordingly, the protrusion PT has a structure extending into the doped semiconductor pattern DP. In addition, the doped semiconductor pattern DP is formed in the upper sidewall portion of the uppermost sacrificial layer 103, and the first barrier insulating layer BI1 is between the upper sidewall portion and the doped semiconductor pattern DP.

[0115] Figures 10A to 10C An embodiment exemplifying the steps of forming a first conductive pattern and a second conductive pattern in the space between the first interlayer insulating layers 101 is shown.

[0116] Referring to Figure 10A , after performing the process shown in Figure 9C , a mask layer 131 for forming a slit is formed on the entire structure including the doped semiconductor pattern DP. Then, an etching process is performed using the mask layer 131 for forming a slit to sequentially etch the second interlayer insulating layer 105 and the sacrificial layer and the first interlayer insulating layer stacked alternately, thereby forming a second slit 141. Then, the sacrificial layer exposed through the second slit 141 is removed. Accordingly, empty spaces are formed between the first interlayer insulating layers 101 and between the uppermost first interlayer insulating layer 101 and the second interlayer insulating layer 105.

[0117] Referring to Figure 10B, the empty spaces between the first interlayer insulating layers 101 and between the first interlayer insulating layer 101 and the second interlayer insulating layer 105 are filled with a conductive material, thereby forming a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 and the second conductive pattern CP2 may include a conductive material having a lower resistance than silicon. According to an embodiment, the first conductive pattern CP1 and the second conductive pattern CP2 may include a metal layer. The first conductive pattern CP1 is formed in the space between the first interlayer insulating layers 101, and the second conductive pattern CP2 is formed in the space between the uppermost first interlayer insulating layer 101 and the second interlayer insulating layer 105.

[0118] Before forming the first conductive pattern CP1 and the second conductive pattern CP2, a second barrier insulating layer BI2 may be formed on the surface of the empty space. The second barrier insulating layer BI2 may include an insulating material having a higher dielectric constant than the first barrier insulating layer BI1. According to an embodiment, the second barrier insulating layer BI2 may include an alumina layer.

[0119] Referring to Figure 10C , the second slit 141 is filled with an insulating material 142. Then, a first slit 151 is formed on the dummy channel structure. The first slit 151 may be formed in a line shape, and the second conductive pattern CP2 surrounding the dummy channel structure is separated into two ends by the first slit 151. Then, the first slit 151 is filled with an insulating material 152.

[0120] According to the above embodiment of the present disclosure, a doped semiconductor pattern DP is provided in a part of the channel region of the drain select transistor, and a channel layer CL is provided in the remaining part thereof. Therefore, even if an impurity diffusion process by heat treatment is not performed, a doped semiconductor pattern DP doped with impurities is provided in the channel region of the drain select transistor, thereby forming a junction overlap region. Therefore, during the erase operation of the semiconductor memory device, the gate-induced drain leakage (GIDL) current generated at the channel under the drain select transistor can be increased.

[0121] Figure 11 is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0122] Referring to Figure 11 , the memory system 1100 includes a semiconductor memory device 1120 and a memory controller 1110.

[0123] The semiconductor memory device 1120 may include: a selection line penetrated by a hole, a memory layer formed on the sidewall of the hole, and a doped semiconductor pattern filling a part of the hole. The semiconductor memory device 1120 may be configured as Figure 4 the semiconductor memory device shown.

[0124] The semiconductor memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0125] The memory controller 1110 is configured to control the semiconductor memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112. The CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 has a data exchange protocol with the host coupled to the memory system 1100. In addition, the error correction block 1114 detects and corrects errors included in the data read from the memory device 1120, and the memory interface 1115 performs an interface connection with the memory device 1120. Additionally, the memory controller 1110 may further include a read-only memory (ROM) configured to store code data for interface connection with the host.

[0126] Figure 12 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure.

[0127] Referring to Figure 12 , a computing system 1200 according to an embodiment of the present disclosure may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically coupled to a system bus 1260. The computing system 1200 may be a mobile device.

[0128] The memory system 1210 may include a semiconductor memory device 1212 and a memory controller 1211. The semiconductor memory device 1212 may include: a selection line penetrated by a hole, a memory layer formed on a sidewall of the hole, and a doped semiconductor pattern filling a part of the hole. The semiconductor memory device 1212 may be configured to Figure 4 the semiconductor memory device shown in

[0129] The present disclosure can stably generate a gate-induced drain leakage (GIDL) current for an erase operation by improving characteristics of a drain selection transistor, thereby improving the reliability of operations of a semiconductor memory device.

[0130] Although examples of embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are also possible. Therefore, the scope of the present disclosure must be defined by the appended claims and equivalents of the claims, rather than by the description preceding them.

[0131] Cross - reference to related applications

[0132] This application claims priority to Korean Patent Application No. 10 - 2020 - 0076050, filed on June 22, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A stack including an interlayer insulating layer and a conductive pattern alternately stacked; And A channel structure penetrating the stack, Wherein each of the plurality of channel structures includes: A channel layer vertically extending up to a height of an upper portion of at least one upper conductive pattern disposed at the top among the plurality of conductive patterns; A memory layer surrounding the channel layer and extending from a lower interlayer insulating layer to a height of an intermediate portion of the upper conductive pattern; and A doped semiconductor pattern disposed above the channel layer and the memory layer, Wherein the doped semiconductor pattern is surrounded by at least a part of the upper conductive pattern.

2. The semiconductor memory device according to claim 1, wherein, The channel layer includes a protrusion extending into the doped semiconductor pattern.

3. The semiconductor memory device according to claim 2, wherein, The doped semiconductor pattern includes a portion disposed in a space between the intermediate portion of the upper conductive pattern and the protrusion.

4. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A first blocking insulating layer surrounding sidewalls of each of the plurality of channel structures.

5. The semiconductor memory device according to claim 1, wherein, The upper conductive pattern is a drain selection line connected to a drain selection transistor included in a cell string.

6. The semiconductor memory device according to claim 1, wherein The doped semiconductor pattern includes an n-type doped silicon layer, and The channel layer includes an undoped silicon layer.

7. The semiconductor memory device according to claim 1, wherein, A lower portion of a sidewall of the upper conductive pattern overlaps with the memory layer, and An upper portion of the sidewall of the upper conductive pattern overlaps with the doped semiconductor pattern.

8. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A core insulating layer vertically extending in the channel layer, Wherein An upper surface of the core insulating layer is lower than an upper surface of the channel layer, and The upper surface of the core insulating layer contacts the doped semiconductor pattern.

9. A semiconductor memory device, the semiconductor memory device comprising: A stack including an interlayer insulating layer and a conductive pattern alternately stacked; And A channel structure penetrating the stack, Wherein each of the plurality of channel structures includes: A channel layer extending up to a height of a part of at least one upper conductive pattern disposed at the top among the plurality of conductive patterns; A memory layer surrounding the channel layer and extending up to a height lower than an upper surface of the channel layer; and A doped semiconductor pattern disposed above the channel layer and the memory layer, The channel layer includes a protrusion protruding relative to an upper surface of the memory layer and extending into the doped semiconductor pattern, and Wherein the doped semiconductor pattern is surrounded by at least a part of the at least one upper conductive pattern.

10. The semiconductor memory device according to claim 9, wherein, The doped semiconductor pattern includes a portion disposed in a space between the upper conductive pattern and the protrusion.

11. The semiconductor memory device according to claim 9, further comprising: A first blocking insulating layer that surrounds sidewalls of each of the plurality of channel structures.

12. The semiconductor memory device according to claim 9, wherein, The upper conductive pattern is a drain selection line connected to a drain selection transistor included in a cell string.

13. The semiconductor memory device according to claim 9, wherein, The doped semiconductor pattern includes an n-type doped silicon layer, and The channel layer includes an undoped silicon layer.

14. The semiconductor memory device according to claim 9, wherein, A part of sidewalls of the upper conductive pattern overlaps with the memory layer, and The remaining parts of the sidewalls of the upper conductive pattern except the part overlap with the doped semiconductor pattern.

15. A method of manufacturing a semiconductor memory device, the method comprising the steps of: Forming a preliminary stack including alternately stacked interlayer insulating layers and sacrificial layers; Forming a channel hole through the preliminary stack; Forming a memory layer extending along sidewalls of the channel hole; Forming a channel layer extending along a surface of the memory layer; Forming a core insulating layer along a surface of the channel layer and filling the channel hole with the core insulating layer; Etching the core insulating layer, the channel layer, and the memory layer provided in an upper part of the channel hole such that the channel layer has a protruding portion protruding with respect to the core insulating layer and the memory layer; And Forming a doped semiconductor pattern in the upper part of the channel hole, Wherein the doped semiconductor pattern is surrounded by at least a part of an upper sacrificial layer provided at the uppermost among the plurality of sacrificial layers.

16. The method according to claim 15, wherein, The etching of the core insulating layer, the channel layer, and the memory layer is configured to: Etch the core insulating layer and the memory layer such that upper surfaces of the core insulating layer and the memory layer are positioned at a height corresponding to a part of sidewalls of the upper sacrificial layer, and Etch the channel layer such that an upper surface of the channel layer is higher than upper surfaces of the core insulating layer and the memory layer.

17. The method according to claim 15, wherein, Forming the doped semiconductor pattern is configured to form the doped semiconductor pattern such that the protruding portion of the channel layer extends into the doped semiconductor pattern.

18. The method according to claim 15, the method further comprising the steps of: Forming a blocking insulating layer extending along a surface of the channel hole before forming the memory layer.

19. The method according to claim 15, the method further comprising the steps of: Forming a slit penetrating the preliminary stack; Removing the sacrificial layer exposed through the slit; And Forming a conductive pattern in a space where the sacrificial layer has been removed.

20. The method according to claim 19, wherein, A part of sidewalls of an upper conductive pattern provided at the uppermost among the plurality of conductive patterns overlaps with the memory layer, and The remaining parts of the sidewalls of the upper conductive pattern except the part overlap with the doped semiconductor pattern.

Images