Variable resistance storage devices

Abstract

A variable resistance storage device includes: a first conductive line; a second conductive line disposed on the first conductive line; a first unit structure at the intersection between the first and second conductive lines, each first unit structure including a switch pattern and a variable resistance pattern; a first buried structure filling a first trench between the first conductive lines; and a second buried structure filling a second trench between the first unit structures. Each first buried structure includes a first pad pattern covering the sidewall of a corresponding first trench, a first filling pattern disposed on the first pad pattern and in the corresponding first trench, and a first covering pattern sealing the corresponding first trench. The second buried structure extends in the plurality of second trenches and connects to the first covering pattern of the first buried structure.

Description

Technical Field

[0001] The present invention relates to semiconductor memory devices, and more specifically, to variable resistance memory devices. Background Technology

[0002] Semiconductor devices can be classified into memory devices and logic devices. Memory devices store data. Generally, semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), lose the stored data when their power supply is interrupted. Non-volatile memory devices, such as Programmable ROM (PROM), Erasable ROM (EPROM), Electrically Erasable ROM (EEPROM), and Flash Memory devices, retain their stored data even when their power supply is interrupted. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide variable resistance storage devices capable of avoiding tilting or bridging that may occur during patterning.

[0004] According to an exemplary embodiment of the present invention, a variable resistance storage device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction intersecting the first direction and arranged on the plurality of first conductive lines; a plurality of first unit structures at the intersections between the plurality of first conductive lines and the plurality of second conductive lines, each first unit structure including a switch pattern and a variable resistance pattern; a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction; and a plurality of second buried structures filling a plurality of second trenches between the plurality of first unit structures. Each of the plurality of first buried structures includes: a first pad pattern covering the sidewall of a corresponding first trench among the plurality of first trenches; a first filling pattern disposed on the first pad pattern and in the corresponding first trench; and a first covering pattern sealing the corresponding first trench in which the first pad pattern and the first filling pattern are provided. The plurality of second buried structures extend in the plurality of second trenches and are connected to the plurality of first covering patterns of the plurality of first buried structures.

[0005] According to an exemplary embodiment of the present invention, a variable resistance storage device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction intersecting the first direction and arranged on the plurality of first conductive lines; a plurality of first unit structures at the intersections between the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first unit structures including a switch pattern and a variable resistance pattern; and a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction. Each of the plurality of first buried structures includes: a first pad pattern covering the sidewall of a corresponding first trench among the plurality of first trenches; a first pad pattern on the first pad pattern and in the corresponding first trench; and a cover pattern disposed in the corresponding first trench. The cover pattern covers the top surface of the first pad pattern and the top surface of the first filling pattern. The bottom surface of the cover pattern has a raised shape toward the first filling pattern. The lowest bottom surface of the cover pattern is located at a level equal to or greater than approximately 2 / 3 times the height of the first conductive line among the plurality of first conductive lines. The first conductive lines are adjacent to the corresponding first trenches.

[0006] According to an exemplary embodiment of the present invention, a variable resistance storage device includes: a substrate; a plurality of first conductive lines on the substrate extending in a first direction; a plurality of second conductive lines extending in a second direction intersecting the first direction and arranged on the plurality of first conductive lines; a plurality of first unit structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines; a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction; and a plurality of second buried structures filling a plurality of second trenches between the plurality of first unit structures. Each of the plurality of first buried structures includes: a first pad pattern covering the sidewall of a corresponding first trench among the plurality of first trenches; a first filling pattern on the first pad pattern and in the corresponding first trench; and a first overlay pattern on the first filling pattern and in the corresponding first trench. Each of the plurality of second buried structures includes a second pad pattern and a second filling pattern. Each of the plurality of first unit structures includes a first electrode, a switch pattern, a second electrode, a variable resistance pattern, and a third electrode provided sequentially. Multiple second burial structures extend in multiple second trenches and are connected to multiple first covering patterns of multiple first burial structures.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a variable resistance memory device includes forming a plurality of first conductive lines extending in a first direction on a substrate, forming a plurality of first buried structures between the plurality of first conductive lines, forming a plurality of first cell structures on the plurality of first conductive lines, and forming a plurality of second buried structures between the plurality of first cell structures. The formation of the plurality of first buried structures includes: forming a first pad layer and a first fill layer, the first pad layer and the first fill layer filling a plurality of trenches between the plurality of first conductive lines; performing a planarization process to expose the top surfaces of the plurality of first conductive lines and to recess the upper portions of the first fill layer and the first pad layer, the recessed first fill layer and the recessed first pad layer being respectively divided into a plurality of first fill patterns and a plurality of first pad patterns, the top surfaces of the plurality of first fill patterns and the top surfaces of the plurality of first pad patterns being located below the exposed top surfaces of the plurality of first conductive lines to form a plurality of first recessed regions between the plurality of first conductive lines; and forming a plurality of preliminary cover patterns filling the plurality of first recessed regions. Attached Figure Description

[0008] Figure 1 A conceptual diagram illustrating some example embodiments of a variable resistance storage device according to the present invention is shown.

[0009] Figure 2 The display shows Figure 1 A circuit diagram of stacked storage cells.

[0010] Figure 3 A plan view is shown illustrating some example embodiments of a variable resistance storage device according to a concept conceived in this invention.

[0011] Figure 4 It shows along Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0012] Figure 5 , Figure 6A and Figure 6B The display shows Figure 4 A magnified view of part of Q.

[0013] Figure 6C The display shows Figure 4 A magnified view of part S.

[0014] Figure 7 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0015] Figure 8 and Figure 9 It shows Figure 7 A magnified view of part Q'.

[0016] Figure 10 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0017] Figure 11 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0018] Figure 12 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0019] Figures 13 to 22 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0020] Figure 23 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0021] Figures 24 to 26 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'. Detailed Implementation

[0022] Figure 1 A conceptual diagram illustrating some example embodiments of a variable resistance storage device according to a concept based on the present invention is shown. (Refer to...) Figure 1 A variable resistance memory device according to some exemplary embodiments of the present invention may include a plurality of memory cell stacks (MCAs) sequentially stacked on a substrate 100. Each memory cell stack (MCA) may include a plurality of variable resistance memory cells arranged in a two-dimensional manner. A variable resistance memory device according to some exemplary embodiments of the present invention may include a plurality of conductive lines configured to be located between the memory cell stacks (MCAs) for writing, reading and erasing the memory cells. Figure 1 Five memory cells stacked on an MCA are shown, but some exemplary embodiments of the inventive concept are not limited thereto.

[0023] Figure 2 The display shows Figure 1A circuit diagram of stacked storage cells. Figure 2 The diagram shows first cell stacks MCA1 through fourth cell stacks MCA4, or alternatively, more or fewer than four cell stacks may be provided. For example, a variable resistive storage device according to some exemplary embodiments of the invention may include two cell stacks (e.g., first cell stack MCA1 and second cell stack MCA2). First cell stack MCA1 may include a cell structure MC provided at the intersection between a first conductive line CL1 and a second conductive line CL2. Similar to first cell stack MCA1, second cell stack MCA2 may include a cell structure MC provided at the intersection between a second conductive line CL2 and a third conductive line CL3. First cell stack MCA1 and second cell stack MCA2 may share the second conductive line CL2. Alternatively, second cell stack MCA2 may not share any conductive line with first cell stack MCA1. (See also...) Figure 12 The implementation of the third memory cell stack MCA3 and the fourth memory cell stack MCA4 will be discussed.

[0024] The cell structures MC of the first memory cell stack MCA1 can be arranged two-dimensionally on the substrate in rows and columns. Each cell structure MC may include a switch pattern and a variable resistor pattern. When a first conductive line CL1 is provided between the substrate and a second conductive line CL2, each cell structure MC can be configured such that the switch pattern is provided between the substrate and the variable resistor pattern. Alternatively, the variable resistor pattern can be provided between the substrate and the switch pattern.

[0025] A switch pattern can be provided at each intersection between the first conductive line CL1 and the second conductive line CL2, and can be physically separated from other switch patterns provided at adjacent intersections. A variable resistor pattern can be provided at a corresponding intersection between the first conductive line CL1 and the second conductive line CL2, and can be physically separated from other variable resistor patterns provided at adjacent intersections. Alternatively, multiple unit structures MC can share a physically connected variable resistor pattern. For example, when viewed in a plane, the variable resistor pattern can have a linear shape (e.g., a straight line shape) extending along the extension direction of the first conductive line CL1 or the second conductive line CL2.

[0026] Figure 3 A plan view is shown illustrating some example embodiments of a variable resistance storage device according to a concept conceived in this invention. Figure 4 It shows along Figure 3 The cross-sectional view taken by lines A-A' and B-B'. Figure 5 , Figure 6A and Figure 6B The display shows Figure 4A magnified view of part of Q. Figure 6C The display shows Figure 4 A magnified view of part S. Figures 3 to 5 and Figures 6A to 6C The embodiments shown all involve stacking two storage cells, but the inventive concept is not limited thereto.

[0027] Reference Figures 3 to 5 The variable resistance storage device may include multiple memory cell stacks MCA1 and MCA2 stacked sequentially. For example, the memory cell stacks MCA1 and MCA2 may correspond to a reference. Figure 1 and Figure 2 The discussion concerns a stack of memory cells. A first memory cell stack MCA1 may be disposed between a first conductive line CL1 and a second conductive line CL2 sequentially provided on a substrate 100. The first memory cell stack MCA1 may include a first cell structure MC1 provided at the intersection between the first conductive line CL1 and the second conductive line CL2. A second memory cell stack MCA2 may be disposed between the second conductive line CL2 and a third conductive line CL3 provided on the second conductive line CL2. The second memory cell stack MCA2 may include a second cell structure MC2 provided at the intersection between the second conductive line CL2 and the third conductive line CL3. Although Figure 3 Each of the first unit structure MC1 and the second unit structure MC2 is depicted as having a quadrilateral shape, but each of the first unit structure MC1 and the second unit structure MC2 may have an arc shape, a circular shape, or any other suitable shape and is not limited thereto.

[0028] A first conductive line CL1 may extend along a first direction D1 substantially parallel to the top surface of the substrate 100, and a second conductive line CL2 may extend along a second direction D2 intersecting the first direction D1 and substantially parallel to the top surface of the substrate 100. For example, the second direction D2 may be perpendicular to the first direction D1. A third conductive line CL3 may extend along the first direction D1 substantially parallel to the first conductive line CL1. The first conductive line CL1, the second conductive line CL2, and the third conductive line CL3 may comprise conductive materials such as tungsten, copper, or aluminum. The first conductive line CL1, the second conductive line CL2, and the third conductive line CL3 may also comprise conductive metal nitrides such as TiN or WN.

[0029] The first conductive line CL1 may have a height H0 in a third direction D3 perpendicular to the top surface of the substrate 100, which may be less than the height H1 of the second conductive line CL2. For example, the height H0 of the first conductive line CL1 may be equal to or less than half the height H1 of the second conductive line CL2. For example, the height H1 of the second conductive line CL2 may be approximately... to approximately Within the range. The height H0 of the first conductive line CL1 can be from approximately to approximately Within the range. Each first conductive line CL1 may have a width in the second direction D2 that decreases as it approaches its top surface from its bottom surface. The description of the second conductive line CL2 can be applied equally to the third conductive line CL3 and the other conductive lines discussed below. The first conductive line CL1 may have a smaller sidewall slope than the second conductive line CL2. Terms such as “about” or “approximately” may reflect quantities, sizes, orientations, or layouts that vary only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, a range from “about 0.1 to about 1” may cover ranges such as deviations of 0% to 5% around 0.1 and deviations of 0% to 5% around 1, particularly if such deviations maintain the same effect as the enumerated ranges.

[0030] An interlayer dielectric layer 110 may be provided between the substrate 100 and the first conductive line CL1. The interlayer dielectric layer 110 may include at least one selected from silicon oxide, silicon nitride, and silicon oxide nitride. A lower buried structure GS0 may be provided to fill the region between the first conductive lines CL1 and extend along the first conductive lines CL1 in a first direction D1. When viewed in a plane, each lower buried structure GS0 may have a strip shape or a line shape (e.g., a straight line shape) extending in the first direction D1. The lower buried structure GS0 may include at least one selected from silicon oxide, silicon nitride, and silicon oxide nitride. The lower buried structure GS0 may extend to the upper portion of the interlayer dielectric layer 110. For example, the lower buried structure GS0 may have its lower portion inserted into the upper portion of the interlayer dielectric layer 110.

[0031] Each first unit structure MC1 may include a switch pattern SM and a variable resistor pattern CR on the switch pattern SM. A first electrode EL1 may be provided between the switch pattern SM and the first conductive line CL1. A first metal pattern MB1 may be provided between the switch pattern SM and the variable resistor pattern CR. A second electrode EL2 may be provided between the switch pattern SM and the first metal pattern MB1. A third electrode EL3 may be provided between the variable resistor pattern CR and the second conductive line CL2. A second metal pattern MB2 may be provided between the third electrode EL3 and the variable resistor pattern CR. For example, each first unit structure MC1 may include a first electrode EL1, a switch pattern SM, a second electrode EL2, a first metal pattern MB1, a variable resistor pattern CR, a second metal pattern MB2, and a third electrode EL3 stacked sequentially on the first conductive line CL1. Although the following description will focus on the first unit structure MC1, the second unit structure MC2 and other unit structures may have the same structure as the first unit structure MC1.

[0032] The following describes an example in which a switch pattern SM can be disposed between a first electrode EL1 and a second electrode EL2, and where a variable resistor pattern CR can be disposed between a second electrode EL2 and a third electrode EL3, or alternatively where a variable resistor pattern CR can be disposed between a first electrode EL1 and a second electrode EL2 and a switch pattern SM can be disposed between a second electrode EL2 and a third electrode EL3.

[0033] The variable resistance pattern CR can be formed from any one or more materials having physical properties capable of storing data. In cases where phase-change memory devices are employed as variable resistance memory devices in some exemplary embodiments of the invention, the variable resistance pattern CR can comprise materials whose phases reversibly change between crystalline and amorphous states based on temperature. For example, the variable resistance pattern CR can have a phase transition temperature from about 250°C to about 350°C to induce a phase transition between crystalline and amorphous states. The variable resistance pattern CR can be formed from compounds in which at least one selected from Te, Se, and S is combined as a chalcogenide element with at least one selected from Ge, Sb, Bi, Pb, Sn, Ag, As, Si, In, Ti, Ga, P, O, and C. For example, the variable resistance pattern CR may include at least one selected from: binary materials, such as GeTe, GeSe, GeS, SbSe, SbTe, SbS, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, YSb, CeSb, DySb, and NdSb; ternary materials, such as GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, Ge SbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, Sc SbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, and N dSbS; quaternary materials such as GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe , BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGe SbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, and NdGeSbS;and quinary materials such as InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSbSeTl, G eScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSb The materials used are SeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn, and GeSbSeZnSn. The variable resistance pattern CR can be formed from a single layer comprising one of the above materials or from multiple layers comprising different materials from each other. Alternatively, the variable resistance pattern CR may include superlattice structures in which Ge-containing and Ge-free layers are repeatedly stacked. For example, the variable resistance pattern CR may have a structure in which GeTe layers and Sb₂Te₃ layers or GeTe layers and Bi₂Te₃ layers are repeatedly stacked. Furthermore, the variable resistance pattern CR may further include at least one material selected from B, C, N, O, P, Cd, W, Ti, Hf, and Zr added to the aforementioned material.

[0034] The variable resistor pattern CR may have recessed areas on its sidewalls. These recessed areas may be regions created when the sidewalls of the variable resistor pattern CR are recessed inwards from the sidewalls of the first metal pattern MB1 and the second metal pattern MB2. The sidewalls of the variable resistor pattern CR with recessed areas may have a concave profile.

[0035] The switching pattern SM can be a bidirectional threshold switch (OTS) device with bidirectional characteristics. For example, the switching pattern SM can be a device based on a threshold switching phenomenon exhibiting a nonlinear IV curve (e.g., an S-shaped IV curve). The switching pattern SM can be associated with a phase transition temperature between a crystalline and amorphous state, which is greater than the phase transition temperature associated with a variable resistance pattern CR. For example, the switching pattern SM can have a phase transition temperature from about 350°C to about 450°C, which is greater than the phase transition temperature of the variable resistance pattern CR. The phase transition temperature of the variable resistance pattern CR can be in the range of about 250°C to about 350°C. When the variable resistance memory device is operated according to some exemplary embodiments of the present invention, the variable resistance pattern CR can be configured to reversibly change its phase between a crystalline and amorphous state at an operating voltage, while the switching pattern SM can remain in its substantially amorphous state without phase transition at the operating voltage. In this specification, the phrase "substantially amorphous" does not exclude the presence of local grain boundaries or locally crystalline portions in the target object.

[0036] The switch pattern SM can be formed from compounds in which at least one selected from Te, Se, and S is combined as a chalcogenide with at least one selected from Ge, Sb, Bi, Al, Pb, Sn, Ag, As, Si, In, Ti, Ga, and P. For example, the switch pattern SM can include at least one selected from: binary materials such as GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, and SnTe; ternary materials such as GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe; and quaternary materials such as GeSiAsTe, GeSi... AsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAsSeBi, Ge AsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn and GeAsTeZn;Quinary materials such as GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn and GeAsSeZnSn;and six-element materials such as GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, Ge SiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiA sSeSSn,GeAsSeTeSIn,GeAsSeTeSGa,GeAsSeTeSAl,GeAsSeTeSTl,GeAsSeTeSZn,GeAsSeTeSSn,GeAsSeTeP In, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGa Sn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTe GaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeS InTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn and GeAsSeSAlSn. ;

[0037] The switch pattern SM can be formed from a single layer comprising one of the aforementioned materials or from multiple layers comprising different materials from each other. Furthermore, the switch pattern SM may further include at least one material selected from B, C, N, and O added to the aforementioned materials.

[0038] The first electrode EL1, the second electrode EL2, and the third electrode EL3 may comprise conductive materials. For example, the first electrode EL1, the second electrode EL2, and the third electrode EL3 may all be carbon-containing electrodes. The first electrode EL1, the second electrode EL2, and the third electrode EL3 may comprise one or more of a metal and a metal nitride. Each first electrode EL1 may have a width substantially the same as or greater than the width of the second conductive line CL2 below the first electrode EL1. Alternatively, as... Figure 6C As shown, each first electrode EL1 may have a width smaller than the width of the second conductive line CL2 below the first electrode EL1.

[0039] The first metal pattern MB1 and the second metal pattern MB2 can cover the top and bottom surfaces of the variable resistor pattern CR, thereby preventing the diffusion of the material included in the variable resistor pattern CR. The first metal pattern MB1 can be provided between the variable resistor pattern CR and the switch pattern SM, thereby reducing contact resistance. The first metal pattern MB1 and the second metal pattern MB2 can include at least one selected from W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0040] The first unit structure MC1 may include spacer structures SS. Each spacer structure SS may cover the sidewall of each of the first metal pattern MB1, the second metal pattern MB2, the variable resistance pattern CR, and the third electrode EL3. The spacer structure SS may have its bottom surface in contact with the top surface of the second electrode EL2. The spacer structure SS may include at least one selected from silicon oxide layers, silicon nitride layers, and silicon nitride layers. For example, the spacer structure SS may include a first spacer ST1 and a second spacer ST2, the second spacer ST2 comprising a material different from that of the first spacer ST1. The first spacer ST1 may fill the recessed area of ​​the variable resistance pattern CR. The second spacer ST2 may cover the sidewall of the first spacer ST1. It will be understood that when an element is referred to as being "connected" or "attached" to or "on" another element, it may be directly connected or attached to said other element or directly on said other element, or an intermediary element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, or referred to as "in contact" with another element, or "in contact with" another element, there is no intermediary element.

[0041] The first unit structure MC1 can be arranged in two dimensions to be spaced apart from each other in the first direction D1 and the second direction D2. The first trench TR1 can separate the first unit structures MC1 from each other, and the first trench TR1 can have a lattice or grid shape extending in the first direction D1 and the second direction D2.

[0042] The first unit structure MC1 may have a first buried structure GS1 therein, filling the first trench TR1. When viewed in a plane, the first buried structure GS1 may have a lattice or mesh shape including portions extending in a first direction D1 and portions extending in a second direction D2. The first buried structure GS1 may include a first pad pattern CP1 and a first fill pattern GP1. For example, the first pad pattern CP1 may conformally cover the sidewalls of the first unit structure MC1. The first pad pattern CP1 may have a bottom surface in contact with the top surface of the lower buried structure GS0 and the top surface of the first conductive line CL1. The first pad pattern CP1 may be partially connected to the top surface of the lower buried structure GS0, and this portion of the first pad pattern CP1 may extend downward below the top surface of the first conductive line CL1. For example, the first pad pattern CP1 may have a lower portion inserted into the upper part of the lower buried structure GS0. The first fill pattern GP1 may be provided on the first pad pattern CP1. The first fill pattern GP1 may be spaced apart from the first unit structure MC1 across the first pad pattern CP1. In one exemplary embodiment, the first pad pattern CP1 may be inserted between the first fill pattern GP1 and the first unit structure MC1.

[0043] The first pad pattern CP1 may include at least one selected from SiN, SiO2, SiON, SiBN, SiCN, SiOCN, Al2O3, AlN, and AlON. The first filling pattern GP1 may include at least one selected from SiN, SiON, SiC, SiCN, SiOC, SiOCN, SiO2, and Al2O3.

[0044] Each second conductive line CL2 may include a barrier pattern 121 and a metal pattern 122. Each third conductive line CL3 may include a barrier pattern 123 and a metal pattern 124. Barrier patterns 121 and 123 may include metal nitrides such as TiN, WN, or TaN. Metal patterns 122 and 124 may include metals such as tungsten, titanium, or tantalum. Barrier patterns 121 and 123 may have a thickness of about 1 / 20 to about 1 / 7 times the thickness of metal patterns 122 and 124. The first conductive line CL1 does not include a barrier pattern, but the inventive concept is not limited thereto. An upper mask pattern 134 may be retained on the third conductive line CL3, or alternatively, the upper mask pattern 134 may not be retained on the third conductive line CL3. For example, when memory cells are stacked and provided on the third conductive line CL3, as referenced... Figure 12 The structure of the discussion is the same, but the upper mask pattern 134 is not provided.

[0045] Reference Figures 4 to 6B The following details the second buried structure GS2. The second buried structure GS2 may fill a second trench TR2 between second conductive lines CL2. The second trench TR2 may extend in a second direction D2 and may be spaced apart from each other in a first direction D1. Each second buried structure GS2 may have a strip shape or a linear shape (e.g., a straight line shape) extending in the second direction D2. For example, the second buried structures GS2 may be separated from each other by the second conductive lines CL2. In an exemplary embodiment, each second conductive line CL2 may be disposed between two adjacent corresponding second buried structures GS2. Each second buried structure GS2 may include a second pad pattern CP2, a second fill pattern GP2, and a first cover pattern SP1. The second pad pattern CP2 may cover the sidewalls of a pair of adjacent second conductive lines CL2 and may also cover the top surface of the first buried structure GS1 exposed between the pair of second conductive lines CL2. For example, the second pad pattern CP2 may have a bottom surface in contact with the first pad pattern CP1 and the first fill pattern GP1. The second pad pattern CP2 may contact the top surface of the first unit structure MC1, such as the top surface of the third electrode EL3, but the inventive concept is not limited thereto. The second pad pattern CP2 may extend in the second direction D2.

[0046] The second filling pattern GP2 may have a lower portion that fills the lower part of the second groove TR2, and may also have an upper portion that contacts the bottom surface of the first cover pattern SP1. When viewed in cross-section, the second filling pattern GP2 may be surrounded by the second padding pattern CP2 and the first cover pattern SP1. The second filling pattern GP2 may extend in the second direction D2.

[0047] The first cover pattern SP1 may extend between the second conductive lines CL2 in a second direction D2 and may be spaced apart from each other in the first direction D1. The first cover pattern SP1 may have a raised shape toward the first unit structure MC1 or the substrate 100. In an exemplary embodiment, the bottom surface of the cover pattern SP1 may contact the second fill pattern GP2 (e.g., the top surface of the second fill pattern GP2), and the bottom surface of the cover pattern SP1 may protrude toward the second fill pattern GP2. For example, the first cover pattern SP1 may have a bottom surface and / or a top surface, each of which has a cross-section protruding toward the substrate 100. For example, the bottom surface of the first cover pattern SP1 may have a shape that is consistent with the shape of the second fill pattern MC1 or the substrate 100. Figure 5 and Figure 6A The drawn shape is the same as, or alternatively, may have the following characteristics: Figure 6BThe shape shown has a relatively small curvature.

[0048] The bottom surface of the first overlay pattern SP1 may contact the top surface of the second filler pattern GP2 and the top surface of the second padding pattern CP2, or alternatively may not contact the top surface of the second padding pattern CP2. The first overlay pattern SP1 may have a thickness t1 greater than the thickness t2 of the second padding pattern CP2. For example, the thickness t1 of the first overlay pattern SP1 may be greater than approximately... to approximately Within the range.

[0049] The first overlay pattern SP1 may have a lowermost portion at a level equal to or greater than approximately 2 / 3 times the height H1 of the second conductive line CL2. In an exemplary embodiment, the first overlay pattern SP1 may have a lowermost bottom surface located at a level equal to or greater than approximately 2 / 3 times the height H1 of the second conductive line CL2. For example, the distance H2 from the top surface of the second conductive line CL2 to the lowermost portion (e.g., the lowermost bottom surface) of the first overlay pattern SP1 may correspond to the distance from approximately... to approximately The value of H2 is not limited thereto. In one exemplary embodiment, the distance H2 can be approximately... to approximately Within the range between.

[0050] The second pad pattern CP2, the second fill pattern GP2, and the first overlay pattern SP1 may comprise materials different from each other. The second pad pattern CP2 may comprise at least one material selected from SiN, SiO2, SiON, SiBN, SiCN, SiOCN, Al2O3, AlN, and AlON. The second fill pattern GP2 may comprise at least one material selected from SiN, SiON, SiC, SiCN, SiOC, SiOCN, SiO2, and Al2O3. The first overlay pattern SP1 may comprise at least one material selected from SiN, SiO2, SiON, SiBN, SiCN, SiOCN, Al2O3, AlN, and AlON.

[0051] For example, the second filling pattern GP2 may have a higher carbon concentration than the first overlay pattern SP1. The first overlay pattern SP1 may have a higher dielectric constant than the second filling pattern GP2. For example, the second filling pattern GP2 may include silicon carbide (SiOC). For example, the first overlay pattern SP1 may be a monolayer comprising one of SiO2, SiN, and SiON. Alternatively, the first overlay pattern SP1 may have a multilayer structure in which multiple monolayers are stacked one on top of another (i.e., a multilayer pattern). Each layer of the multilayer pattern may include one of SiO2, SiN, and SiON. For example, as Figure 6AAs shown, the first overlay pattern SP1 may include a first layer L1 and a second layer L2, which are made of different materials. For example, the first layer L1 may include one of SiO2, SiN, and SiON, and the second layer L2 may include another of SiO2, SiN, and SiON. The second layer L2 may have a thickness greater than that of the first layer L1. For example, the second layer L2 may have a thickness equal to or greater than twice the thickness of the first layer L1.

[0052] A third buried structure GS3 can be provided to fill the area between the second unit structures MC2. The third buried structure GS3 may have a lattice or grid shape including portions extending in a first direction D1 and portions extending in a second direction D2. The third buried structure GS3 may include a third pad pattern CP3 and a third fill pattern GP3. For example, the third pad pattern CP3 may conformally cover the sidewalls of the second unit structure MC2. The third pad pattern CP3 may include at least one selected from SiN, SiO2, SiON, SiBN, SiCN, SiOCN, Al2O3, AlN, and AlON. The third fill pattern GP3 may include at least one selected from SiN, SiON, SiC, SiCN, SiOC, SiOCN, SiO2, and Al2O3.

[0053] The third pad pattern CP3 may have a bottom surface that contacts the top surface of the second buried structure GS2 and the top surface of the second conductive line CL2. The third pad pattern CP3 may be partially connected to the top surface of the second buried structure GS2, and this portion may extend downward below the top surface of the second conductive line CL2. For example, the third pad pattern CP3 may have a lower portion inserted between the second conductive lines CL2. The thickness t1 of the first cover pattern SP1 in the third direction D3 may be less than the width t3 of the second buried structure GS2 in the first direction D1 at the level of the bottom surface of the first cover pattern SP1. For example, the second layer L2 may have a thickness equal to or greater than four times the thickness of the first layer L1.

[0054] A fourth buried structure GS4 can be provided to fill the area between the third conductive lines CL3. Each fourth buried structure GS4 may have a strip shape or a line shape (e.g., a straight line shape) extending in the first direction D1. For example, the fourth buried structures GS4 may be separated from each other by the third conductive lines CL3. In an exemplary embodiment, each third conductive line CL3 may be disposed between two corresponding fourth buried structures that are adjacent to each other. Each fourth buried structure GS4 may include a fourth pad pattern CP4 and a fourth fill pattern GP4. Except as expressly and differently stated, the description of the second pad pattern CP2 and the second fill pattern GP2 may be applied equally to the fourth pad pattern CP4 and the fourth fill pattern GP4, respectively. Unlike the second buried structure GS2, the fourth buried structure GS4 may not include a cover pattern. Alternatively, as will be referred to Figure 12 The structure discussed, the fourth burial structure GS4, may include a covering pattern.

[0055] Each of the first burial structure GS1 to the fourth burial structure GS4 does not have non-solid regions such as air gaps, seams, and voids, or alternatively may have non-solid regions therein. The term "air" as discussed herein may refer to the atmosphere or other gases that may be present during the manufacturing process.

[0056] Figure 7 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'. Figure 8 and Figure 9 It shows Figure 7 A magnified view of part Q'. For the sake of brevity, descriptions of repeated parts will be omitted.

[0057] Reference Figures 7 to 9 The thickness t1 of the first covering pattern SP1 in the third direction D3 can be greater than the width t3 of the second burial structure GS2 in the first direction D1 at the horizontal position of the bottom surface of the first covering pattern SP1. For example, the thickness t1 of the first covering pattern SP1 can be greater than the width t3 of the second burial structure GS2 in the first direction D1 at the horizontal position of the bottom surface of the first covering pattern SP1. to approximately Within the range. The first covering pattern SP1 may have a lowermost part (e.g., the lowest bottom surface) at a level equal to or greater than approximately 2 / 3 times the height H1 of the second conductive line CL2. For example, the distance H2' from the top surface of the second conductive line CL2 to the lowermost part (e.g., the lowest bottom surface) of the first covering pattern SP1 may correspond to the distance from approximately to approximately The value of H2 is not limited thereto. In one exemplary embodiment, the distance H2' can be from approximately to approximately Within the range between.

[0058] The first overlay pattern SP1 can be a single layer including one of SiO2, SiN, and SiON, or as... Figure 9 As shown, the first overlay pattern SP1 may include a first layer L1 and a second layer L2, which are made of different materials. For example, the first layer L1 may include one of SiO2, SiN, and SiON, and the second layer L2 may include another of SiO2, SiN, and SiON. The second layer L2 may have a greater thickness than the first layer L1.

[0059] Figure 10 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0060] In this embodiment, each lower burial structure GS0 may include a lower liner pattern CP0, a lower filler pattern GP0, and a lower cover pattern SP0. Unless otherwise stated, the description of the second burial structure GS2 can be applied to the lower burial structure GS0. For example, the lower liner pattern CP0, the lower filler pattern GP0, and the lower cover pattern SP0 may each comprise the same material as the second liner pattern CP2, the second filler pattern GP2, and the first cover pattern SP1. For example, the lower cover pattern SP0 may be a single layer comprising one of SiO2, SiN, and SiON. As another example, the lower cover pattern SP0 may have a multilayer structure (i.e., a multilayer pattern) in which multiple single layers are stacked one on top of another. Each layer of the multilayer pattern may comprise one of SiO2, SiN, and SiON.

[0061] Figure 11 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3The cross-sectional views are taken along lines A-A' and B-B'. In this embodiment, the peripheral circuit region PS can be provided below the cell array region comprising a stack of multiple memory cells. For example, the peripheral circuit region PS can be provided between the first memory cell stack MCA1 and the substrate 100. The peripheral circuit region PS can include peripheral logic circuitry. For example, the peripheral circuit region PS can include row decoders and column decoders, page buffers, and control circuitry. The peripheral circuit region PS can include N-type metal-oxide-semiconductor (NMOS) transistors and P-type metal-oxide-semiconductor (PMOS) transistors, low-voltage transistors and high-voltage transistors, and resistors integrated on the substrate 100. For example, a peripheral transistor PT can be disposed on the peripheral circuit region PS. The peripheral transistor PT can include its peripheral gate electrode PG and an active region defined by the device isolation layer 11 on the substrate 100. The peripheral transistor PT can be covered by the lower interlayer dielectric layer 50. The peripheral circuit line 33 can be connected to the peripheral transistor PT via a peripheral contact plug 34.

[0062] Figure 12 The diagram illustrates some exemplary embodiments of a variable resistance storage device according to the concept of the present invention. Figure 3 The cross-sectional views taken by lines A-A' and B-B'. (Refer to...) Figure 2 , Figure 3 and Figure 12 A variable resistance storage device according to some exemplary embodiments of the present invention may include a first storage cell stack MCA1, a second storage cell stack MCA2, a third storage cell stack MCA3, a fourth storage cell stack MCA4, and a first conductive line CL1, a second conductive line CL2, a third conductive line CL3, a fourth conductive line CL4, and a fifth conductive line CL5. The foregoing description is equally applicable to the first storage cell stack MCA1, the second storage cell stack MCA2, and the first conductive line CL1, the second conductive line CL2, and the third conductive line CL3.

[0063] A fourth conductive line CL4 and a fifth conductive line CL5 may be provided sequentially on a third conductive line CL3. A third memory cell stack MCA3 may be provided between the third conductive line CL3 and the fourth conductive line CL4, and a fourth memory cell stack MCA4 may be provided between the fourth conductive line CL4 and the fifth conductive line CL5. The third memory cell stack MCA3 and the fourth memory cell stack MCA4 may have the same configuration as the second memory cell stack MCA2. A fifth buried structure GS5 may be provided to fill the area between the cell structures of the third memory cell stack MCA3, and a seventh buried structure GS7 may be provided to fill the area between the cell structures of the fourth memory cell stack MCA4. The fifth buried structure GS5 and the seventh buried structure GS7 may be substantially the same as the third buried structure GS3. For example, the fifth buried structure GS5 may include a fifth pad pattern CP5 and a fifth fill pattern GP5. The seventh buried structure GS7 may include a seventh pad pattern CP7 and a seventh fill pattern GP7.

[0064] like Figure 12 As shown in part P, in addition to the fourth liner pattern CP4 and the fourth fill pattern GP4, each fourth burial structure GS4 may also include a second overlay pattern SP2. For example, Figure 12 The structure of part of P can be related to Figure 5 , Figure 6A and Figure 6B The structure of the Q portion shown is basically the same. A sixth buried structure GS6 can be provided to fill the area between the fourth conductive lines CL4. For example... Figure 12 As shown in part R, each sixth burial structure GS6 may include a sixth liner pattern CP6, a sixth fill pattern GP6, and a third overlay pattern SP3. For example, Figure 12 The structure of part of R can be related to Figure 5 , Figure 6A and Figure 6B The structures of the portions Q shown are basically the same. The description of the first covering pattern SP1 can be applied in the same way to the second covering pattern SP2 and the third covering pattern SP3.

[0065] An eighth buried structure GS8 can be provided to fill the area between the fifth conductive lines CL5. Each eighth buried structure GS8 may include an eighth pad pattern CP8 and an eighth fill pattern GP8.

[0066] Figures 13 to 22 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0067] Reference Figure 3 and Figure 13An interlayer dielectric layer 110 and first conductive lines CL1 can be formed on a substrate 100. Forming the first conductive lines CL1 may include depositing a first conductive layer on the substrate 100 and etching the first conductive layer using a mask pattern as an etching mask. The first conductive lines CL1 may each have a lower width greater than their upper width and also have sloping sidewalls. In an exemplary embodiment, each first conductive line CL1 may have a first portion having an upper width and a second portion having a lower width greater than the upper width. The first portion of each first conductive line CL1 may be closer to a second conductive line CL2 than the second portion of each first conductive line CL1. A lower buried structure GS0 may be formed to fill the area between the first conductive lines CL1. The lower buried structure GS0 may be formed of at least one selected from silicon oxide, silicon nitride, and silicon nitride. A planarization process may then be performed to expose the top surface of the first conductive lines CL1. In an exemplary embodiment, the planarization process may include a chemical mechanical polishing (CMP) process or an etch-back process.

[0068] A second conductive layer 22, a switching layer 41, a third conductive layer 23, a first metal layer 31, a variable resistance layer 42, a second metal layer 32, and a fourth conductive layer 24 may be sequentially formed on the first conductive line CL1. For example, the formation of the above layers may include performing at least one of chemical vapor deposition, sputtering, and atomic layer deposition.

[0069] Reference Figure 3 and Figure 14 A first mask pattern 52 may be formed on the fourth conductive layer 24. The first mask pattern 52 may include a silicon nitride layer, a silicon oxide layer, and / or a silicon oxide nitride layer. The first mask pattern 52 may be used as an etching mask to perform an etching process in which the fourth conductive layer 24, the second metal layer 32, the variable resistance layer 42, and the first metal layer 31 are sequentially patterned to form a first trench TR1. A first metal pattern MB1, a variable resistance pattern CR, a second metal pattern MB2, and a third electrode EL3 may be sequentially formed on the third conductive layer 23. For example, the first mask pattern 52 may be spaced apart from each other in a first direction D1 and a second direction D2. The etching process may include ion beam etching and / or reactive ion etching.

[0070] Recessed regions can be formed on the sidewalls of the variable resistance pattern CR. For example, the recessed regions can be formed by performing a wet cleaning process using a cleaning solution with etch selectivity relative to the variable resistance pattern CR. Alternatively, the formation of the recessed regions can be omitted. Spacer structures SS can be formed to cover the variable resistance pattern CR. The spacer structure SS can be formed by forming a dielectric layer covering the sidewalls of each of the first metal pattern MB1, the second metal pattern MB2, the variable resistance pattern CR, and the third electrode EL3, followed by an anisotropic etching process. For example, the spacer structure SS can include a first spacer ST1 and a second spacer ST2, the second spacer ST2 comprising a material different from that of the first spacer ST1. The spacer structure SS can be formed by atomic layer deposition and / or chemical vapor deposition.

[0071] Reference Figure 3 and Figure 15 An etching process can be performed in which the third conductive layer 23, the switching layer 41, and the second conductive layer 22 are sequentially etched to form the second electrode EL2, the switching pattern SM, and the first electrode EL1. The first memory cell stack MCA1 can be formed to include the first cell structure MC1. The etching process can include ion beam etching and / or reactive ion etching. During the etching process, the first trench TR1 can further extend toward the substrate 100. For example, a first recessed region R1 can be formed on the upper part of the lower buried structure GS0.

[0072] Reference Figure 3 and Figure 16 A first pad pattern CP1 and a first fill pattern GP1 can be formed to sequentially cover the interior of the first trench TR1. The first pad pattern CP1 and the first fill pattern GP1 can constitute a first buried structure GS1. The first pad pattern CP1 can extend into the first recessed region R1. Subsequently, a planarization process can be performed to expose the top surface of the third electrode EL3. The first pad pattern CP1 can be formed by chemical vapor deposition, physical vapor deposition, and / or atomic layer deposition. After depositing the first pad pattern CP1, a post-processing process can be performed to improve film quality. For example, the post-processing process can include at least one selected from annealing, UV treatment, and plasma treatment. Inert gases such as N, He, and Ar can be used in the post-processing.

[0073] The first filling pattern GP1 can be formed using a thin-layer formation method with excellent gap-filling properties, such as flowable chemical vapor deposition (FCVD) or spin-coated glass (SOG) coating. For example, the first filling pattern GP1 can be formed using flowable chemical vapor deposition with SiOC. The first trench TR1 can be filled with a dielectric layer without seams or voids. As another example, the first filling pattern GP1 can be formed using atomic layer deposition, chemical vapor deposition, and / or physical vapor deposition.

[0074] Reference Figure 3 and Figure 17 A second conductive line CL2 can be formed on the first memory cell stack MCA1. The formation of the second conductive line CL2 may include sequentially forming a barrier layer and a metal layer, and then using a mask pattern MS as an etching mask to form a second trench TR2. Each second conductive line CL2 may be formed including a barrier pattern 121 and a metal pattern 122. The mask pattern MS may include a second mask pattern 131 and a third mask pattern 132. For example, the second mask pattern 131 may include silicon nitride, and the third mask pattern 132 may include silicon oxide.

[0075] Multiple dielectric layers can be formed to sequentially cover the interior of the second trench TR2, and a planarization process can be performed to form a second pad pattern CP2 and a second fill pattern GP2. The second pad pattern CP2 and the second fill pattern GP2 can be formed using the same materials and methods as those used for forming the first pad pattern CP1 and the first fill pattern GP1. This also applies to other pad patterns and other fill patterns. For example, the second fill pattern GP2 can be formed by flowable chemical vapor deposition using SiOC. The planarization process can expose a third mask pattern 132, and each of the second pad pattern CP2 and the second fill pattern GP2 can be divided into multiple blocks within each second trench TR2.

[0076] Reference Figure 3 and Figure 18 A planarization process can be performed to remove the third mask pattern 132 and expose the top surface of the second mask pattern 131.

[0077] Reference Figure 3 and Figure 19 A planarization process can be performed to remove the second mask pattern 131. Figures 17 to 19 The planarization processes can be distinguished from each other, or alternatively, Figures 17 to 19 At least two of the planarization processes can be indistinguishable from each other. As Figure 19As a result of the planarization process discussed herein, the upper portion of each of the second pad pattern CP2 and the second fill pattern GP2 can be removed to form a second recessed region R2. The second recessed region R2 can be formed due to dishing caused by differences in the physical properties between the second conductive line CL2, the second pad pattern CP2, and the second fill pattern GP2. The planarization process may include an in-situ cleaning process using HF.

[0078] Reference Figure 3 and Figure 20 A preliminary first overlay pattern PSP1 can be formed to fill the second recessed region R2. For example, the preliminary first overlay pattern PSP1 can be formed by atomic layer deposition. Each preliminary first overlay pattern PSP1 can be formed as a single layer comprising one of SiO2, SiN, and SiON, or a multilayer structure wherein multiple single layers are stacked one on top of another (i.e., a multilayer pattern). Each layer of the multilayer pattern can include one of SiO2, SiN, and SiON.

[0079] A planarization process can be performed on the preliminary first overlay pattern PSP1 to expose the second conductive line CL2. The preliminary first overlay pattern PSP1 is shown with its top surface at a height (or level) that is the same as or lower than the height (or level) of the top surface of the second conductive line CL2.

[0080] Reference Figure 3 and Figure 21 A second memory cell stack MCA2, including a second cell structure MC2, can be formed on the second conductive line CL2. The second cell structure MC2 can be connected to a reference... Figures 13 to 15 The method discussed for forming the first unit structure MC1 is essentially the same as that used in the formation. A third trench TR3 can be formed between the second unit structures MC2. During the formation of the third trench TR3, the upper part of the preliminary first cover pattern PSP1 can be etched to form the first cover pattern SP1. Each second buried structure GS2 can be formed to include a second pad pattern CP2, a second fill pattern GP2, and a first cover pattern SP1.

[0081] When an etchant is used in an etching process to form the second unit structure MC2, the second filler pattern GP2 can be etched at a higher rate than the second pad pattern CP2. When the first overlay pattern SP1 is absent, the second filler pattern GP2 may undergo over-removal or etch distribution, causing instability in the overlay structure used for the second unit structure MC2. This can lead to tilting of the second unit structure MC2 and cell bridging attribution to this tilt. According to some exemplary embodiments of the present invention, the first overlay pattern SP1 can be formed with greater etching resistance to its associated process than the second filler pattern GP2, thereby resolving the tilting of the second unit structure MC2.

[0082] Reference Figure 3 and Figure 22 A third pad pattern CP3 and a third fill pattern GP3 can be formed to sequentially cover the interior of the third trench TR3. The third pad pattern CP3 and the third fill pattern GP3 can constitute a third buried structure GS3. The third pad pattern CP3 can extend between the second conductive lines CL2 and can cover the top surface of the first cover pattern SP1. The third buried structure GS3 can be formed by referring to... Figure 16 The method discussed for forming the first buried structure GS1 is essentially the same as that used in the formation. The third filling pattern GP3 can be formed using flowable chemical vapor deposition with SiOC.

[0083] Return to reference Figure 3 and Figure 4 A third conductive line CL3 can be formed on the second memory cell stack MCA2. The formation of the third conductive line CL3 may include sequentially forming a barrier layer and a metal layer, and using a mask pattern as an etching mask to form trenches. Each third conductive line CL3 may be formed including a barrier pattern 123 and a metal pattern 124. Subsequently, multiple dielectric layers may be formed, and a planarization process may be performed to form a fourth buried structure GS4. Each fourth buried structure GS4 includes a fourth pad pattern CP4 and a fourth fill pattern GP4. The fourth fill pattern GP4 can be formed by flowable chemical vapor deposition using SiOC. After the planarization process, the upper mask pattern 134 may be retained, or alternatively, the upper mask pattern 134 may not be retained.

[0084] Figure 23 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0085] Reference Figure 19The resulting structure can undergo an additional etching process performed on the second pad pattern CP2 and the second fill pattern GP2. This additional etching process can include dry etching and / or wet etching. The second recessed region R2 can extend toward the substrate 100, thus forming an extended second recessed region R2'. Afterwards, [further steps can be performed]. Figures 20 to 22 The process. As a result, a reference can be established. Figures 7 to 9 The structure of the discussion.

[0086] Figures 24 to 26 The diagram illustrates a method for manufacturing a variable resistance memory device, showing some exemplary embodiments of the concept according to the present invention. Figure 3 The cross-sectional view taken by lines A-A' and B-B'.

[0087] Reference Figure 3 and Figure 24 An interlayer dielectric layer 110 and a first conductive line CL1 can be formed on the substrate 100. Lower trenches TR0 can separate the first conductive lines CL1 from each other. A lower pad pattern CP0 and an underfill pattern GP0 can be formed in each lower trench TR0. A planarization process can be performed to form the lower pad pattern CP0 and the underfill pattern GP0. The underfill pattern GP0 can be formed by flowable chemical vapor deposition using SiOC. As a result of the planarization process, a recessed region R0 can be formed on the upper part of the underfill pattern GP0.

[0088] Reference Figure 3 and Figure 25 A preliminary undercoat pattern PSP0 can be formed to fill the recessed region R0. For example, the preliminary undercoat pattern PSP0 can be formed by atomic layer deposition. The preliminary undercoat pattern PSP0 can be formed from a single layer including one of SiO2, SiN, and SiON, or from a multilayer structure including multiple single layers stacked on top of each other (i.e., a multilayer pattern). Each layer of the multilayer pattern can include one of SiO2, SiN, and SiON.

[0089] Reference Figure 3 and Figure 26 , can execute reference Figures 13 to 15 The discussed process is used to form the first memory cell stack MCA1. The first trench TR1 between the first cell structures MC1 can further extend toward the substrate 100. For example, the upper portion of the initial undercover pattern PSP0 can be etched to form a first recessed region R1 and an undercover pattern SP0. Each undercover structure GS0 can be formed to include an underpainting pattern CP0, an underfill pattern GP0, and an undercover pattern SP0. Afterwards, reference... Figures 16 to 22 The discussed processes are intended to form a reference. Figure 10 The variable resistance storage device under discussion.

[0090] According to some exemplary embodiments of the present invention, tilting or bridging that may occur during the patterning of the unit structure can be prevented. Ordinal numbers such as "first," "second," "third," etc., may be used only as labels for certain elements, steps, etc., to distinguish them from each other. Terms not used in the specification, such as "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0091] Although some exemplary embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. Therefore, it will be understood that the above embodiments are illustrative in all respects and not restrictive.

[0092] This application claims priority to Korean Patent Application No. 10-2020-0075755, filed on June 22, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A variable resistance memory device, comprising: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction and arranged on the plurality of first conductive lines; a plurality of first cell structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines, each of the first cell structures including a switching pattern and a variable resistance pattern; a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction; and a plurality of second buried structures filling a plurality of second trenches between the plurality of first cell structures, wherein each of the plurality of first buried structures includes: a first spacer pattern covering sidewalls of a corresponding first trench of the plurality of first trenches; a first fill pattern disposed on the first spacer pattern and in the corresponding first trench; and a first cap pattern configured to seal the corresponding first trench in which the first spacer pattern and the first fill pattern are provided, and wherein the plurality of second buried structures extends in the plurality of second trenches and connects to the plurality of first cap patterns of the plurality of first buried structures, wherein the first cap pattern is disposed between the first conductive lines and connected to the second buried structure between the first conductive lines.

2. The device of claim 1, wherein the first cap pattern includes a material having an etch resistance greater than an etch resistance of the first fill pattern, and wherein the etch resistance of the first cap pattern and the etch resistance of the first fill pattern are determined with respect to an etching process forming the plurality of second trenches.

3. The device of claim 2, wherein the first fill pattern includes silicon carbon oxide, and wherein the first cap pattern is formed of a single layer having one of silicon oxide, silicon nitride, and silicon oxynitride (SiON).

4. The device of claim 2, wherein the first fill pattern includes silicon carbon oxide, and wherein the first cap pattern is formed as a multi-layer pattern including a first layer of silicon oxide and a second layer of silicon nitride.

5. The device of claim 1, wherein a lowermost bottom surface of the first cap pattern is located at a level equal to or greater than 2 / 3 times a height of a first conductive line of the plurality of first conductive lines, and wherein the first conductive line is adjacent to the corresponding first trench.

6. The device of claim 1, wherein a distance from a top surface of a first conductive line of the plurality of first conductive lines to a lowermost bottom surface of the first cap pattern is in a range from 50A to 350A.

7. The device of claim 1, wherein each of the plurality of second buried structures includes a second spacer pattern and a second fill pattern, and when viewed in a plane, the plurality of second fill patterns of the plurality of second buried structures are arranged in a lattice shape. wherein 8. The device of claim 1, wherein a bottom surface of the first cap pattern has a convex shape toward the first fill pattern.

9. The device of claim 1, ​ wherein a bottom surface of the first cover pattern is in contact with a top surface of the first fill pattern and a top surface of the first liner pattern.

10. The device of claim 1, wherein a carbon concentration of the first fill pattern is higher than a carbon concentration of the first cover pattern.

11. The device of claim 1, wherein each of the plurality of first conductive lines has a first portion having an upper width and a second portion having a lower width greater than the upper width, and wherein the first portion of each of the plurality of first conductive lines is closer to the plurality of second conductive lines than the second portion of each of the plurality of first conductive lines.

12. The device of claim 1, further comprising: a substrate; and a peripheral circuit region between the substrate and the plurality of first conductive lines.

13. The device of claim 1, further comprising: a plurality of third conductive lines extending in the first direction and disposed on the plurality of second conductive lines; a plurality of second unit structures at intersections between the plurality of second conductive lines and the plurality of third conductive lines; a third buried structure filling a plurality of third trenches between the plurality of second unit structures; and a plurality of fourth buried structures filling a plurality of fourth trenches between the plurality of third conductive lines and extending in the first direction, wherein each of the fourth buried structures comprises: a fourth liner pattern covering sidewalls of a corresponding fourth trench of the plurality of fourth trenches; a fourth fill pattern disposed on the fourth liner pattern and in the corresponding fourth trench; and a fourth cover pattern configured to seal the corresponding fourth trench in which the fourth fill pattern and the fourth liner pattern are provided.

14. A variable resistance memory device, comprising: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction and disposed on the plurality of first conductive lines; a plurality of first unit structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first unit structures comprising a switching pattern and a variable resistance pattern; and a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction, wherein each of the plurality of first buried structures comprises: a first liner pattern covering sidewalls of a corresponding first trench of the plurality of first trenches; a first fill pattern on the first liner pattern and in the corresponding first trench; and a cover pattern disposed in the corresponding first trench, wherein the cover pattern covers a top surface of the first liner pattern and a top surface of the first fill pattern, wherein a bottom surface of the cover pattern has a convex shape toward the first fill pattern, wherein a lowermost bottom surface of the cover pattern is located at a level equal to or greater than 2 / 3 times a height of a first conductive line of the plurality of first conductive lines, and wherein the first conductive line is adjacent to the corresponding first trench, wherein the cover pattern is disposed between the first conductive line.

15. The device of claim 14, wherein the lowest bottom surface of the capping pattern is lower than a top surface of the first conductive lines.

16. The device of claim 14, wherein the plurality of first buried structures comprises two first buried structures adjacent to each other and a second conductive line among the plurality of first conductive lines between the two first buried structures, and wherein the second conductive line is disposed between the capping pattern of one of the two first buried structures and the capping pattern of the other.

17. The device of claim 14, wherein the first fill pattern comprises silicon carbon oxide, and wherein the capping pattern is formed by a single layer having one of silicon oxide and silicon nitride.

18. The device of claim 14, wherein the first fill pattern comprises silicon carbon oxide, and wherein the capping pattern is formed by a multi-layer pattern comprising a first layer of silicon oxide and a second layer of silicon nitride.

19. A variable resistance memory device, comprising: a substrate; a plurality of first conductive lines on the substrate, the plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction and disposed on the plurality of first conductive lines; a plurality of first cell structures at intersections between the plurality of first conductive lines and the plurality of second conductive lines; a plurality of first buried structures filling a plurality of first trenches between the plurality of first conductive lines and extending in the first direction; and a plurality of second buried structures filling a plurality of second trenches between the plurality of first cell structures, wherein each of the plurality of first buried structures comprises: a first spacer pattern capping sidewalls of a corresponding first trench among the plurality of first trenches; a first fill pattern on the first spacer pattern and in the corresponding first trench; and a first capping pattern on the first fill pattern and in the corresponding first trench, wherein each of the plurality of second buried structures comprises a second spacer pattern and a second fill pattern, wherein each of the plurality of first cell structures comprises a first electrode, a switching pattern, a second electrode, a variable resistance pattern, and a third electrode provided in sequence, and wherein the plurality of second buried structures extends in the plurality of second trenches and connects to the plurality of first capping patterns of the plurality of first buried structures, wherein the first capping pattern is disposed between and connected to the second buried structures between the first conductive lines.

20. The device of claim 19, wherein a distance from a top surface of a first conductive line among the plurality of first conductive lines to a lowest bottom surface of the first capping pattern is in a range from 50 A to 350 A. ​

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