Method to quickly relock DLL circuit

Abstract

The present invention provides a method for rapidly relocking a DLL circuit. The method includes: detecting overflow or underflow in real time, and setting a control signal based on the detection result to control internal clock delay. This method significantly reduces instruction and data loss, and promptly restores the normal phase lock state without resetting the DLL circuit. Furthermore, in the event of overflow or underflow, the method provides a clock with minimal error for output data and rapidly relocks the DLL, resulting in high data transmission accuracy and stability. The method effectively mitigates the adverse effects of temperature changes on clock processing, improves DRAM reliability, and further promotes the in-depth application of integrated circuit technology.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for quickly relocking a DLL circuit. Background Art

[0002] Dynamic random access memory (DRAM) and the external control chip (CPU) use clocks to accurately transmit instructions and data. During a read operation, the DRAM needs to provide an output clock (dqs). dqs is primarily used to accurately distinguish each transmission cycle within a clock cycle (tCK) and facilitate accurate data reception at the receiver. If the phase difference between the output clock (dqs) and the external clock (clk) is significantly, the CPU may capture incorrect instructions and data. Currently, adjusting the DRAM output clock (dqs) to align it with the external clock (clk) is primarily achieved through a delay-locked loop (DLL) circuit. The DLL circuit provides a delay to maintain phase alignment between the output clock (dqs) and the external clock (clk).

[0003] Unstable voltage and temperature fluctuations during DRAM chip operation often cause the DLL circuit to malfunction, a condition generally referred to as DLL lock failure. Two prominent lock failure scenarios are generally referred to as overflow and underflow. Overflow typically occurs when the DLL circuit continuously issues instructions to increase delay, but the DLL circuit has already provided its maximum delay and cannot increase it further. Consequently, the output clock (dqs) remains unlocked and no adjustments can be made. Underflow occurs when the DLL circuit continuously issues instructions to decrease delay, but the DLL circuit has already provided its minimum adjustable delay and cannot reduce it further, resulting in phase lock failure and an inability to adjust out of the current overflow or underflow. In either of these situations, the memory chip cannot provide data and instructions at the correct time, leading to data transmission failure. In particular, with the development of integrated circuit technology and the deepening of application needs, when devices integrated with DRAM are used in extreme environments, sudden temperature changes often occur, and overflow or underflow is more likely to occur, making it impossible for the DRAM output clock dqs to be aligned with the external clock clk. At this time, the existing DLL circuit will not correct the phase of the output clock dqs, and the memory chip will ultimately be unable to accurately transmit data.

[0004] A known solution is to reset the DLL circuit. This takes a relatively long time. For example, for DDR4-2666 memory, the required DLL circuit locking time is 854tCK. During this time, the DRAM chip cannot receive any instructions, and subsequent instructions will be lost. Clearly, resetting the DLL circuit does not quickly relock the DLL circuit for an active DRAM chip, making it an ineffective solution for overflow or underflow. The adverse effects of overflow or underflow caused by factors such as temperature fluctuations limit the application of DRAM memory and integrated circuit devices using it in complex environments.

[0005] Therefore, there is a great need to study a method for quickly relocking the DLL circuit, which can restore the DLL circuit to its normal locked state in a shorter time without resetting the DLL circuit, and solve the problem of large-scale loss of instructions and data when the DLL circuit underflows or overflows in DRAM memory, so as to further promote the in-depth development and widespread application of semiconductor integrated circuit technology. Summary of the Invention

[0006] The present invention aims to solve all or part of the problems of the above-mentioned prior art and provides a method for quickly relocking a DLL circuit so that the DLL circuit can jump out of the overflow or underflow state in time, relock in a short time, and realize the correct transmission of data and instructions.

[0007] In order to facilitate understanding of the content of the present invention, the working principle of the DLL circuit and the overflow and underflow phenomena involved in the present invention are described as examples rather than limitations. Figure 1 As shown, the external clock clk is provided by the CPU. The DLL circuit includes a duty cycle adjustment module DCC (Duty Cycle Correction) for adjusting the clock duty cycle, a delay chain module delay_line for providing adjustable delay, and a fixed delay module delay replica for replicating the clock. Figure 1The actual delay of the Logic circuit in the DLL circuit. This is because the Logic circuit follows the DLL circuit, and the impact of this part of the Logic circuit on the clock needs to be added to the DLL circuit as well. Only in this way can the output clock dqs after the Logic circuit be phase-aligned with clk. In the present invention, overflow means that the phase difference output by the phase detection module phase detect indicates that the delay provided by the current DLL circuit needs to be further increased, but at this time the delay chain module delay_line has already provided the maximum delay. Underflow means that the phase difference output by the phase detection module phase detect indicates that the delay needs to be further reduced, but at this time the delay chain module delay_line has already provided the minimum delay. Due to underflow or overflow, the delay required by the delay chain module delay_line has exceeded its adjustable range. At this time, if the control module control only requires the increase or decrease of the delay units participating in the delay chain in the delay chain module delay_line based on the phase difference output by the phase detection module phase detect, the delay chain module delay_line will be stuck at its maximum or minimum delay value, causing the DRAM to be unlocked and need to be relocked.

[0008] The present invention provides a method for rapidly relocking a DLL circuit. The DLL circuit includes a control module and a delay chain module; the delay chain module includes a coarse delay module and a fine delay module connected in series. The method comprises the following steps: Step S1: obtaining, through the control module, a phase difference between a current external clock and a feedback clock of the DLL circuit, and a current delay provided by the coarse delay module; Step S2: determining whether the current delay can continue to change to compensate for the phase difference, and detecting in real time whether overflow or underflow exists; if not, updating the current control signal based on the phase difference by the control module to adjust the current delay and update the feedback clock, and returning to Step S1; if so, randomly generating an updated control signal by the control module to set the current delay so that the DLL circuit avoids overflow or underflow, and returning to Step S1; and repeating Steps S1 to S2 until the external clock and the feedback clock are phase-aligned. When overflow or underflow occurs in the DLL circuit, an updated delay can be set by randomly generating an updated control signal. A feedback clock can still be obtained in response to the control signal, allowing the locking process to be promptly restarted.

[0009] The coarse delay module includes several delay links, each of which includes a plurality of cascaded delay units. The current delay amount is based on the number of delay units traversed by the internal clock of the DLL circuit. The method of detecting whether there is overflow or underflow in real time includes: determining whether the current delay amount needs to be further increased or decreased based on the phase difference; obtaining the number of delay units currently in use through the control module, and determining whether the number of delay units can be further changed to further increase or decrease the current delay amount.

[0010] The method for detecting the overflow is: if the current delay amount needs to be further increased and the currently used delay units have reached the maximum, then it is determined that the overflow exists.

[0011] The method for detecting the existence of the underflow is: if the current delay amount needs to be further reduced and the currently used delay units are already the minimum, then it is determined that the underflow exists.

[0012] The control signal includes a first control signal and a second control signal; the internal clock obtains a first clock by passing through a number of the delay units in response to the first control signal; the internal clock obtains a second clock by passing through a number of the delay units in response to the second control signal; the method for making the DLL circuit escape from the overflow or the underflow is: keeping the current first control signal unchanged to keep the current first clock unchanged; randomly generating a new second control signal to control the internal clock to pass through a random number of the delay units to update the second clock; and updating the feedback clock based on the current first clock and the updated second clock.

[0013] Before randomly generating an updated second control signal, the current first clock is used through the DLL circuit as a temporary clock for the current output data. If overflow or underflow is detected in the DLL circuit, the current first clock is delayed by the subsequent portion of the DLL circuit and directly output to the external circuit as a temporary clock for the output data. This provides a clock with minimal error for the output data before relocking, thus preventing data read interruptions, ensuring data read continuity in the DRAM, and minimizing instruction and data loss during the time required for relocking.

[0014] The DLL circuit also includes a duty cycle adjustment module connected to the input end of the coarse adjustment delay module, which is used to receive an external clock and adjust its duty cycle before outputting the internal clock; the delay chain includes a first branch and a second branch each having N delay units; the first clock is obtained by delaying the internal clock through i delay units of the first branch to obtain the first clock, 1≤i≤N; the second clock is obtained by delaying the internal clock through j delay units of the second branch to obtain the second clock, 1≤j≤N; wherein N, i and j are positive integers; the process of determining whether the number of delay units can be further changed to continue to increase or decrease the current delay amount includes determining whether the difference between i and j can continue to increase or decrease.

[0015] The first clock is an odd-frequency divided signal; the second clock is an even-frequency divided signal.

[0016] The control signal also includes a fine-tuning control signal; the method of updating the feedback clock includes: the fine-tuning delay module responds to the fine-tuning control signal, delays the first clock based on the phase difference between the first clock and the second clock, obtains and outputs a delayed clock; and accumulates the system fixed delay on the delayed clock to obtain the feedback clock.

[0017] The delayed clock is obtained by dividing the phase difference between the first and second clocks into a number of delay steps based on delay accuracy requirements; and then delaying the first clock by m delay steps to obtain the delayed clock. The fine-tuning delay module divides the unit delay step into a number of delay steps based on the specific delay accuracy requirements, and the fine-tuning control signal is used to set the number of delay steps to accumulate the delay, further improving the locking speed and accuracy.

[0018] Compared with the prior art, the present invention has the following main beneficial effects:

[0019] 1. The present invention's method for rapidly relocking a DLL circuit detects overflow or underflow in real time by determining whether the current delay can continue to change to compensate for the phase difference. Based on the detection result, control signals are set accordingly, enabling rapid alignment of the external clock with the feedback clock. Randomly updating the control signals allows the DLL circuit to quickly return to a normal phase-locked state without resetting, ensuring phase alignment between the DRAM's output clock and input clock. By directly outputting the first clock through the DLL circuit when overflow or underflow occurs, a clock with minimal error is provided to the output data before relocking, avoiding transmission interruptions and significantly reducing instruction and data loss.

[0020] 2. The implementation of the method for rapidly relocking the DLL circuit of the present invention is extremely beneficial for improving the reliability of DRAM operation, providing a practical and effective solution for overcoming the limitations on the application of devices integrating DRAM due to the adverse effects of environmental factors such as temperature, and further promoting the in-depth application of integrated circuit devices in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the principle of DLL circuit synchronization clock according to an example of the present invention.

[0022] Figure 2 FIG. 1 is a block diagram of a DLL circuit according to a first embodiment of the present invention.

[0023] Figure 3 FIG. 1 is a simplified block diagram of a DLL circuit according to a first embodiment of the present invention.

[0024] Figure 4 This is a signal timing diagram of the DLL circuit according to the first embodiment of the present invention when it is normally phase-locked.

[0025] Figure 5 Schematic diagram of the basic structure of the delay chain module according to the first embodiment of the present invention.

[0026] Figure 6 Schematic diagram of a delay link according to the first embodiment of the present invention.

[0027] Figure 7 This is a timing diagram of the signal output by the fine-tuning delay module in the first embodiment of the present invention.

[0028] Figure 8 Schematic diagram of a delayed link when underflow occurs according to the first embodiment of the present invention.

[0029] Figure 9 1 is a schematic diagram of a method for quickly relocking a DLL circuit according to an embodiment of the present invention.

[0030] Figure 10 Schematic diagram of a delay link when relocking a DLL circuit in Embodiment 1 of the present invention.

[0031] Figure 11 This is a schematic diagram of a delayed link when an overflow occurs in embodiment 2 of the present invention.

[0032] Figure 12 Schematic diagram of the delay link when relocking the DLL circuit in the second embodiment of the present invention. DETAILED DESCRIPTION

[0033] In the following embodiments, the operations of the embodiments are described in a specific order. The description of these orders is for a better understanding of the details in the embodiments so as to fully understand the present invention. However, the description of these orders does not necessarily correspond one-to-one to the methods of the present invention, nor can it be used to limit the scope of the present invention.

[0034] Example 1

[0035] like Figure 2 As shown, the DLL circuit of the present embodiment includes a phase detection module phase detect, a control module control, a duty cycle adjustment module DCC, a delay chain module delay_line and a fixed delay module delay_replica. The communication connection of each part is the same as the conventional DLL circuit and will not be expanded. After the external clock clk and the initial feedback clock clk_fb are compared in phase by the phase detection module phase detect, the control module control makes a control strategy to control the duty cycle adjustment module DCC and the delay chain module delay_line. In the example case, the duty cycle adjustment module DCC adjusts the duty cycle of the external clock clk to 50% to obtain the internal clock. The external clock clk is delayed by the delay chain module delay_line to obtain the delayed clock clk_1, and clk_1 accumulates the system fixed delay through the fixed delay module delay_replica to update the feedback clock clk_fb. In order to facilitate understanding of the main points of the present invention, the work of the duty cycle adjustment module DCC is omitted here, as shown in the following figure. Figure 3 As shown, Figure 3 Lieutenant General Figure 2 The delay link portion of the DLL circuit structure can be simplified into the delay chain module delay_line and the fixed delay module delay_replica. An example is provided to illustrate the current delay operation. It should be noted that the above simplification is for ease of explanation and does not necessarily imply that the DLL circuit structure of this embodiment does not include the duty cycle adjustment module DCC. When the DLL circuit of this embodiment is normally phase-locked, the timing diagram of the delayed clock clk_1 output by the delay chain module delay_line, the input external clock clk, and the feedback clock clk_fb output by the DLL circuit during phase lock is shown in the following figure. Figure 4As shown. The analog delay link of the fixed delay module delay_replica is the inherent delay of the replication system and is affected by factors such as process drift and temperature. For clarity, this embodiment uses delay time to characterize the delay. In the application scenario of this embodiment, temperature is positively correlated with the delay time of the fixed delay module delay_replica. As the temperature rises, the delay time t_rep of the fixed delay module delay_replica increases, while the total delay time t_delay for normal phase locking remains fixed. Therefore, the delay time t_line of the delay chain module delay_line needs to be reduced to ensure the proper operation of the DLL circuit. However, when the temperature rises beyond a certain range, t_line needs to be reduced to less than the minimum delay time provided by the delay chain module delay_line. At this point, t_line cannot be further reduced, and the DLL circuit will fail to phase lock properly. This loss of lock is referred to as underflow in this embodiment. Conversely, when the temperature decreases, the delay time t_rep of the fixed delay module delay_replica decreases accordingly, causing the delay time t_line required by the delay chain module delay_line to continue to increase. When the required delay time t_line reaches the maximum delay time provided by the delay chain module delay_line, t_line can no longer be increased, and the DLL circuit will no longer be able to properly lock to its phase. This loss of lock is referred to in this embodiment as an overflow. In DRAM memory, the external clock clk is the CPU's command clock, and the feedback clock clk_fb is the clock that outputs data. When an overflow or underflow occurs, the DLL circuit loses its proper phase lock. The external clock clk and the current feedback clock clk_fb cannot maintain the same phase. Rapidly escaping the overflow or underflow and re-locking are necessary to ensure that the CPU can properly read DRAM data.

[0036] The delay chain module delay_line and the signal flow of this embodiment are as follows Figure 5 As shown. The internal clock clk_coarse input to the coarse delay module coarse delay responds to the first control signal and the second control signal output by the control module control, and generates the first clock and the second clock input to the fine delay module fine delay. Figure 6The example delay chain includes a first branch A and a second branch B, each having N delay units. 1≤i≤N, 1≤j≤N; wherein N, i and j are positive integers. In this embodiment, the control module control includes a detection unit and a first counter, a second counter and a third counter. When there is no underflow or overflow, the control module control outputs a command to increase or decrease the current delay amount according to the size of the current phase difference. The first control signal of the example is the odd control code cnt_odd; the second control signal is the even control code cnt_even. The fine-tuning control signal is directly input to the fine-tuning delay module fine delay, including a counting control code cnt_fine. In this embodiment, the first clock clk_odd is an odd-numbered frequency-divided signal generated by the internal clock clk_coarse after passing through i delay units; the second clock clk_even is an even-numbered frequency-divided signal generated by the internal clock clk_coarse after passing through j delay units. The first clock clk_odd and the second clock clk_even are input together into the fine-tuning delay module fine delay. As shown Figure 6 As shown, each delay unit is composed of three NAND gates, with the outputs of two NAND gates connected to the first input and the second input of the third NAND gate, respectively. The delay unit may also have other structures, such as inverters, transmission gates, and other circuit structures to implement the delay function, and the circuit structure is not limited thereto. Figure 6The example has a total of 18 delay cells, meaning the example value of N is 9. A maximum of 9 delay cells can be used to generate the first clock clk_odd; a maximum of 9 delay cells can be used to generate the second clock clk_even. The number of delay cells in the coarse delay module and the maximum values ​​of i and j are not limited by this and can be set based on the actual application or specific product design parameters. In this embodiment, the first clock clk_odd and the second clock clk_even pass through the same number of NAND gates, either an even number or an odd number. The first clock clk_odd and the second clock clk_even have a phase difference. In this embodiment, the fine-tuning control signal also includes a frequency division signal for performing frequency division based on the actual delay accuracy requirements. This divides the phase difference between the first clock clk_odd and the second clock clk_even into a number of equal parts for further fine-tuning the delay. Each equal part is a delay step (a larger number of equal divisions results in a smaller single delay step for fine-tuning the delay, and thus a higher delay accuracy). The phase difference between the first clock clk_odd and the second clock clk_even is divided into n equal parts. A delay step is one-nth of the phase difference. The fine-tuning control signal cnt_fine is input to the fine-tuning delay module fine delay to select the delay of the input first clock clk_odd by m delay steps, that is, assign a value to m. Finally, the delayed clock clk_1 output by the delay chain module delay_line is the first clock clk_odd plus m delay steps. Figure 7 As shown, in the exemplary case, a 1 / 8 ratio frequency divider is used, n is 8, and m is 2. The result of fine-tuning the delay is to add two delay steps based on the first clock clk_odd.

[0037] During the DLL circuit locking process of this embodiment, the control module decides whether to increase or decrease the currently provided delay amount based on the size of the acquired phase difference. The corresponding first control signal cnt_odd and the second control signal cnt_even determine the number of delay units in the coarse delay module to be used, that is, assign values ​​to i and j. The first control signal cnt_odd and the second control signal cnt_even determine whether the number of delay units used in the delay chain through which the first clock clk_odd and the second clock clk_even pass is alternately increased or decreased. In this embodiment, the delay chain when underflow occurs is as follows: Figure 8As shown, after comparing the phases of the external clock clk and the current feedback clock clk_fb, the control module issues a command to continue reducing the current delay amount. However, at this point, the minimum number of delay units has been used to participate in the delay chain, that is, the current i and j are already at their minimum value of 1. It can be seen that the number of delay units used in the first branch chain A of the first clock clk_odd and the second branch chain B of the second clock clk_even cannot continue to decrease alternately, that is, the difference between i and j cannot continue to decrease. Figure 8 In the example, the phase difference between the first clock clk_odd and the second clock clk_even is already the smallest, and the delay of the delayed clock clk_1 cannot be further reduced, that is, t_line cannot be reduced. Then the detection unit detects that underflow has occurred at this time. Figure 9 As shown, an exemplary method for rapidly relocking a DLL circuit includes: Step S1. Obtaining, through the control module control, the phase difference between the current external clock clk and the feedback clock clk_fb, as well as the current delay provided by the coarse delay module coarse_delay. Step S2. Determining whether the current delay can continue to change to compensate for the phase difference, and detecting in real time whether underflow exists. Different operations are performed: If underflow does not exist, the control module control updates the current control signal based on the phase difference to adjust the current delay and update the feedback clock, and the process returns to Step S1; if underflow exists, the control module control randomly generates a new control signal to set the current delay so that the DLL circuit avoids underflow, and the process returns to Step S1. Steps S1 to S2 are repeated until the external clock clk and the feedback clock clk_fb are phase-aligned. The method for rapidly relocking a DLL circuit in this embodiment can be implemented through VLSI design, combining corresponding algorithms with a digital ASIC process to design the control module. In some specific applications, this is implemented through analog circuit design, but is not limited to this.

[0038] When underflow occurs, the control module control keeps the current first control signal cnt_odd unchanged, so that the current first clock clk_odd remains unchanged. The control module control randomly sets a new second control signal cnt_even to control the internal clock clk_coarse to pass through a random number of delay units to obtain an updated second clock clk_even. Figure 10As shown, the random number of delay units in this embodiment is five. The random number can be greater than the minimum value of j and is not limited thereto. The new second clock clk_even and the unchanged current first clock clk_odd are input to the fine delay module finedelay to generate an updated delayed clock clk_1. After passing through the fixed delay module delay_replica, the updated feedback clock clk_fb is output. The phase detector module phase detect compares the phase of this updated feedback clock clk_fb with the external clock clk. The control module control updates the first and second control signals based on the phase difference, restarting the DLL circuit phase lock process until the external clock clk and the final feedback clock clk_fb are aligned in phase. In this embodiment, the example in which the first control signal is an odd control code cnt_odd and the second control signal is an even control code cnt_even is used to facilitate understanding of the present invention. In some implementations, the delay link structure of the coarse delay module and the circuit structure of the fine delay module are set accordingly according to actual applications and product designs, and there may be more corresponding counters or signals generated by them. The control signal may be a digital signal or an analog signal, and is set accordingly according to the DLL circuit design of the specific application, but is not limited thereto.

[0039] Example 2

[0040] like Figure 11 As shown, the second embodiment provides an example of a method for quickly relocking the DLL circuit when an overflow occurs. In step S2, it is determined whether the current delay amount can continue to change to compensate for the phase difference, and whether there is an overflow is detected in real time. After comparing the phases of the external clock clk currently input to the DLL circuit and the feedback clock clk_fb, the control module control determines that a command to increase the delay needs to be issued. At the same time, the detection unit determines that the most delay units in the current first branch A and the second branch B have been used to participate in the delay link. That is, it is determined that the current values ​​of i and j have reached their maximum values ​​respectively. Then it is detected that an overflow has occurred in the DLL circuit at this time. As shown Figure 11 As shown in FIG, the current first clock clk_odd is generated by the internal clock clk_coarse after passing through 9 delay units, and the second clock clk_even is also obtained after passing through 9 delay units. At this time, the current delay amount cannot be increased. Figure 12As shown, the control module control maintains the current first control signal cnt_odd unchanged, so that the current first clock clk_odd remains unchanged. On the one hand, the clock output by the current first clock clk_odd after passing through the fine delay module fine delay and then the fixed delay module delay_replica is used as the clock for outputting data, ensuring that the current DRAM memory can read and write data normally without losing instructions or data. On the other hand, the control module control sets a new second control signal cnt_even to control the internal clock clk_coarse to pass through a random number of delay units to obtain an updated second clock clk_even. The random number used in this embodiment is 5 delay units. The random number can be less than the maximum value of j and is not limited. The updated second clock clk_even and the unchanged current first clock clk_odd are input into the fine delay module fine delay to generate an updated delayed clock clk_1. After passing through the fixed delay module delay_replica, the updated delayed clock clk_1 outputs an updated feedback clock clk_fb. The phase detection module phase detect compares the phase of the updated feedback clock clk_fb with the external clock clk. The control module control generates the first control signal and the second control signal based on the phase difference at this time to restart the DLL circuit phase locking process until the external clock clk and the final feedback clock clk_fb are in phase.

[0041] In this embodiment, the control module control is specifically configured as a detection unit and a counting unit, and the corresponding control signal is a counter signal. This is to facilitate understanding of the specific application of the present invention. In other implementations, the control module control comprises other specific circuit components, and may also include circuit elements such as encoders, buffers, and logic units. The control signal may be in a form other than a counter signal, such as a current signal, a voltage signal, or other analog signal, without limitation. This embodiment illustrates a method for the control module control to detect overflow in real time. In other implementations, other methods combined with specific circuit structures may be used, such as comparing the current phase difference with the previous phase difference to determine whether the two phase comparison results are different, thereby detecting whether the DLL circuit is in normal operation. This is not limited to this method.

[0042] For the sake of clarity, some commonly used English nouns or letters used in this invention are only for illustrative purposes and are not intended to be limiting or specific. Their possible Chinese translations or specific letters should not be used to limit the scope of protection of this invention. It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0043] This document uses specific examples to illustrate the structure and working principle of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for rapidly relocking a DLL circuit, wherein the DLL circuit comprises a control module and a delay chain module; the delay chain module comprises a coarse delay module and a fine delay module connected in series; and wherein: The steps include: Step S1. Obtaining, by the control module, a phase difference between a current external clock and a feedback clock of the DLL circuit and a current delay amount provided by the coarse adjustment delay module; Step S2. Determine whether the current delay can continue to change to compensate for the phase difference, and detect in real time whether there is overflow or underflow; If not, the control module updates the current control signal based on the phase difference to adjust the current delay amount and update the feedback clock, and then returns to step S1; If so, randomly generating an updated control signal through the control module to set the current delay amount so that the DLL circuit is out of the overflow or underflow, and returning to step S1; Repeating step S1 to step S2 until the external clock and the feedback clock are phase-aligned; The control signal includes a first control signal and a second control signal; the internal clock responds to the first control signal and passes through a plurality of delay units to obtain a first clock; the internal clock responds to the second control signal and passes through a plurality of delay units to obtain a second clock; The method of making the DLL circuit out of the overflow or underflow is: Keeping the current first control signal unchanged to keep the current first clock unchanged; randomly generating a new second control signal to control the internal clock to go through a random number of delay units to update the second clock; The feedback clock is updated based on the current first clock and the updated second clock.

2. The method for rapidly relocking a DLL circuit according to claim 1, wherein: The coarse delay module includes a plurality of delay chains, each of which includes a plurality of delay units connected in cascade, and the current delay amount is based on the number of delay units traversed by the internal clock of the DLL circuit; The method of detecting overflow or underflow in real time includes: determining, according to the phase difference, whether the current delay amount needs to be further increased or decreased; The number of currently used delay units is obtained through the control module, and it is determined whether the number of delay units can be further changed to continue increasing or decreasing the current delay amount.

3. The method for rapidly relocking a DLL circuit according to claim 2, wherein: The method for detecting the overflow is: if the current delay amount needs to be further increased and the currently used delay units have reached the maximum, then it is determined that the overflow exists.

4. The method for rapidly relocking a DLL circuit according to claim 2, wherein: The method for detecting the existence of the underflow is: if the current delay amount needs to be further reduced and the currently used delay units are already the minimum, then it is determined that the underflow exists.

5. The method for rapidly relocking a DLL circuit according to claim 1, wherein: Before randomly generating the updated second control signal, the current first clock is used as a temporary clock for current output data through the DLL circuit.

6. The method for rapidly relocking a DLL circuit according to claim 1, wherein: The DLL circuit further includes a duty cycle adjustment module connected to the input end of the coarse adjustment delay module, configured to receive an external clock and adjust its duty cycle before outputting the internal clock; the delay chain includes a first branch and a second branch each having N delay units; The first clock is obtained by delaying the internal clock through the i delay units of the first branch chain to obtain the first clock, where 1≤i≤N; The second clock is obtained by delaying the internal clock through j delay units of the second branch chain to obtain the second clock, where 1≤j≤N; Wherein N, i and j are positive integers; the process of determining whether the number of delay units can be further changed to continue increasing or decreasing the current delay amount includes determining whether the difference between i and j can continue to increase or decrease.

7. The method for rapidly relocking a DLL circuit according to claim 6, wherein: The first clock is an odd-frequency divided signal; the second clock is an even-frequency divided signal.

8. The method for rapidly relocking a DLL circuit according to claim 7, wherein: The control signal also includes a fine-tuning control signal; the method of updating the feedback clock includes: the fine-tuning delay module responds to the fine-tuning control signal, delays the first clock based on the phase difference between the first clock and the second clock, obtains and outputs a delayed clock; and accumulates the system fixed delay on the delayed clock to obtain the feedback clock.

9. The method for rapidly relocking a DLL circuit according to claim 8, wherein: The delayed clock is obtained by dividing the phase difference between the first clock and the second clock into a number of delay steps based on the delay accuracy requirement; The first clock is cumulatively delayed by m delay steps to obtain the delayed clock.

Images