Wiring electrode

Abstract

The present invention provides a wiring electrode that can suppress alloying between metal layers and can improve reliability. The wiring electrode 1 of the present invention is a wiring electrode formed by laminating a plurality of layers on a piezoelectric substrate 12 (substrate), and includes an adhesive layer 2 in contact with the piezoelectric substrate 12, a topmost layer 5 indirectly provided on the adhesive layer 2, a low-resistance layer 3 provided between the adhesive layer 2 and the topmost layer 5, having a first main surface 3c on the adhesive layer 2 side and a second main surface 3d opposed to the first main surface 3c, and having the lowest resistance among the plurality of layers, and a barrier layer 4 provided between the low-resistance layer 3 and the topmost layer 5. In a plan view, the outer periphery of the second main surface 3d of the low-resistance layer 3 is located inside compared to the outer periphery 4a of the barrier layer 4, and the outer periphery 2a of the adhesive layer 2 is located outside compared to the outer periphery 3a of the low-resistance layer 3.

Description

Technical Field

[0001] The present invention relates to a wiring electrode. Background Art

[0002] Heretofore, wiring electrodes have been used in various electronic components. An example of a wiring electrode used in a surface acoustic wave device is disclosed in Patent Document 1 below. The wiring electrode is provided on a substrate. An AlCu layer, a Cu layer, a Ti layer, and an Au layer are laminated in this order in the wiring electrode. Each metal layer is formed by a lift-off method. By inserting the Cu layer and the Ti layer between the AlCu layer and the Au layer, alloying due to metal diffusion between Al in the AlCu layer and Au in the Au layer can be suppressed.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-065092 Summary of the Invention

[0006] In the wiring electrode of Patent Document 1, alloying due to mutual metal diffusion between the main surfaces of the AlCu layer and the Au layer is suppressed. However, when each metal layer is formed by the lift-off method, Au constituting the Au layer sometimes surrounds the side surface of the formed AlCu layer. Therefore, alloying may occur between the side surface of the AlCu layer and the surrounding Au. As a result, the resistance of the wiring electrode may increase, and sometimes the reliability deteriorates.

[0007] An object of the present invention is to provide a wiring electrode capable of suppressing alloying between metal layers and improving reliability.

[0008] The wiring electrode according to the present invention is a wiring electrode formed by laminating a plurality of layers on a substrate, and includes: an adhesive layer in contact with the substrate; a top layer indirectly provided on the adhesive layer; a low-resistance layer provided between the adhesive layer and the top layer, having a first main surface on the adhesive layer side and a second main surface opposed to the first main surface, and having the lowest resistance among the plurality of layers; and a barrier layer provided between the low-resistance layer and the top layer; the adhesive layer, the low-resistance layer, the barrier layer, and the top layer each have an outer periphery, and in a plan view, the outer periphery of the second main surface of the low-resistance layer is located inside the outer periphery of the barrier layer, and the outer periphery of the adhesive layer is located outside the outer periphery of the low-resistance layer.

[0009] According to the wiring electrode of the present invention, alloying between metal layers can be suppressed, and reliability can be improved. Brief Description of the Drawings

[0010] Figure 1 It is a cross-sectional view of a wiring electrode according to the first embodiment of the present invention.

[0011] Figure 2 It is a cross-sectional view of an elastic wave device including the wiring electrode according to the first embodiment of the present invention along the direction in which the electrode fingers of the IDT electrode extend.

[0012] Figure 3 It is a cross-sectional view of a wiring electrode showing a state in which bumps are provided on the wiring electrode according to the first embodiment of the present invention.

[0013] Figure 4 It is a top view of the IDT electrode of an elastic wave device including the wiring electrode according to the first embodiment of the present invention.

[0014] Figure 5 (a) to Figure 5 (e) are cross-sectional views showing a part corresponding to the cross-section shown in Figure 2 an example for explaining a manufacturing method of an elastic wave device according to the first embodiment of the present invention.

[0015] Figure 6 (a) and Figure 6 (b) are cross-sectional views for explaining a process of forming a laminate of metal layers in an example of a method for forming a wiring electrode according to the first embodiment of the present invention.

[0016] Figure 7 (a) and Figure 7 (b) are cross-sectional views for explaining an etching process in an example of a method for forming a wiring electrode according to the first embodiment of the present invention.

[0017] Figure 8 It is a cross-sectional view of a wiring electrode showing a state in which a metal constituting the outermost layer adheres to a metal layer that is a low-resistance layer of the wiring electrode.

[0018] Figure 9 It is a cross-sectional view of a wiring electrode according to the first modification of the first embodiment of the present invention.

[0019] Figure 10 It is a cross-sectional view of a wiring electrode according to the second modification of the first embodiment of the present invention.

[0020] Figure 11 It is a cross-sectional view of a wiring electrode according to the third modification of the first embodiment of the present invention.

[0021] Figure 12 It is a cross-sectional view of a wiring electrode according to the second embodiment of the present invention.

[0022] Figure 13 This is a cross-sectional view of a wiring electrode according to the third embodiment of the present invention.

[0023] Figure 14 This is a cross-sectional view of a wiring electrode according to the fourth embodiment of the present invention.

[0024] Figure 15 This is a cross-sectional view of a wiring electrode according to the first modification of the fourth embodiment of the present invention.

[0025] Figure 16 This is a cross-sectional view of a wiring electrode according to the second modification of the fourth embodiment of the present invention.

[0026] Figure 17 This is a cross-sectional view of a surface acoustic wave device including a wiring electrode according to the fifth embodiment of the present invention along the direction in which the electrode fingers of the IDT electrode extend.

[0027] Figure 18 This is a cross-sectional view of a wiring electrode according to the fifth embodiment of the present invention.

[0028] Figure 19 This is a cross-sectional view showing a part corresponding to the cross-section shown in Figure 17 and is an example for explaining a manufacturing method of a surface acoustic wave device according to the fifth embodiment of the present invention.

[0029] Figure 20 (a) to Figure 20 (c) are enlarged cross-sectional views for explaining an example of a manufacturing method of a surface acoustic wave device according to the fifth embodiment. Detailed Embodiments

[0030] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings to make the present invention clearer.

[0031] It should be noted that each embodiment described in this specification is an exemplification, and it should be pointed out that component substitution or combination can be made between different embodiments.

[0032] Figure 1 This is a cross-sectional view of a wiring electrode according to the first embodiment of the present invention. Figure 2 This is a cross-sectional view of a surface acoustic wave device including a wiring electrode according to the first embodiment along the direction in which the electrode fingers of the IDT electrode extend. Figure 2 The dash-dot line A in Figure 2 represents the boundary between the first bus bar and the first electrode finger of the IDT electrode described later. The dash-dot line A in other cross-sectional views also represents the same boundary. It should be noted that Figure 1 the cross-section in

[0033] is a cross-section along the surface acoustic wave propagation direction described later. AsFigure 1 As shown, the wiring electrode 1 is provided on the piezoelectric substrate 12. The wiring electrode 1 is formed by laminating multiple layers. As Figure 2 shown, the wiring electrode 1 of the present embodiment is used in the elastic wave device 10 including the piezoelectric substrate 12. The piezoelectric substrate 12 is a piezoelectric substrate composed only of a piezoelectric layer. For the piezoelectric layer, lithium tantalate, lithium niobate, zinc oxide, aluminum nitride, quartz, PZT, etc. can be used, for example. It should be noted that the piezoelectric substrate 12 may be composed of a laminate including a piezoelectric layer and other layers.

[0034] However, the wiring electrode related to the present invention can also be used for electronic components other than elastic wave devices. In this case, the wiring electrode can be provided on a substrate other than the piezoelectric substrate. Or, when the wiring electrode is used for an elastic wave device or the like, the wiring electrode can also be provided on a substrate other than the piezoelectric substrate.

[0035] As Figure 1 and Figure 2 shown, the wiring electrode 1 has an adhesive layer 2 in contact with the piezoelectric substrate 12, a low-resistance layer 3 provided on the adhesive layer 2, a barrier layer 4 provided on the low-resistance layer 3, and a topmost layer 5 provided on the barrier layer 4.

[0036] The adhesive layer 2 is a layer that bonds the wiring electrode 1 and the piezoelectric substrate 12. The low-resistance layer 3 has the lowest resistance among the multiple layers of the wiring electrode 1. The topmost layer 5 is indirectly provided on the adhesive layer 2 and is located at the uppermost layer among the multiple layers of the wiring electrode 1. It should be noted that in this specification, the upper layer refers to Figure 1 the layer above in

[0037] Figure 3 is a cross-sectional view of the wiring electrode showing the state where bumps are provided on the wiring electrode according to the first embodiment.

[0038] The wiring electrode 1 has a bump pad portion 1a. A bump 6 is provided on the topmost layer 5 in the bump pad portion 1a. Figure 3 The bump 6 shown, for example, is an Au bump or the like.

[0039] Here, the materials and film thicknesses of the respective layers of the wiring electrode 1 of the present embodiment are as follows.

[0040] Adhesive layer 2: Material... Ti, Film thickness... 50 nm

[0041] Low-resistance layer 3: Material... Al, Film thickness... 800 nm

[0042] Barrier layer 4: Material... Ti, Film thickness... 100 nm

[0043] The outermost layer 5: material... Au, film thickness... 400 nm

[0044] However, the materials and film thicknesses of the respective layers of the wiring electrode 1 are not limited to the above. It should be noted that the adhesive layer 2 is preferably composed of at least one metal selected from Ti, Ni, Cr, and alloys mainly composed of these metals. Thereby, the bonding force between the wiring electrode 1 and the piezoelectric substrate 12 can be appropriately increased. The low-resistance layer 3 is preferably composed of Al or an alloy mainly composed of Al. Thereby, the resistance of the wiring electrode 1 can be appropriately reduced. It should be noted that the low-resistance layer 3 can be composed of Cu or the like, for example. The outermost layer 5 is preferably composed of Au or an alloy mainly composed of Au. Thereby, Au bumps or the like can be appropriately bonded to the wiring electrode 1. It should be noted that the outermost layer 5 can be composed of Pt or the like, for example.

[0045] As Figure 1 shown, the low-resistance layer 3 has an outer periphery 3a. In this specification, the outer periphery refers to the outer periphery in a plan view, and the plan view refers to Figure 1 viewed from above. The low-resistance layer 3 has a first main surface 3c on the side of the adhesive layer 2, a second main surface 3d opposed to the first main surface 3c, and a side surface 3b connecting the first main surface 3c and the second main surface 3d. In the present embodiment, the side surface 3b of the low-resistance layer 3 extends in a direction perpendicular to the main surface of the piezoelectric substrate 12. The outer periphery 3a of the low-resistance layer 3 is located on the side surface 3b.

[0046] It should be noted that the side surface 3b may extend obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12. Or, the side surface 3b may have a curved surface shape. In these cases, the outer periphery 3a of the low-resistance layer 3 is located at the outermost part of the side surface 3b. Here, take Figure 1 the length in the direction perpendicular to the thickness direction of the wiring electrode 1 in the cross section of the wiring electrode 1 shown as the width. For example, in the case of extending obliquely such that the width of the low-resistance layer 3 becomes narrower toward the piezoelectric substrate 12 side, the outer periphery of the second main surface 3d corresponds to the outer periphery 3a of the entire low-resistance layer 3. On the other hand, in the case of extending obliquely such that the width of the low-resistance layer 3 becomes wider toward the piezoelectric substrate 12 side, in the plan view, the outer periphery of the second main surface 3d is located inside the outer periphery 3a of the low-resistance layer 3. However, in the present embodiment, the width of the low-resistance layer 3 is constant, so the outer periphery of the second main surface 3d corresponds to the outer periphery 3a of the entire low-resistance layer 3.

[0047] Similar to the low-resistance layer 3, the adhesive layer 2, the barrier layer 4, and the outermost layer 5 each have an outer periphery 2a, an outer periphery 4a, and an outer periphery 5a. Also, the adhesive layer 2, the barrier layer 4, and the outermost layer 5 have side surfaces 2b, 4b, and 5b. In the present embodiment, the side surfaces 2b, 4b, and 5b of the adhesive layer 2, the barrier layer 4, and the outermost layer 5 extend perpendicular to the main surface of the piezoelectric substrate 12. It should be noted that the side surfaces 2b, 4b, and 5b may also extend obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12. Alternatively, the side surfaces 2b, 4b, and 5b may also have a curved surface shape.

[0048] As Figure 1 and Figure 2 shown, the outer periphery 3a of the low-resistance layer 3 is located inside compared to the outer periphery 4a of the barrier layer 4, and the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3. It should be noted that in a plan view, it is sufficient that the outer periphery of the second main surface 3d of the low-resistance layer 3 is located inside compared to the outer periphery 4a of the barrier layer 4, and the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3.

[0049] The outer periphery 2a of the adhesive layer 2, the outer periphery 4a of the barrier layer 4, and the outer periphery 5a of the outermost layer 5 overlap in a plan view. When taking the length in the direction perpendicular to the thickness direction of the wiring electrode 1 in the cross section of the wiring electrode 1 shown in Figure 1 as the width, the width of the low-resistance layer 3 is narrower than the widths of the adhesive layer 2, the barrier layer 4, and the outermost layer 5.

[0050] Figure 4 is a top view of the IDT electrode of the surface acoustic wave device including the wiring electrode according to the first embodiment. It should be noted that Figure 4 the wiring electrode is omitted. Figure 2 The cross section of the IDT electrode shown in Figure 4 is the cross section along the I-I line in

[0051] As Figure 2 and Figure 4 shown, an IDT electrode 13 is provided on the piezoelectric substrate 12. Elastic waves are excited by applying an alternating voltage to the IDT electrode 13. As Figure 4 shown, a pair of reflectors 14 and reflectors 15 are provided on both sides of the elastic wave propagation direction of the IDT electrode 13 on the piezoelectric substrate 12.

[0052] The IDT electrode 13 has a first bus bar 16 and a second bus bar 17 that face each other. The IDT electrode 13 has a plurality of first electrode fingers 18 each having one end connected to the first bus bar 16. Also, the IDT electrode 13 has a plurality of second electrode fingers 19 each having one end connected to the second bus bar 17. The plurality of first electrode fingers 18 and the plurality of second electrode fingers 19 are interlaced with each other.

[0053] As Figure 2 shown, a wiring electrode 1 is connected to the first bus bar 16 of the IDT electrode 13. The wiring electrode 1 extends from the first bus bar 16 onto the piezoelectric substrate 12. In the present embodiment, the wiring electrode 1 is provided on a part of the upper surface of the first bus bar 16, but the wiring electrode 1 may be provided on the entire upper surface of the first bus bar 16.

[0054] It should be noted that the wiring electrode 1 may not be directly connected to the IDT electrode 13. The wiring electrode 1 may be electrically connected to the IDT electrode 13 via other lead wirings connected to the IDT electrode 13 or the like. Here, in the case where the lead wiring or the like is connected to any position on the side surface 3b of the low-resistance layer 3 connected to the wiring electrode 1, the lead wiring is not included in the side surface 3b. For example, when the wiring electrode 1 is an electrode for external connection connected to the IDT electrode 13 via a lead wiring, the lead wiring is not included in the side surface 3b. That is, the outer periphery 3a of the second main surface 3d of the low-resistance layer 3 is the outer periphery of the side surface 3b when no lead wiring is connected.

[0055] The surface acoustic wave device 10 of the present embodiment is a surface acoustic wave resonator. However, the surface acoustic wave device is not limited to a surface acoustic wave resonator, and may be a filter device having a plurality of surface acoustic wave resonators, a multiplexer including the filter device, or the like. At this time, the wiring electrode according to the present invention can be connected to each surface acoustic wave resonator or the like.

[0056] The feature of the present embodiment is that in a plan view, the outer periphery 3a of the second main surface 3d of the low-resistance layer 3 is located inside compared to the outer periphery 4a of the barrier layer 4, and the outer periphery 2a of the adhesive layer 2 is located outside compared to the outer periphery 3a of the low-resistance layer 3. Thereby, alloying can be effectively suppressed and reliability can be improved. The following will describe this in detail together with the manufacturing method of the surface acoustic wave device 10 of the present embodiment.

[0057] Figure 5 (a) to Figure 5 (e) are cross-sectional views showing a part of the cross-section corresponding to Figure 2 that shown, which is an example of the manufacturing method of the surface acoustic wave device of the first embodiment. Figure 6 (a) and Figure 6(b) is a cross-sectional view of a process for forming a stack of metal layers in an example of a method for forming a wiring electrode according to the first embodiment. Figure 7 (a) and Figure 7 (b) are cross-sectional views for explaining an etching process in an example of a method for forming a wiring electrode according to the first embodiment.

[0058] As Figure 5 (a) shows, a piezoelectric substrate 12 is prepared. Next, the IDT electrode 13 shown in Figure 4 is formed on the piezoelectric substrate 12 by a lift-off method. More specifically, a resist pattern 7A is formed on the piezoelectric substrate 12. Portions corresponding to the shape of the IDT electrode 13 and portions corresponding to the reflectors 14 and 15 are opened in the resist pattern 7A. Next, as Figure 5 (b) shows, a metal film 13X is formed on the piezoelectric substrate 12 by evaporation or sputtering or the like so as to cover the resist pattern 7A. Next, the resist pattern 7A is peeled off, and as Figure 5 (c) shows, the IDT electrode 13 is obtained. The reflectors 14 and 15 are formed simultaneously with the IDT electrode 13. It should be noted that the method for forming the IDT electrode 13, the reflectors 14, and the reflectors 15 is not limited to the above.

[0059] Next, as Figure 5 (d) shows, a stack of metal layers 1X is formed on the piezoelectric substrate 12 extending from the first bus bar 16 of the IDT electrode 13. The stack 1X can be formed by a lift-off method or the like, for example. More specifically, as Figure 6 (a) shows, a resist pattern 7B is formed on the piezoelectric substrate 12. Next, as Figure 6 (b) shows, a metal layer 2X that becomes the adhesive layer 2 is formed. Next, a metal layer 3X that becomes the low-resistance layer 3 is laminated on the metal layer 2X. Next, a metal layer 4X that becomes the barrier layer 4 is laminated on the metal layer 3X. Next, a metal layer 5X that becomes the outermost layer 5 is laminated on the metal layer 4X. The metal layer 2X, the metal layer 3X, the metal layer 4X, and the metal layer 5X can be formed by evaporation or sputtering or the like, for example. Next, the resist pattern 7B is peeled off. Thus, a stack 1X of the adhesive layer 2, the metal layer 3X that becomes the low-resistance layer 3, the barrier layer 4, and the outermost layer 5 as shown in Figure 5 (d) is obtained.

[0060] Next, as Figure 7As shown in (a), a resist pattern 7C is formed on the piezoelectric substrate 12 so as to cover the side surfaces of each layer of the stack 1X. Next, the side surfaces of the metal layer 3X that becomes the low resistance layer 3 are etched. At this time, an etching liquid that acts on the metal layer 3X that becomes the low resistance layer 3 and does not easily act on the adhesive layer 2, the barrier layer 4, and the outermost layer 5 is used. More specifically, in the formation of the wiring electrode 1, a mixed solution of acetic acid, phosphoric acid, and nitric acid is used as an etching liquid. However, the types of etching liquids are not limited to the above.

[0061] By etching the side of the metal layer 3X, as Figure 7 As shown in (b), a low-resistance layer 3 is obtained whose outer periphery 3a is located inside the outer periphery 4a of the barrier layer 4. Next, the resist pattern 7C is peeled off. Figure 5 As shown in (e), the wiring electrode 1 of the first embodiment is obtained. Then, for example, a step involving heating, such as a step of bonding the bump 6 to the wiring electrode 1, may be performed.

[0062] When the outermost layer 5 of the wiring electrode 1 is joined to the bump 6, the outermost layer 5 is easily expanded when heated. In addition, when the bump 6 is joined, a large load is often applied to the outermost layer 5, or ultrasonic vibration is also applied. Therefore, especially when the outermost layer 5 is joined to the bump 6, a part of the expanded outermost layer 5 may pass over the outer periphery 4a of the barrier layer 4 and droop toward the piezoelectric substrate 12 side. As in the past, when the outer periphery of the low resistance layer overlaps with the outer periphery of the barrier layer in a plan view, a part of the outermost layer sometimes droops to the side of the low resistance layer. Therefore, the metal constituting the low resistance layer may alloy with the metal constituting the outermost layer, and the resistance of the wiring electrode may increase.

[0063] In contrast, in this embodiment, if Figure 1 As shown, in a plan view, the outer periphery 3a of the second main surface 3d of the low-resistance layer 3 is located inside the outer periphery 4a of the barrier layer 4. Thus, even when the outermost layer 5 is heated and expanded, it is difficult for the metal constituting the outermost layer 5 to reach the side surface 3b of the low-resistance layer 3. Therefore, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be effectively suppressed. Therefore, the increase in resistance of the wiring electrode 1 can be suppressed, and reliability can be improved.

[0064] The outer periphery 3a of the low resistance layer 3 is preferably located inside the outer periphery 4a of the barrier layer 4. As a result, it is more difficult for the metal constituting the outermost layer 5 to reach the side surface 3b of the low resistance layer 3. Therefore, alloying of the metal constituting the low resistance layer 3 and the metal constituting the outermost layer 5 can be further suppressed.

[0065] However, in the process of forming the laminated body 1X to be the wiring electrode 1, Figure 6As shown in (b), after forming the metal layer 3X that becomes the low-resistance layer 3 and the metal layer 4X that becomes the barrier layer 4, the metal layer 5X that becomes the outermost layer 5 is laminated on the metal layer 4X. At this time, the metal used to form the outermost layer 5 sometimes surrounds the side surface of the metal layer 3X that becomes the low-resistance layer 3. At this time, even after the resist pattern 7B is peeled off, the metal constituting the outermost layer 5 may adhere to the side surface of the metal layer 3X. Figure 8 The state in which the metal B constituting the outermost layer 5 adheres to the side surface of the metal layer 3X of the laminate 1X is shown. When a process accompanied by heating is performed in a state where the metal B adheres to the side surface of the metal layer 3X, the metal constituting the metal layer 3X is alloyed with the metal B, and the resistance of the wiring electrode may increase.

[0066] In contrast, when forming the wiring electrode 1 of the present embodiment, even if the metal B adheres to the side surface of the metal layer 3X, as Figure 7 (a) and Figure 7 (b) show, etching of the side surface of the metal layer 3X can still be performed. Thereby, the metal B is removed from the side surface of the metal layer 3X. Therefore, it is difficult for the metal B to remain on the side surface 3b of the formed low-resistance layer 3. Therefore, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be further suppressed.

[0067] In addition, as Figure 1 shows, the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3, so the area of the adhesive layer 2 can be increased. Thereby, the bonding force between the wiring electrode 1 and the piezoelectric substrate 12 can be improved. Therefore, the reliability can be further improved.

[0068] Here, as Figure 3 shows, in the wiring electrode 1, the outer periphery 5a of the outermost layer 5 is located outside the outer periphery 3a of the low-resistance layer 3. Thereby, the bonding area between the wiring electrode 1 and the bump 6 can be increased. Therefore, the bonding force between the wiring electrode 1 and an external electrode or the like can be improved. Therefore, the reliability can be improved more effectively.

[0069] And, in a plan view, the outer periphery 5a of the outermost layer 5 overlaps with the outer periphery 4a of the barrier layer 4. In this way, the outer periphery 5a of the outermost layer 5 is located outside the outer periphery 4a of the barrier layer 4, so the metal constituting the outermost layer 5 can be effectively prevented from reaching the side surface 3b of the low-resistance layer 3 due to expansion, stress, and ultrasonic vibration caused by heating. Therefore, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be effectively suppressed. On the other hand, the outer periphery 5a of the outermost layer 5 is located inside the outer periphery 4a of the barrier layer 4, so the bonding area between the outermost layer 5 and the bump 6 can be increased. Therefore, the bonding force with an external electrode or the like can be further improved, and the reliability can be improved more effectively.

[0070] AsFigure 1 or Figure 2 As described above, the structure of the present embodiment is illustrated in a cross-sectional view along the direction of elastic wave propagation or the direction in which the electrode fingers extend. However, in a cross-sectional view along a direction other than this, when the structure becomes Figure 1 the same effects as those described above can also be obtained. More specifically, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be suppressed, and reliability can be improved.

[0071] In the present embodiment, the side surface 3b of the low-resistance layer 3 extends in a direction perpendicular to the main surface of the piezoelectric substrate 12. However, the shape of the side surface 3b of the low-resistance layer 3 is not limited to the above. Hereinafter, first to third modification examples of the first embodiment in which only the shape of the side surface of the low-resistance layer is different from that of the first embodiment are shown. In the first to third modification examples, similar to the first embodiment, alloying of the metal constituting the low-resistance layer and the metal constituting the outermost layer can be suppressed, and reliability can be improved.

[0072] As Figure 9 shown, in the first modification example, the side surface 27b of the low-resistance layer 27 has a curved surface shape. More specifically, in the low-resistance layer 27, the width of the portion where the low-resistance layer 27 contacts the adhesive layer 2 or the portion where the low-resistance layer 27 contacts the barrier layer 4 is the widest. Figure 9 In the cross-section of the wiring electrode shown, the outer periphery 27a of the low-resistance layer 27 is located at the portion where the low-resistance layer 27 contacts the adhesive layer 2 or the portion where the low-resistance layer 27 contacts the barrier layer 4.

[0073] As Figure 10 shown, in the second modification example, the side surface 28b of the low-resistance layer 28 extends obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12. More specifically, the side surface 28b of the low-resistance layer 28 extends obliquely such that the width of the low-resistance layer 28 becomes wider as it approaches the piezoelectric substrate 12 side. Figure 10 In the cross-section of the wiring electrode shown, the outer periphery 28a of the low-resistance layer 28 is located at the portion where the low-resistance layer 28 contacts the adhesive layer 2. The outer periphery of the first main surface of the low-resistance layer 28 corresponds to the outer periphery of the entire low-resistance layer 28. It should be noted that when forming the wiring electrode of the second modification example, for example, after forming the low-resistance layer 28 in which the side surface 28b extends obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12, the barrier layer 4 and the outermost layer 5 can be formed.

[0074] As Figure 11 shown, in the third modification example, the side surface 29b of the low-resistance layer 29 extends obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12. More specifically, the side surface 29b of the low-resistance layer 29 extends obliquely such that the width of the low-resistance layer 29 becomes narrower as it approaches the piezoelectric substrate 12 side.Figure 11 In the cross-section of the wiring electrode shown, the outer periphery 29a of the low-resistance layer 29 is located at the portion where the low-resistance layer 29 contacts the barrier layer 4. The outer periphery of the second main surface of the low-resistance layer 29 corresponds to the outer periphery 29a of the entire low-resistance layer 29. It should be noted that when forming the wiring electrode of the third modification, for example, after forming the low-resistance layer 29 with the side surface 29b extending obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12, the barrier layer 4 and the outermost layer 5 can be formed.

[0075] Figure 12 It is a cross-sectional view of the wiring electrode according to the second embodiment.

[0076] In that the outer periphery 5a of the outermost layer 5 is located inside compared with the outer periphery 4a of the barrier layer 4, this embodiment is different from the first embodiment. Except for the above point, the wiring electrode of this embodiment has the same structure as the wiring electrode 1 of the first embodiment. It should be noted that the outer periphery 5a of the outermost layer 5 is located outside compared with the outer periphery 3a of the low-resistance layer 3.

[0077] As described above, the outer periphery 5a of the outermost layer 5 is located inside compared with the outer periphery 4a of the barrier layer 4. Thus, when the outermost layer 5 is heated and expanded by the formation of bumps or the like, it is possible to suppress a part of the expanded outermost layer 5 from hanging down toward the piezoelectric substrate 12 side over the outer periphery 4a of the barrier layer 4. Therefore, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be effectively suppressed. Therefore, an increase in the resistance of the wiring electrode can be effectively suppressed, and the reliability can be effectively improved.

[0078] In addition, similar to the first embodiment, the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3. Therefore, the area of the adhesive layer 2 can be increased, and thus, the bonding force between the wiring electrode and the piezoelectric substrate 12 can be improved, and the reliability can be further improved.

[0079] Figure 13 It is a cross-sectional view of the wiring electrode according to the third embodiment.

[0080] In that the outer periphery 5a of the outermost layer 5 is located inside compared with the outer periphery 3a of the low-resistance layer 3, this embodiment is different from the second embodiment. Except for this point, the wiring electrode of this embodiment has the same structure as the wiring electrode of the second embodiment.

[0081] As Figure 13As shown, the outer periphery 5a of the outermost layer 5 is located inside compared to the outer periphery 4a of the barrier layer 4, and is also located inside compared to the outer periphery 3a of the low-resistance layer 3. Thus, when the outermost layer 5 expands due to heating such as bump formation, it is possible to effectively prevent a part of the expanded outermost layer 5 from hanging down toward the piezoelectric substrate 12 side beyond the outer periphery 4a of the barrier layer 4. Therefore, alloying between the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be further suppressed. As a result, an increase in the resistance of the wiring electrode can be further suppressed, and reliability can be further improved.

[0082] In addition, similar to the second embodiment, the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3, so that the area of the adhesive layer 2 can be increased. Thereby, the bonding force between the wiring electrode and the piezoelectric substrate 12 can be improved, and reliability can be more effectively improved.

[0083] Figure 14 It is a cross-sectional view of a wiring electrode according to a fourth embodiment.

[0084] In this embodiment, the outer periphery 5a of the outermost layer 5 and the outer periphery 4a of the barrier layer 4 are located inside compared to the outer periphery 2a of the adhesive layer 2, which is different from the first embodiment. Except for this point, the wiring electrode of this embodiment has the same structure as the wiring electrode 1 of the first embodiment. It should be noted that the outer periphery 4a of the barrier layer 4 and the outer periphery 5a of the outermost layer 5 overlap in a plan view.

[0085] As Figure 14 shown, the outer periphery 4a of the barrier layer 4 is located inside compared to the outer periphery 2a of the adhesive layer 2, so the width of the portion where the barrier layer 4 does not contact the low-resistance layer 3 is narrow. Thereby, it is possible to prevent the barrier layer 4 and the outermost layer 5 from hanging down toward the piezoelectric substrate 12 side. Therefore, alloying between the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be effectively suppressed. As a result, an increase in the resistance of the wiring electrode can be effectively suppressed, and reliability can be effectively improved.

[0086] In addition, similar to the first embodiment, the outer periphery 2a of the adhesive layer 2 is located outside the outer periphery 3a of the low-resistance layer 3, so that the area of the adhesive layer 2 can be increased. Thereby, the bonding force between the wiring electrode and the piezoelectric substrate 12 can be improved, and reliability can be further improved.

[0087] In this embodiment, the side surface 2b of the adhesive layer 2, the side surface 4b of the barrier layer 4, and the side surface 5b of the outermost layer 5 extend in a direction perpendicular to the main surface of the piezoelectric substrate 12. It should be noted that the side surfaces 2b, 4b, and 5b can extend obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12, for example.

[0088] Figure 15It is a cross-sectional view of a wiring electrode according to a first modification of the fourth embodiment.

[0089] In the first modification of the fourth embodiment, the side surface 32b of the adhesive layer 32, the side surface 34b of the barrier layer 34, and the side surface 35b of the outermost layer 35 extend obliquely with respect to the direction perpendicular to the main surface of the piezoelectric substrate 12. More specifically, the side surface 32b of the adhesive layer 32, the side surface 34b of the barrier layer 34, and the side surface 35b of the outermost layer 35 extend obliquely such that the widths of the adhesive layer 32, the barrier layer 34, and the outermost layer 35 are wider closer to the piezoelectric substrate 12 side. Figure 15 In the cross-section of the wiring electrode shown, the outer periphery 32a of the adhesive layer 32 is at the portion where the adhesive layer 32 contacts the piezoelectric substrate 12. The outer periphery 34a of the barrier layer 34 is on the extension line C in the width direction of the portion where the barrier layer 34 contacts the low-resistance layer 3. The outer periphery 35a of the outermost layer 35 is at the portion where the outermost layer 35 contacts the barrier layer 34.

[0090] Figure 15 In the cross-section shown, the adhesive layer 32 has a pair of side surfaces 32b facing each other. The same applies to the low-resistance layer 3, the barrier layer 34, and the outermost layer 35. One of the side surfaces 32b of the adhesive layer 32, one of the side surfaces 34b of the barrier layer 34, and one of the side surfaces 35b of the outermost layer 35 are located on Figure 15 the straight imaginary line D1 shown. The other of the side surfaces 32b of the adhesive layer 32, the other of the side surfaces 34b of the barrier layer 34, and the other of the side surfaces 35b of the outermost layer 35 are located on Figure 15 the straight imaginary line D2 shown. The side surface 3b of the low-resistance layer 3 is inside the imaginary line D1 and the imaginary line D2. In this modification, as in the fourth embodiment, alloying between the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 35 can be further suppressed, and reliability can be improved. It should be noted that when the side surfaces 32b of the adhesive layer 32, the side surfaces 34b of the barrier layer 34, and the side surfaces 35b of the outermost layer 35 extend obliquely from the direction perpendicular to the main surface of the piezoelectric substrate 12, the side surfaces 32b, 34b, and 35b do not necessarily have to be located on a straight imaginary line.

[0091] Figure 16 It is a cross-sectional view of a wiring electrode according to a second modification of the fourth embodiment. Figure 16 The dash-dot line E1 in it indicates the position of the outer periphery of the low-resistance layer, and the dash-dot line E2 indicates the position of the outer periphery of the second main surface of the low-resistance layer. The dash-dot line F indicates the position of the outer periphery of the barrier layer.

[0092] In the second modification of the fourth embodiment, the side surface 28b of the low-resistance layer 28 extends obliquely such that the width of the low-resistance layer 28 becomes wider as it approaches the piezoelectric substrate 12 side. In this modification, the outer periphery 28a of the low-resistance layer 28 ( Figure 16 at the position indicated by the one-dot chain line E1 in) is located outside the outer periphery 4a of the barrier layer 4 ( Figure 16 at the position indicated by the one-dot chain line F in). On the other hand, similar to the fourth embodiment, in a plan view, the outer periphery of the second main surface 28d of the low-resistance layer 28 ( Figure 16 at the position indicated by the one-dot chain line E2 in) is located inside the outer periphery 4a of the barrier layer 4, and the outer periphery 2a of the adhesive layer 2 is located outside compared to the outer periphery 28a of the low-resistance layer 28. In this case, alloying of the metal constituting the low-resistance layer 28 and the metal constituting the outermost layer 5 can be suppressed, and reliability can be improved.

[0093] Figure 17 FIG. is a cross-sectional view of the surface acoustic wave device including the wiring electrode according to the fifth embodiment along the direction in which the electrode fingers of the IDT electrode extend. Figure 18 FIG. is a cross-sectional view of the wiring electrode according to the fifth embodiment. Figure 17 The one-dot chain line A1 and the one-dot chain line A2 in indicate the boundary between the first bus bar of the IDT electrode and the other part. Figure 17 The one-dot chain line A1 and the one-dot chain line A2 in cross-sectional views other than also indicate the same boundary.

[0094] As Figure 17 and Figure 18 shown, the barrier layer 44 of the wiring electrode 41 of the present embodiment includes a first barrier layer 44A and a second barrier layer 44B. The second barrier layer 44B is laminated on the first barrier layer 44A, and the outermost layer 5 is laminated on the second barrier layer 44B. For example, the material of the first barrier layer 44A and the material of the second barrier layer 44B may be the same material.

[0095] As Figure 18As shown, in the present embodiment, the outer periphery of the first barrier layer 44A is located outside compared to the outer periphery of the second barrier layer 44B. The outer periphery 44a of the barrier layer 44 is the outer periphery of the first barrier layer 44A. In a plan view, the outer periphery of the second barrier layer 44B overlaps with the outer periphery 5a of the outermost layer 5. Therefore, similar to the second embodiment, the outer periphery 5a of the outermost layer 5 is located inside compared to the outer periphery 44a of the barrier layer 44. The outer periphery 3a of the low-resistance layer 3 is located inside compared to the outer periphery 2a of the adhesive layer 2, the outer periphery 44a of the barrier layer 44, and the outer periphery 5a of the outermost layer 5. Therefore, also in the present embodiment, similar to the second embodiment, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be suppressed, and reliability can be improved. It should be noted that in a plan view, the outer peripheries of the first barrier layer 44A and the second barrier layer 44B may overlap.

[0096] Figure 17 In the surface acoustic wave device 40 shown, the wiring electrode 41 is provided integrally with the IDT electrode 53. More specifically, the first bus bar 16 of the IDT electrode 53 is provided integrally with the adhesive layer 2, the low-resistance layer 3, and the first barrier layer 44A of the wiring electrode 41. However, the first bus bar 16 may also have the second barrier layer 44B and the outermost layer 5 similarly to the wiring electrode 41.

[0097] Here, the materials of the respective layers of the wiring electrode 41 and the IDT electrode 53 in the present embodiment are as follows. However, the materials of the respective layers of the wiring electrode 41 and the IDT electrode 53 are not limited thereto.

[0098] Material of the adhesive layer 2: Ti

[0099] Material of the low-resistance layer 3: AlCu

[0100] Material of the first barrier layer 44A: Ti

[0101] Material of the second barrier layer 44B: Ti

[0102] Material of the outermost layer 5: Au

[0103] When obtaining the surface acoustic wave device 40, the process of forming the wiring electrode 41 and the process of forming the IDT electrode 53 can be performed simultaneously. Thereby, productivity can be improved. Hereinafter, an example of the manufacturing method of the surface acoustic wave device 40 will be described.

[0104] Figure 19 is a cross-sectional view showing a part of the cross-section corresponding to an example of the manufacturing method of the surface acoustic wave device for explaining the fifth embodiment Figure 17 shown. Figure 20 (a) to Figure 20(c) is an enlarged cross-sectional view showing an example of a method for manufacturing an elastic wave device according to the fifth embodiment.

[0105] As Figure 19 shown, a laminate and an IDT electrode 53 that form part of the wiring electrode 41 are dry-etched on the piezoelectric substrate 12. More specifically, a metal layer that becomes the adhesive layer 2, a metal layer 3X that becomes the low-resistance layer 3, and a metal layer that becomes the first barrier layer 44A are laminated on the piezoelectric substrate 12. Each of the above metal layers can be formed, for example, by vapor deposition or sputtering. Next, a resist pattern is formed on the metal layer that becomes the first barrier layer 44A. Next, dry etching is performed, and then the resist pattern is peeled off. Thus, a laminate and an IDT electrode 53 that form part of the wiring electrode 41 are formed. At the same time as the IDT electrode 53, each reflector is also formed.

[0106] Next, as Figure 20 (a) shows, a resist pattern 57 is formed so as to expose the side surface of the laminate that forms part of the wiring electrode 41. Next, the side surface of the metal layer 3X that becomes the low-resistance layer 3 is dry-etched. At this time, a gas that acts on the metal layer 3X that becomes the low-resistance layer 3 and hardly acts on the adhesive layer 2 and the first barrier layer 44A is used. More specifically, in the formation of the wiring electrode 41, a Cl-based gas is used as the gas for dry etching. However, the type of the gas for dry etching is not limited to the above.

[0107] Next, the resist pattern 57 is peeled off. Thus, as Figure 20 (b) shows, a low-resistance layer 3 is obtained in which the outer periphery 3a is located inside compared to the outer periphery of the first barrier layer 44A. Next, as Figure 20 (c) shows, a second barrier layer 44B is formed on the first barrier layer 44A by a peeling method, and the outermost layer 5 is formed on the second barrier layer 44B. Thus, the wiring electrode 41 of the fifth embodiment is obtained.

[0108] Here, when forming the outermost layer 5, the outer periphery 3a of the low-resistance layer 3 is located inside compared to the outer periphery of the first barrier layer 44A. Therefore, the metal for forming the outermost layer 5 surrounds the side surface 3b of the low-resistance layer 3. Therefore, alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be effectively suppressed. In addition, when the outermost layer 5 is heated and expands, before the metal constituting the outermost layer 5 reaches the first barrier layer 44A, the metal needs to move on the side surface of the second barrier layer 44B. Therefore, it is more difficult for the metal of the outermost layer 5 to reach the side surface 3b of the low-resistance layer 3, and alloying of the metal constituting the low-resistance layer 3 and the metal constituting the outermost layer 5 can be further suppressed.

[0109] On the other hand, in a plan view, when the outer periphery of the second barrier layer 44B overlaps with the outer periphery of the first barrier layer 44A, the area of the outermost layer 5 can also be increased. Thereby, the bonding area between the wiring electrode 41 and the bump can be increased. Therefore, the bonding force between the wiring electrode 41 and an external electrode or the like can be improved.

[0110] It should be noted that the second barrier layer 44B does not necessarily have to be provided, and the barrier layer 44 may be composed only of the first barrier layer 44A. However, the formation of the second barrier layer 44B and the formation of the outermost layer 5 can be performed without inserting a process such as resist pattern peeling. Therefore, the bonding force between the second barrier layer 44B and the outermost layer 5 can be more reliably improved, and the bonding force between the barrier layer 44 and the outermost layer 5 can be more reliably improved.

[0111] Symbol Explanation

[0112] 1... Wiring electrode

[0113] 1X... Stacked body

[0114] 1a... Bump pad portion

[0115] 2... Adhesive layer

[0116] 2X... Metal layer

[0117] 2a... Outer periphery

[0118] 2b... Side surface

[0119] 3... Low-resistance layer

[0120] 3X... Metal layer

[0121] 3a... Outer periphery

[0122] 3b... Side surface

[0123] 3c, 3d... First and second main surfaces

[0124] 4... Barrier layer

[0125] 4X... Metal layer

[0126] 4a... Outer periphery

[0127] 4b... Side surface

[0128] 5... Outermost layer

[0129] 5X... Metal layer

[0130] 5a... Outer periphery

[0131] 5b... Side surface

[0132] 6... Bump

[0133] 7A to 7C... Resist pattern

[0134] 10... Surface acoustic wave device

[0135] 12... Piezoelectric substrate

[0136] 13... IDT electrode

[0137] 13X... Metal film

[0138] 14, 15... Reflector

[0139] 16, 17... First and second bus bars

[0140] 18, 19... First and second electrode fingers

[0141] 27... Low-resistance layer

[0142] 27a... Outer periphery

[0143] 27b... Side surface

[0144] 28... Low-resistance layer

[0145] 28a... Outer periphery

[0146] 28b... Side surface

[0147] 28d... Second main surface

[0148] 29... Low-resistance layer

[0149] 29a... Outer periphery

[0150] 29b... Side surface

[0151] 32... Adhesive layer

[0152] 32a... Outer periphery

[0153] 32b... Side surface

[0154] 34... Barrier layer

[0155] 34a... Outer periphery

[0156] 34b... Side surface

[0157] 35... Outermost layer

[0158] 35a... Outer periphery

[0159] 35b... Side surface

[0160] 40... Surface acoustic wave device

[0161] 41... Wiring electrode

[0162] 44... Barrier layer

[0163] 44A, 44B... first and second barrier layers

[0164] 44a... outer perimeter

[0165] 53... IDT electrode

[0166] 57... resist pattern

[0167] B... metal

Claims

1. A wiring electrode is a wiring electrode provided on a substrate and formed by laminating multiple layers, and includes: An adhesive layer in contact with the substrate, The outermost layer indirectly provided on the adhesive layer, A low-resistance layer provided between the adhesive layer and the outermost layer, having a first main surface on the adhesive layer side and a second main surface opposed to the first main surface, and having the lowest resistance among the multiple layers, A barrier layer provided between the low-resistance layer and the outermost layer; The adhesive layer, the low-resistance layer, the barrier layer, and the outermost layer each have an outer periphery, In a plan view, the outer periphery of the second main surface of the low-resistance layer is located inside compared to the outer periphery of the barrier layer, and the outer periphery of the adhesive layer is located outside compared to the outer periphery of the low-resistance layer; The width of the central side in the thickness direction of the low-resistance layer is narrower than the width of the portion where the first main surface of the low-resistance layer contacts the layers other than the low-resistance layer among the multiple layers, and the width of the portion where the second main surface of the low-resistance layer contacts the layers other than the low-resistance layer among the multiple layers.

2. The wiring electrode according to claim 1, wherein, The outer periphery of the low-resistance layer is located inside compared to the outer periphery of the barrier layer.

3. The wiring electrode according to claim 1 or 2, wherein The outer periphery of the outermost layer is located inside compared to the outer periphery of the barrier layer.

4. The wiring electrode according to claim 1 or 2, wherein The outer periphery of the outermost layer is located inside compared to the outer periphery of the low-resistance layer.

5. The wiring electrode according to claim 1 or 2, wherein The outer periphery of the outermost layer is located outside compared to the outer periphery of the low-resistance layer.

6. The wiring electrode according to claim 1 or 2, wherein The outer periphery of the outermost layer and the outer periphery of the barrier layer are located inside compared to the outer periphery of the adhesive layer.

7. The wiring electrode according to claim 1 or 2, wherein, The low-resistance layer is made of Al or an alloy mainly composed of Al.

8. The wiring electrode according to claim 1 or 2, wherein The outermost layer is made of Au or an alloy mainly composed of Au.

9. The wiring electrode according to claim 1 or 2, wherein The adhesive layer is made of at least one metal selected from Ti, Ni, Cr, and alloys mainly composed of these metals.

10. The wiring electrode according to claim 1 or 2, wherein The side surface of the low-resistance layer has a curved surface shape.

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