An AI chip control method, electronic device and AI chip

Abstract

The present application is applicable to the field of computer technology, and provides an AI chip control method, an electronic device, and an AI chip. The method includes: generating register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, and the AI ​​chip is used to perform the task to be calculated; writing the register configuration information into the AI ​​chip so that the AI ​​chip performs calculations according to the register configuration information, which can simplify the operation process of the AI ​​chip, thereby improving the operation efficiency, and the control method for the AI ​​chip to perform calculations according to the register configuration information can solve the problem of difficulty in timing convergence of the AI ​​chip, thereby increasing the operating frequency; and enabling the AI ​​chip to switch to the next calculation immediately after completing the current calculation, thereby improving the operation performance of the AI ​​chip.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular, relates to an AI chip control method, an electronic device, and an AI chip. Background Art

[0002] As the capabilities of deep learning algorithms improve, they are increasingly used, which has led to the emergence of a large number of AI chips for hardware acceleration of deep learning algorithms. Current AI chips use an instruction set architecture and operate in an instruction control mode. The workflow includes operations such as instruction fetch, decoding, execution, and writing back to registers or memory.

[0003] However, controlling the operation of AI chips through instructions will make the operation process of AI chips complicated, affect computing efficiency, make it difficult for AI chip timing to converge, and restrict the operating frequency. Summary of the invention

[0004] The embodiments of the present application provide an AI chip control method, an electronic device, and an AI chip, which can solve the problems of complex AI chip operation process, limited computing efficiency, difficult AI chip timing convergence, and restricted operating frequency.

[0005] In a first aspect, an embodiment of the present application provides an AI chip control method, including:

[0006] Obtain parameter information of the task to be calculated and architectural parameter information of the AI ​​chip;

[0007] Generate register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, and the AI ​​chip is used to execute the task to be calculated;

[0008] The register configuration information is written into the AI ​​chip so that the AI ​​chip performs calculations according to the register configuration information.

[0009] Furthermore, the parameter information of the task to be calculated includes data information, algorithm information and an algorithm type corresponding to the algorithm information, and the architecture parameter information of the AI ​​chip includes cache unit information and computing unit information;

[0010] Generate register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, including:

[0011] Determine a cache task according to the data information and the cache unit information;

[0012] Determine the operation mode and data flow path of the AI ​​chip according to the algorithm type and the operation unit information, or determine the operation mode and data flow path of the AI ​​chip according to the data information, the algorithm type and the operation unit information;

[0013] Generate register configuration information based on input information and generated information, the input information includes parameter information of the task to be calculated and architecture parameter information of the AI ​​chip, and the generated information includes the cache task, the operation mode and the data flow path.

[0014] Furthermore, the data information includes data volume information and data type;

[0015] Determining a cache task according to the data information and the cache unit information includes:

[0016] Calculate the total data volume according to the data volume information;

[0017] Determine whether to allocate cache space according to the total data volume and the cache unit information.

[0018] Furthermore, the computing unit information includes computing parallelism and computing type;

[0019] Determining the operation mode and data flow path of the AI ​​chip according to the algorithm type and the operation unit information includes:

[0020] The operation mode and the data flow path are determined according to the algorithm type, the operation parallelism and the operation type.

[0021] Furthermore, the computing unit information includes computing parallelism and computing type;

[0022] Determining the operation mode and data flow path of the AI ​​chip according to the data information, the algorithm type, and the operation unit information includes:

[0023] The operation mode and the data flow path are determined according to the judgment result, the algorithm type, the operation parallelism and the operation type, and the judgment result is the result of judging whether to allocate the cache space of the cache unit.

[0024] Furthermore, the AI ​​chip includes at least one execution module;

[0025] Generate register configuration information based on input information and generated information, including:

[0026] Determine the input information and the generated information corresponding to each of the execution modules according to the operation mode and the data flow path;

[0027] The input information and the generated information are operated to obtain register configuration information corresponding to the execution module.

[0028] In a second aspect, an embodiment of the present application provides an AI chip control method, including:

[0029] The AI ​​chip includes at least one execution module, and the method includes:

[0030] Receive register configuration information from external devices;

[0031] Initializing each of the execution modules according to the register configuration information;

[0032] Acquire data to be processed, where the data to be processed is stored in an external storage device;

[0033] The initialized execution module performs operation on the data to be processed to obtain the operation result;

[0034] The calculation result is transmitted to the external device or the external storage device.

[0035] Furthermore, the execution module includes a cache unit and a calculation unit;

[0036] Initializing the data flow of each execution module according to the register configuration information, including:

[0037] Determine the addressing mode and the number of reads corresponding to each cache unit according to the register configuration information;

[0038] A data flow path for each computing unit is determined according to the register configuration information.

[0039] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements a method as described in any one of the first aspect or the second aspect.

[0040] In a fourth aspect, an embodiment of the present application provides an AI chip, comprising at least one execution module, which, when executed, implements the method as described in any one of the second aspects.

[0041] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0042] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0043] The embodiments of the present application generate register configuration information according to parameter information of the task to be calculated and architectural parameter information of the AI ​​chip, and the AI ​​chip is used to execute the task to be calculated; the register configuration information is written into the AI ​​chip so that the AI ​​chip performs calculations according to the register configuration information, which can simplify the operation process of the AI ​​chip, thereby improving the calculation efficiency, and the control method for the AI ​​chip to perform calculations according to the register configuration information can solve the problem of difficulty in timing convergence of the AI ​​chip, thereby increasing the operating frequency; and the AI ​​chip can immediately switch to the next calculation after completing the current calculation, thereby improving the operation performance of the AI ​​chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 It is a flowchart of an AI chip control method provided in one embodiment of the present application;

[0046] Figure 2 is a flowchart of an AI chip control method provided by another embodiment of the present application;

[0047] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0048] Figure 4 It is a schematic diagram of the structure of the AI ​​chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0050] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0051] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0052] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0053] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0054] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0055] The characteristics of current AI chips are high computing parallelism, high computing power, and simple control logic. Most AI chips use an instruction set-based architecture. The working process of AI chips with this architecture includes operations such as instruction fetching, decoding, execution, and writing back to registers or memories. Specifically, the AI ​​chip first reads instructions from the memory, then decodes the instructions through the logic circuit, analyzes the instructions to obtain the specific operations to be executed and the data to be processed, and then passes the data to be processed through the register device to the ALU (Arithmetic & logical Unit) or AI-specific computing unit for calculation, and finally writes the results of the calculation back to the register or memory.

[0056] However, because the instruction set-based architecture is derived from the CPU architecture, its original design intention is to ensure that the CPU is as versatile as possible and can complete any computing task. Therefore, the architecture focuses on the versatility of the control logic. This conflicts with the original design intention of the AI ​​chip, which is to provide high computing power, high parallelism, simple control logic, and the ability to undertake massive computing tasks. This makes the operation process of AI chips using the instruction set architecture complicated, affects computing efficiency, and makes it difficult for AI chips to converge in timing, and restricts the operating frequency.

[0057] Figure 1 1 is a flow chart of an AI chip control method provided in an embodiment of the present application. As an example but not a limitation, the method is applied to an electronic device. For example, the electronic device includes a host or a server.

[0058] like Figure 1 As shown, the method includes:

[0059] S101: Obtain parameter information of the task to be calculated and architecture parameter information of the AI ​​chip.

[0060] For example, the user inputs parameter information of the computing task that the AI ​​chip currently needs to run and the architecture parameter information of the AI ​​chip. The electronic device obtains the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip.

[0061] S102: Generate register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, and the AI ​​chip is used to execute the task to be calculated.

[0062] Specifically, based on the parameter information and architecture parameter information, register configuration information that can be parsed by the AI ​​chip is generated.

[0063] S103: Write the register configuration information into the AI ​​chip, so that the AI ​​chip performs calculations according to the register configuration information.

[0064] For example, the electronic device writes register configuration information to the AI ​​chip through the PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) bus. After receiving the register configuration information, the AI ​​chip parses it and directly performs operations based on the register configuration information, so that the AI ​​chip does not need to go through the steps of fetching instructions, decoding, and writing back to the register, thereby improving the computing efficiency of the AI ​​chip.

[0065] It should be noted that the register configuration information is generated by electronic devices and is separate from the AI ​​chip operation. Therefore, the register configuration information can be generated at any time and can also be entered into the AI ​​chip at any time. When the AI ​​chip completes the current computing task, the next computing task can be executed immediately, which can improve computing efficiency.

[0066] This embodiment generates register configuration information according to parameter information of the task to be calculated and architectural parameter information of the AI ​​chip, and the AI ​​chip is used to execute the task to be calculated; the register configuration information is written into the AI ​​chip so that the AI ​​chip performs calculations according to the register configuration information, which can simplify the operation process of the AI ​​chip, thereby improving the calculation efficiency, and the control method for the AI ​​chip to perform calculations according to the register configuration information can solve the problem of difficulty in timing convergence of the AI ​​chip, thereby increasing the operating frequency; and the AI ​​chip can immediately switch to the next calculation after completing the current calculation, thereby improving the operation performance of the AI ​​chip.

[0067] In another embodiment, the parameter information of the task to be calculated includes data information, algorithm information and the algorithm type corresponding to the algorithm information, and the architecture parameter information of the AI ​​chip includes cache unit information and computing unit information.

[0068] The data information includes data volume information, data type information, etc. The data volume information includes data volume information of input data and data volume information of output data. For example, the data volume information includes width, height, and number of channels.

[0069] The cache unit information includes the capacity information of the on-chip cache unit of the AI ​​chip, and the computing unit information includes the computing parallelism of the computing unit of the AI ​​chip, the computing type supported by the AI ​​chip, etc. Accordingly, the AI ​​chip includes at least one execution module, and the execution module includes a cache unit and a computing unit.

[0070] It should be noted that the parameter information will add type information according to the algorithm type, and the type information is pre-correlated with the corresponding algorithm type. For example, if the algorithm type includes convolution, the parameter information will add convolution kernel information, convolution window moving step, and padding information accordingly.

[0071] Furthermore, the data volume information of the input data will be added with size information according to the data type. For example, if the data type includes coefficient and shortcut, the data volume information of the input data will be added with the data volume information of the coefficient and the data volume information of the shortcut.

[0072] Generate register configuration information based on the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, including:

[0073] First, the cache task is determined according to the data information and the cache unit information.

[0074] Specifically, first, the total data volume is calculated based on the data information.

[0075] According to the data volume information of each group in the data information, the corresponding total data volume is calculated. For example, according to the width, height, and number of channels of each group of input data, the corresponding total data volume is calculated. According to the width, height, and number of channels of each group of output data, the corresponding total data volume is calculated.

[0076] Second, determine whether to allocate cache space based on the total data volume and cache unit information.

[0077] The total amount of input data is compared with the capacity information of the on-chip cache unit. If the value of the capacity information is greater than the value of the total amount of data, it is determined that cache space is allocated. The cache space is the input cache space, which is used to store the data to be processed corresponding to the input data and obtain the corresponding address. If the value of the capacity information is less than the value of the total amount of data, it is determined that cache space is not allocated. Accordingly, when the AI ​​chip performs calculations, it directly performs calculations after obtaining the data to be processed.

[0078] The total amount of output data is compared with the capacity information of the on-chip cache unit. If the value of the capacity information is greater than the value of the total amount of data, it is determined that cache space is allocated. The cache space is the output cache space, which is used to store the amount of output data. If the value of the capacity information is less than the value of the total amount of data, it is determined that cache space is not allocated. Accordingly, after the AI ​​chip performs the calculation, the calculation result is directly output to the electronic device.

[0079] Each set of input data and output data needs to be judged to determine whether cache space needs to be allocated.

[0080] Next, the operation mode and data flow path of the AI ​​chip are determined based on the algorithm type and operation unit information;

[0081] Specifically, the operation mode and data flow path are determined according to the algorithm type, operation parallelism and operation type. Among them, when designing the AI ​​chip, which specific algorithm types have been designed, and the operation mode and data flow path can be determined based on the operation parallelism and operation type. When these algorithm types are obtained, the operation mode and data flow path can be determined based on the operation parallelism and operation type. For example, the A and B algorithm types are types of operation modes and data flow paths that can be determined based on the operation parallelism and operation type. The task to be calculated includes the A and B algorithm types, and according to the operation parallelism and operation type, it is obtained that the AI ​​chip supports simultaneous operation of A and B, then the corresponding operation mode is parallel operation of A and B, and the first computing unit is allocated for operation A, and the second computing unit is allocated for operation B. And the corresponding data flow path is that the first computing unit obtains data from the storage space storing the data to be processed, and after the first computing unit calculates A, the obtained operation result is output to the second computing unit, and after the second computing unit calculates B, the obtained operation result is output to the electronic device, thereby forming a connection relationship.

[0082] Or, determine the operation mode and data flow path of the AI ​​chip based on data information, algorithm type and operation unit information;

[0083] Specifically, the operation mode and data flow path are determined according to the judgment result, algorithm type, operation parallelism and operation type. Among them, the judgment result is the result of judging whether to allocate the cache space of the cache unit. When designing the AI ​​chip, specific algorithm types have been designed, and the operation mode and data flow path can be determined based on the judgment result, operation parallelism and operation type. When these algorithm types are obtained, the operation mode and data flow path can be determined according to the judgment result, operation parallelism and operation type. For example, the C, D, and E algorithm types are the types of operation modes and data flow paths determined according to the judgment result, operation parallelism and operation type. The tasks to be calculated include C, D, and E algorithm types. Based on the operation parallelism and operation type, it is obtained that the AI ​​chip supports simultaneous operation of C, D, and E. On this basis, the operation mode and data flow path are determined according to the judgment result.

[0084] If the judgment result is to allocate cache space, the operation mode is to calculate C, D, and E in sequence, and the first calculation unit is allocated to calculate C, the second calculation unit is allocated to calculate D, and the third calculation unit is allocated to calculate E. The corresponding data flow path is that the first calculation unit obtains data from the cache space storing the data to be processed, that is, obtains data from the input cache space, and after the first calculation unit calculates C, the obtained calculation result is output to the output cache space, the second calculation unit obtains the result from the output cache space, calculates D, and outputs the obtained calculation result to the output cache space, and the third calculation unit obtains the result from the second cache unit, calculates E, and outputs the obtained calculation result to the electronic device, thereby forming a connection relationship.

[0085] If the judgment result is that the cache space is not allocated, the operation mode is parallel calculation C, D, E, and the first calculation unit is allocated for calculation C, the second calculation unit is allocated for calculation D, and the third calculation unit is allocated for calculation E. The corresponding operation mode is parallel calculation C, D, E, and the first calculation unit is allocated for calculation C, the second calculation unit is allocated for calculation D, and the third calculation unit is allocated for calculation E. The corresponding data flow path is that the first calculation unit obtains data from the cache space storing the data to be processed, and after the first calculation unit calculates C, the obtained calculation result is output to the second calculation unit, the second calculation unit calculates D, and the obtained calculation result is output to the third calculation unit, and the third calculation unit calculates E and outputs the obtained calculation result to the electronic device, thereby forming a connection relationship.

[0086] Next, register configuration information is generated based on the input information and generated information. The input information includes parameter information of the task to be calculated and architectural parameter information of the AI ​​chip. The generated information includes cache tasks, operation modes, and data flow paths.

[0087] Specifically, according to the operation mode and the data flow path, the input information and the generated information corresponding to each execution module are determined.

[0088] The corresponding input information and generated information are operated to obtain the register configuration information of the corresponding execution module. The operation is performed according to the corresponding formula, which is determined when the AI ​​chip is designed.

[0089] It should be noted that the generated register configuration information can be modified directly, that is, when the demand changes, the generated register configuration information can be directly modified, which can facilitate the operation and testing of the AI ​​chip, and the generation of the register configuration information is implemented in the electronic device and can be generated at any time without affecting the operation and testing of the AI ​​chip.

[0090] Figure 2 1 is a flow chart of an AI chip control method provided in an embodiment of the present application. As an example but not a limitation, the method is applied to an AI chip, wherein the AI ​​chip includes at least one execution module.

[0091] like Figure 2 As shown, the method includes:

[0092] S201: Receive register configuration information from an external device.

[0093] S202: Initialize each execution module according to the register configuration information.

[0094] Specifically, the AI ​​chip allocates register configuration information to each execution module based on an address that is determined when the AI ​​chip is designed.

[0095] S203: Acquire the data to be processed, and store the data to be processed in an external storage device.

[0096] When the cache unit on the AI ​​chip cannot store the data to be processed, it needs to be stored in an external storage device. For example, the external storage device is DDR (double data rate synchronous dynamic random access memory).

[0097] S204: The initialized execution module performs operations on the data to be processed to obtain operation results.

[0098] Specifically, the initialized execution module operates on the data to be processed according to the data stream.

[0099] S205: Transmitting the calculation result to an external device or an external storage device.

[0100] The external device is an electronic device, for example, a host or a server.

[0101] Specifically, the calculation result is transmitted to the external device according to the register configuration information, for example, transmitted to the external device via the PCIE bus to complete the entire processing flow of the calculation task.

[0102] Or it can be transmitted to an external storage device according to register configuration information, so that the operation result serves as the data to be processed by the next task.

[0103] This embodiment receives register configuration information from an external device; initializes each execution module according to the register configuration information; obtains data to be processed, and stores the data to be processed in an external storage device; the initialized execution module performs operations on the data to be processed to obtain operation results; and transmits the operation results to an external device or an external storage device. This can simplify the operation of the AI ​​chip, thereby improving the operation efficiency. The AI ​​chip performs operations according to the register configuration information, which can solve the problem of difficult timing convergence of the AI ​​chip, thereby increasing the operating frequency; and enables the AI ​​chip to immediately switch to the next operation after completing the current operation, thereby improving the operation performance of the AI ​​chip.

[0104] In another embodiment, the execution module includes a cache unit and a calculation unit;

[0105] Initialize each execution module according to the register configuration information, including:

[0106] First, the addressing mode and the number of reads corresponding to each cache unit are determined according to the register configuration information.

[0107] Specifically, the cache unit determines the addressing mode corresponding to the space for storing the data to be processed and the computing unit to interact with it according to the register configuration information, so as to interact with the computing unit for data, and determines the number of times to read the cache unit.

[0108] Correspondingly, during operation, the cache unit reads the data to be processed according to the addressing mode and then outputs it to the corresponding calculation unit.

[0109] According to the register configuration information, the data flow path of each computing unit is determined.

[0110] Specifically, the computing unit determines the data flow path and operation mode according to the register configuration information, thereby determining the units through which the data to be processed and the intermediate data generated during the operation pass in the AI ​​chip, that is, determining which unit the data is input from and which unit the data is output to.

[0111] Correspondingly, during operation, the computing unit receives data from the corresponding unit, obtains the operation result, and then outputs the operation result to the corresponding unit.

[0112] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0113] Figure 3 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Figure 3 As shown, the electronic device 3 of this embodiment includes: at least one processor 30 ( Figure 3 Only one is shown), a memory 31, and a computer program 32 stored in the memory 31 and executable on the at least one processor 30, wherein the processor 30 implements the steps of any method embodiment described above applied to a host or a server when executing the computer program 32.

[0114] The electronic device 3 may be a computing device such as a host or a server. The electronic device 3 may include, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will appreciate that Figure 3 It is only an example of the electronic device 3 and does not constitute a limitation on the electronic device 3. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0115] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0116] In some embodiments, the memory 31 may be an internal storage unit of the electronic device 3, such as a hard disk or memory of the electronic device 3. In other embodiments, the memory 31 may also be an external storage device of the electronic device 3, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 3. Further, the memory 31 may also include both an internal storage unit of the electronic device 3 and an external storage device. The memory 31 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program, etc. The memory 31 may also be used to temporarily store data that has been output or is to be output.

[0117] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0118] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0119] Figure 4 Schematic diagram of the structure of the AI ​​chip provided in the embodiment of the present application. Figure 4 As shown, the AI ​​chip 4 of this embodiment includes at least one computing unit 40, an input cache space 41 composed of cache units, and an output cache space 42 composed of cache units.

[0120] When the computing unit 40 is executed, the steps in any method embodiment of the computing unit of the AI ​​chip are implemented. When the cache unit is executed, the steps in any method embodiment of the cache unit of the AI ​​chip are implemented.

[0121] The AI ​​chip 4 may include, but is not limited to, a computing unit 40, an input buffer space 41 and an output buffer space 42. Those skilled in the art will appreciate that Figure 4 It is only an example of the electronic device 4 and does not constitute a limitation on the electronic device 4. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0122] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / electronic device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0123] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0124] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0125] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0126] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An AI chip control method, It is characterized in that include: Obtain parameter information of the task to be calculated and architecture parameter information of the AI ​​chip, wherein the parameter information of the task to be calculated includes data information, algorithm information, and an algorithm type corresponding to the algorithm information, and the architecture parameter information of the AI ​​chip includes cache unit information and computing unit information; Generate register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip, and the AI ​​chip is used to execute the task to be calculated; Writing the register configuration information into the AI ​​chip so that the AI ​​chip performs calculations according to the register configuration information; Among them, generating register configuration information according to the parameter information of the task to be calculated and the architecture parameter information of the AI ​​chip includes: Calculate the total data volume based on the data volume information; Determine whether to allocate cache space according to the total data volume and the cache unit information, wherein the data information includes the data volume information and the data type; Determine the operation mode and data flow path of the AI ​​chip according to the algorithm type, operation parallelism and operation type; Or, determining the operation mode and data flow path of the AI ​​chip according to the data information, the algorithm type, the operation parallelism and the operation type; Register configuration information is generated according to input information and generated information, wherein the input information includes parameter information of the task to be calculated and architecture parameter information of the AI ​​chip, and the generated information includes cache tasks, the operation mode and the data flow path.

2. The method according to claim 1, It is characterized in that Determining the operation mode and data flow path of the AI ​​chip according to the data information, the algorithm type, the operation parallelism, and the operation type, including: The operation mode and the data flow path are determined according to the judgment result, the algorithm type, the operation parallelism and the operation type, and the judgment result is the result of judging whether to allocate the cache space of the cache unit.

3. The method according to claim 1, It is characterized in that The AI ​​chip includes at least one execution module; Generate register configuration information based on input information and generated information, including: Determine the input information and the generated information corresponding to each of the execution modules according to the operation mode and the data flow path; The input information and the generated information are operated to obtain register configuration information corresponding to the execution module.

4. An AI chip control method, It is characterized in that The AI ​​chip includes at least one execution module, and the method includes: Receiving register configuration information from an external device, wherein the register configuration information is obtained by the method according to any one of claims 1 to 3; Initializing each of the execution modules according to the register configuration information; Acquire data to be processed, where the data to be processed is stored in an external storage device; The initialized execution module performs operation on the data to be processed to obtain the operation result; The calculation result is transmitted to the external device or the external storage device.

5. The method according to claim 4, It is characterized in that The execution module includes a cache unit and a calculation unit; Initializing the data flow of each execution module according to the register configuration information, including: Determine the addressing mode and the number of reads corresponding to each cache unit according to the register configuration information; A data flow path for each computing unit is determined according to the register configuration information.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the computer program, the method according to any one of claims 1 to 3 is implemented.

7. An AI chip, It is characterized in that The method comprises at least one execution module, and when the execution module is executed, the method according to any one of claims 4 to 5 is implemented.

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