Methods, apparatus, devices, and readable storage media for resetting

Abstract

The present disclosure provides a method, device, equipment and readable storage medium for reset, relates to the technical field of data processing, and particularly relates to the field of chips and information flow. The specific implementation scheme is as follows: in response to receiving a message related to an exception of a functional module of a system on chip, adjusting an indication value in a first register of the functional module to prevent the functional module from making new access to a network on chip of the system on chip; in response to the number of access times to a second register of the functional module being less than or equal to a threshold number of times, obtaining a count value in the second register, the count value indicating the number of uncompleted accesses to the network on chip in the functional module; and in response to the count value indicating that there is no uncompleted access to the network on chip in the functional module, resetting the functional module. Through the method, the cost of exception processing can be reduced, and the reset does not affect other modules, has good portability, and reduces hardware overhead.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a method, device, apparatus and readable storage medium for reset in the field of chip and information flow. BACKGROUND

[0002] With the continuous development of semiconductor technology, more and more logic is integrated in a System on Chip (SoC) chip, and the structure of the SoC chip is more and more complex. A typical SoC chip often contains a microprocessor, a communication interface, an on-chip memory or an off-chip memory interface, and a series of customized Intellectual Property (IP) cores, etc. In the running process of such a huge and complex system, the occurrence of an exception is inevitable. After the occurrence of an exception, the system may be in a state where it cannot continue to work correctly. Therefore, there are many problems to be handled in the process of resetting the SoC. SUMMARY

[0003] The present disclosure provides a method, device, apparatus and readable storage medium for reset.

[0004] According to a first aspect of the present disclosure, a method for reset is provided. The method comprises, in response to receiving a message related to an exception of a functional module of a System on Chip (SoC), adjusting an indication value in a first register of the functional module for preventing the functional module from making new accesses to a Network on Chip (NoC) of the SoC; in response to a number of accesses to a second register of the functional module being less than a threshold number, obtaining a count value in the second register, the count value indicating a number of uncompleted accesses to the NoC in the functional module; and in response to the count value indicating that there is no uncompleted access to the NoC in the functional module, resetting the functional module.

[0005] According to a second aspect of the present disclosure, an apparatus for reset is provided. The apparatus comprises a scheduling module configured to, in response to receiving a message related to an exception of a functional module of a System on Chip (SoC), adjust an indication value in a first register of the functional module for preventing the functional module from making new accesses to a Network on Chip (NoC) of the SoC; an obtaining module configured to, in response to a number of accesses to a second register of the functional module being less than a threshold number, obtain a count value in the second register, the count value indicating a number of uncompleted accesses to the NoC in the functional module; and a functional module resetting module configured to, in response to the count value indicating that there is no uncompleted access to the NoC in the functional module, reset the functional module.

[0006] According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises at least one processor; a function module comprising at least a first register and a second register, and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to the first aspect of the present disclosure.

[0007] According to a fourth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions being used to cause a computer to perform the method according to the first aspect of the present disclosure.

[0008] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method according to the first aspect of the present disclosure.

[0009] It should be understood that the contents described in this part are not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings are used to better understand the present scheme, and do not limit the present disclosure. Among them:

[0011] Figure 1 A schematic diagram of an environment 100 in which a plurality of embodiments of the present disclosure can be implemented is shown;

[0012] Figure 2 A flowchart of a method 200 for resetting according to some embodiments of the present disclosure is shown;

[0013] Figure 3 A schematic diagram of a system 300 for resetting according to some embodiments of the present disclosure is shown;

[0014] Figure 4 A schematic diagram of an example 400 of a function module according to some embodiments of the present disclosure is shown;

[0015] Figure 5 A schematic diagram of a method 500 for resetting according to some embodiments of the present disclosure is shown;

[0016] Figure 6 A block diagram of an apparatus 600 for resetting according to some embodiments of the present disclosure is shown; and

[0017] Figure 7 A block diagram of a device 700 capable of implementing a plurality of embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are presented for the purpose of illustration and description. It is to be understood that the embodiments described herein are merely exemplary and that various changes and modifications can be made thereto without departing from the scope and spirit of the present disclosure. As such, it is to be understood that the embodiments described herein are merely exemplary and that various changes and modifications can be made thereto without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0019] In the description of embodiments of the present disclosure, the term "includes" and its derivatives mean "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" or "the embodiment" means "at least one embodiment". The terms "a first", "a second", etc. can refer to different or same objects. Other explicit or implicit definitions can also be included below.

[0020] As mentioned before, during the operation of a large and complex system on chip, the occurrence of exceptions is inevitable. After the occurrence of an exception, the system can be in a state where it cannot continue to work correctly. Therefore, resetting the system is a common exception handling method. The simplest and safest way of handling is to globally reset the chip, and after global reset, all modules can enter a safe and controllable initialization state. However, exceptions often occur in a local part of the system, and global reset will reset the remaining normally working modules, which is costly. Since the SoC system often uses a network on chip (NoC) for on-chip interconnection, if the reset module and the NoC have unfinished transactions during local reset, functional errors or exceptions may occur again after reset, or even the NoC may be hung up and affect the part that has not appeared an exception.

[0021] A traditional solution is to first locally reset the processor core when an exception occurs, then read out the register information of the exception site through the processor core and write it to the memory that is not affected by the reset, and then use global soft reset and write the register information back. However, its main purpose is to recover the exception site after reset to facilitate the investigation of the cause of the exception, so it consumes a lot of time in saving and restoring the exception site, and still needs global reset at the end to ensure the correctness of the system.

[0022] Another traditional solution is to use a multi-level reset system, determine the level that needs to be reset according to the exception detection signal of each level, and use an independent reset chip off-chip. However, its main purpose is to ensure the reliability and anti-interference ability of chip reset in harsh environments such as strong electromagnetism, and the granularity of local reset is still coarse, and a reset chip off-chip is needed. This results in a large hardware overhead.

[0023] To at least solve the above problems, according to an embodiment of the present disclosure, an improved solution for resetting is proposed. Wherein, if the system-on-chip determines that a message related to an exception of a functional module of the system-on-chip is received, the system-on-chip adjusts an indication value in a first register of the functional module for preventing the functional module from making a new access to a network-on-chip of the system-on-chip. Then, it is determined whether the number of accesses to a second register of the functional module is less than a threshold number, and if so, a count value in the second register is obtained, the count value indicating the number of uncompleted accesses to the network-on-chip in the functional module. If it is determined that the count value indicates that there is no uncompleted access to the network-on-chip in the functional module, the functional module is reset. By the above method, the cost of exception handling can be reduced, and the influence on other modules during resetting can be avoided, which has good portability and reduces hardware overhead.

[0024] Figure 1 A schematic diagram of an environment 100 in which a plurality of embodiments of the present disclosure can be implemented is shown. The example environment 100 includes a system-on-chip 102.

[0025] The system-on-chip includes a processor 104 for managing the system-on-chip 102, including handling interrupts, exceptions, and register read / write, etc. The processor 104 can be a microprocessor integrated in the system-on-chip. Figure 1 The location of the processor 104 in the system-on-chip is only an example, and is not a specific limitation of the present disclosure. The functions of the processor 104 can also be implemented by a central processing unit of a host.

[0026] The system-on-chip 102 further includes functional modules 106-1, 106-2, …, 106-N, where N is a positive integer, and for ease of description, collectively referred to as functional modules 106. In the present disclosure, the functional modules 106 are responsible for completing tasks issued by the processor. The original data for the task comes from the memory, and the result data is written to the memory. In some embodiments, Figure 1 The N functional modules 106 in the system-on-chip are homogeneous modules that implement the same function. In some embodiments, Figure 1 The N functional modules 106 in the system-on-chip are heterogeneous modules responsible for different functions. The above examples are only used to describe the present disclosure, and are not specific limitations of the present disclosure.

[0027] The processor 104 is configured to receive an exception message from the functional module 106. After receiving the exception message from the functional module 106, the processor 104 manages at least two designated registers in the functional module 106 to determine whether to reset only the functional module 106 or reset the entire system-on-chip for the exception.

[0028] At least two registers are configured in functional module 106, wherein the first register is configured to determine whether to block functional module 106 from initiating new access to on-chip network 108. Normally, the default value of the first register allows functional module 106 to initiate new access to the on-chip network. The second register is configured to store the number of incomplete accesses to on-chip network 108 currently being performed by functional module 106.

[0029] After receiving a message indicating an anomaly in functional module 106, processor 104 first sets the first register of functional module 106 to a preset value that blocks the functional module from initiating new accesses to the on-chip network. Then, it accesses the second register fewer than a predetermined number of times, checking each time to ensure the number of incomplete accesses stored in the second register has reached zero. If the number of incomplete accesses reaches zero within the predetermined number of accesses, it indicates that isolation of functional module 106 has been completed. Therefore, only the functional module needs to be reset. Thus, when an anomaly occurs on the SoC, if the anomaly only affects a local module, only the faulty module needs to be reset, while the remaining modules can continue to operate normally, and the scheduling module can continue to send tasks to the other functional modules.

[0030] If the number of incomplete accesses stored in the second register does not become 0 within a predetermined number of accesses, it indicates that the corresponding data processing result cannot be received on the on-chip network 108. Therefore, a global reset is performed on the on-chip system.

[0031] The above method can reduce the cost of exception handling and avoid affecting other modules during reset, thus having good portability and reducing hardware overhead.

[0032] The above combination Figure 1 An environment 100 in which various embodiments of this disclosure can be implemented is described below. (The following is in conjunction with...) Figure 2 A flowchart describing a method 200 for resetting according to some embodiments of the present disclosure. Figure 2 Method 200 in the middle can be derived from Figure 1 It can be executed by the system-on-a-chip 102 or any suitable computing device.

[0033] At box 202, it is determined whether a message related to an exception of a functional module of the on-chip system has been received. If a message related to an exception of a functional module of the on-chip system is received, at box 204, the indicator value in the first register of the functional module is adjusted to prevent the functional module from making new accesses to the on-chip network of the on-chip system. For example, as Figure 1As shown, upon receiving the exception message from the functional module 106, the processor 104 of the system-on-chip 102 sets the value of the first register in the functional module 106 to a predetermined value for preventing the functional module from making new accesses to the on-chip network of the system-on-chip.

[0034] In some embodiments, the information related to the exception is obtained from a status register of the functional module 106, which is different from the first register for determining whether to prevent the functional module from making new accesses to the on-chip network of the system-on-chip and the second register for storing the number of outstanding accesses to the on-chip network in the functional module. In this way, the error information can be quickly obtained and the cause of the error can be understood.

[0035] At block 206, it is determined whether the number of accesses to the second register of the functional module is less than a threshold number of accesses. If the number of accesses to the second register of the functional module is less than the threshold number of accesses, at block 208, a count value in the second register is obtained, the count value indicating the number of outstanding accesses to the on-chip network in the functional module. The count value in the second register is obtained within a predetermined number of accesses to determine whether there is an outstanding access to the on-chip network in the functional module.

[0036] In some embodiments, upon receiving the exception message from the functional module, the system-on-chip 102 sets a counter for counting the number of accesses to the second register and sets its initial value to 0. It is then determined whether the number of accesses is the threshold number of accesses. If not, the count value of the second register is obtained and it is then determined whether the count value indicates that there is no outstanding access to the on-chip network in the functional module.

[0037] In some embodiments, if the number of accesses is equal to the threshold number of accesses, the system-on-chip is reset. This indicates that there is an outstanding access to the on-chip network in the functional module after multiple accesses to the second register, which indicates that there is a problem with the data transfer and management of the on-chip network, and thus a global reset is performed. In this way, it can be quickly determined whether to perform a global reset of the system.

[0038] At block 210, it is determined whether the count value indicates that there is no outstanding access to the on-chip network in the functional module. If the count value indicates that there is no outstanding access to the on-chip network in the functional module, at block 212, the functional module is reset.

[0039] In some embodiments, the system-on-chip 102 compares the count value in the second register with a threshold count value. If it is determined that the count value is the same as the threshold count value, it is determined that there is no outstanding access to the on-chip network in the functional module. Alternatively or additionally, the threshold count value is 0. In this way, it can be quickly determined whether there is an outstanding access.

[0040] In some embodiments, if it is determined that the count value is not the same as the threshold count value, it is determined that there is an unfinished access to the network-on-chip in the function module. At this time, the number of accesses is incremented. Then, after a predetermined period of time, it is re-determined whether there is an unfinished access to the network-on-chip in the function module based on the incremented number of accesses and the count value in the second register is re-acquired. In this way, it can be ensured that the decision to reset is made within an appropriate time range.

[0041] In some embodiments, a task is sent to the reset function module. In this way, the task can be quickly processed.

[0042] By this method, the cost of exception handling can be reduced, and the influence on other modules when resetting can be avoided, which has good portability and reduces hardware overhead.

[0043] The above conclusions Figure 2 A flowchart of a method 200 for resetting according to some embodiments of the present disclosure is described. The method 200 for resetting according to some embodiments of the present disclosure is described below in conjunction with Figure 3 A schematic diagram of a system 300 for resetting according to some embodiments of the present disclosure is described below in conjunction with the method 200.

[0044] As Figure 3 shown, the system includes a processor 302, a system control module 304, a scheduling module 306. The system also includes function modules 308-1, 308-2, …, 308-N, where N is a positive integer, and for the convenience of description, collectively referred to as function modules 308.

[0045] In this system, the processor 302 is responsible for the control of the entire SoC, including processing interrupts, exceptions, register read / write, etc. The processor 302 can be a central processor on the host side, or a microprocessor integrated on the chip, which is only an example and not a specific limitation of the present disclosure.

[0046] The system control module 304 is responsible for the control logic related to the SoC system, such as issuing a reset signal to the function module 308, etc. The processor 302 can control the behavior of the function module 308 through register configuration.

[0047] The scheduling module 306 is responsible for the delivery of tasks and the forwarding of interrupts and exceptions. The scheduling module 306 can deliver the tasks issued by the processor 302 to the function module 308 that can be used at present, or can forward the interrupts and exceptions returned by the function module 308 to the processor 302.

[0048] The function module 308 is responsible for completing the task issued by the processor. The original data is from the memory 312, and the result data is written to the memory 312. The N function modules in the figure can be heterogeneous modules responsible for different functions, which are only examples and not specific limitations of the present disclosure.

[0049] The network on chip 310 is responsible for data interaction between the function module 308 and the memory 312. The memory 312 is used for data access. The memory 312 can be an on-chip memory or an off-chip memory.

[0050] The above conclusion and Figure 3 The schematic diagram of the system 300 for reset according to some embodiments of the present disclosure is described. The schematic diagram of the example 400 of the function module according to some embodiments of the present disclosure is described below in combination with Figure 4

[0051] As Figure 4 shown, the clock and reset unit 402 of the function module 404 generates an internal clock and reset signal through an external clock and reset signal 402, and ensures that the internal reset signal meets the timing requirements under the internal clock. The external clock signal can come from the clock generation component of the system on chip, and the reset signal comes from the processor.

[0052] The register unit 408 is responsible for managing the registers of the function module, and performs exception throwing when the function module detects an exception. The system control module on the system on chip can perform register read and write operations on the register unit 408. The register unit 408 at least includes a readable and writable register 1 for blocking the access of the direct memory access unit 410 to the NoC, and a readable register 2 for obtaining the number of current and NoC incomplete transactions of the direct memory access unit 410. Among them, the default value of the register 1 is not to block the direct memory access unit 410, and the register 1 does not need to be configured again after local reset. Therefore, the register unit 408 can be used to transmit register read and write data and exception signals 414.

[0053] The direct memory access unit 410 is responsible for transmitting input data or output data 416 for the data processing unit 412, and the direct memory access unit 410 can determine whether to block the access to the NoC according to the register 1 configuration value, and feed back the number of current and NoC incomplete transactions to the register 2. The data processing unit 412 is responsible for the main functional logic of the function module and processes data.

[0054] The above conclusion and Figure 4 The schematic diagram of the example 400 of the function module according to some embodiments of the present disclosure is described. The schematic diagram of the method 500 for reset according to some embodiments of the present disclosure is described below in combination with Figure 5 ​​

[0055] As Figure 5 shown, at block 502, the function module M (M<=N) detects an internal exception. At block 504, the function module M reports the exception to the processor through the scheduling module. Specifically, the function module M reports the exception to the scheduling module, and the scheduling module forwards the exception signal to the processor. At block 506, the processor reads the register of the function module M to obtain the exception field information.

[0056] At block 508, the processor writes the register 1 of the function module M to block its access to the system on a chip. Specifically, the processor performs a write operation on the register 1 of the function module M to configure the function module M to no longer initiate an access to the NoC. At block 510, the processor sets a counter and sets 0 to count the number of accesses to the register 2.

[0057] At block 512, the processor determines whether the value of the counter reaches a preset value. If yes, it is determined that the timeout, indicating that the request that has not been completed by the direct memory access unit cannot be completed due to the current possible abnormal situation of the common resource such as the NoC or the memory, and only a global reset can be performed at block 516. If no, it proceeds to block 514. At block 514, the processor reads the register 2 of the function module M, and at block 518, it determines whether the value of the register 2 is 0. If yes, it is considered that the isolation of the function module M and the NoC has been completed, and it proceeds to block 522; if no, at block 520, the value of the counter is incremented by 1, and after waiting for a certain time, it proceeds to block 512. At block 522, the processor sends a reset signal to the function module M through the system control module, and the function module M returns to the normal state. At block 524, the processor re-sends the task to the function module M through the scheduling module.

[0058] By this method, the cost of exception handling can be reduced, and the influence on other modules during reset can be avoided, which has good portability and reduces the hardware overhead.

[0059] Figure 6 A schematic block diagram of an apparatus 600 for reset is shown according to an embodiment of the present disclosure. As Figure 6 shown, the apparatus 600 includes a scheduling module 602 configured to, in response to receiving a message related to an exception of a function module of a system on a chip, adjust an indication value in a first register of the function module for preventing the function module from making a new access to a network on a chip of the system on a chip; an obtaining module 604 configured to, in response to a number of accesses to a second register of the function module being less than a threshold number of times, obtain a count value in the second register, the count value indicating a number of accesses to the network on a chip that are not completed in the function module; and a function module reset module 606 configured to, in response to the count value indicating that there is no access to the network on a chip that is not completed in the function module, reset the function module.

[0060] In some embodiments, the apparatus 600 further includes a system reset module configured to reset the system on chip in response to the access number being equal to the threshold number.

[0061] In some embodiments, the function module reset module 606 includes a comparison module configured to compare the count value with a threshold count value, a first outstanding access determination module configured to determine that there is no outstanding access to the network on chip in the function module in response to the count value being the same as the threshold count value.

[0062] In some embodiments, the apparatus 600 further includes a first outstanding access determination module configured to determine that there is outstanding access to the network on chip in the function module in response to the count value being different from the threshold count value, an increment module configured to increment the access number, and a re-determination module configured to determine whether there is outstanding access to the network on chip in the function module based on the incremented access number and the re-acquired count value after a predetermined time period.

[0063] In some embodiments, the apparatus 600 further includes an exception information acquisition module configured to acquire information related to the exception from a state register of the function module, the state register being different from the first register and the second register.

[0064] In some embodiments, the apparatus 600 further includes a sending module configured to send a task to the reset function module.

[0065] In the technical solutions of the present disclosure, the acquisition, storage and application of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0066] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium and a computer program product.

[0067] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The example electronic device 700 can be used to implement Figure 1The system-on-a-chip 102 is described herein. Electronic devices are intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0068] like Figure 7 As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 702 or a computer program loaded from storage unit 708 into random access memory (RAM) 703. RAM 703 may also store various programs and data required for the operation of device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0069] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of monitors, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0070] The computing unit 701 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, and the like. The computing unit 701 performs various methods and processes described above, such as the methods 200 and 500. For example, in some embodiments, the methods 200 and 500 can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, portions or all of the computer program can be loaded and / or installed onto the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded onto the RAM 703 and executed by the computing unit 701, one or more steps of the methods 200 and 500 described above can be performed. Alternatively, in other embodiments, the computing unit 701 can be configured to perform the methods 200 and 500 by other any suitable means, such as by means of firmware.

[0071] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0072] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a function / operation specified in the flowchart and / or block diagram. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, and partially on a remote machine or a server.

[0073] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0074] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0075] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0076] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0077] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps described in the present disclosure can be performed in parallel, in series, or in a different order, without limitation herein, so long as the desired results of the technology described in the present disclosure are achieved.

[0078] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and scope of the disclosure. Any further modifications, equivalents, and / or alterations of the specific embodiments described herein are included in the scope of the disclosure.

Claims

1. A method for reset, comprising: adjusting, in response to receiving a message related to an exception of a functional module of a system-on-chip, an indication value in a first register of the functional module for preventing the functional module from new accesses to a network-on-chip of the system-on-chip; obtaining, in response to a number of accesses to a second register of the functional module being less than a threshold number, a count value within the second register, the count value indicating a number of outstanding accesses to the network-on-chip in the functional module; resetting, in response to the count value indicating that there is no outstanding access to the network-on-chip in the functional module, the functional module; and resetting, in response to the number of accesses being equal to the threshold number, the system-on-chip.

2. The method of claim 1, wherein resetting the functional module comprises: comparing the count value to a threshold count value; and determining, in response to the count value being the same as the threshold count value, that there is no outstanding access to the network-on-chip in the functional module.

3. The method of claim 2, further comprising: determining, in response to the count value being different from the threshold count value, that there is an outstanding access to the network-on-chip in the functional module; incrementing the number of accesses; and determining, after a predetermined period of time, whether there is an outstanding access to the network-on-chip in the functional module based on the incremented number of accesses and a newly obtained count value.

4. The method of claim 1, further comprising: obtaining information related to the exception from a status register of the functional module, the status register being different from the first register and the second register.

5. The method of claim 1, further comprising: sending a task to the reset functional module.

6. An apparatus for reset, comprising: a scheduling module configured to adjust, in response to receiving a message related to an exception of a functional module of a system-on-chip, an indication value in a first register of the functional module for preventing the functional module from new accesses to a network-on-chip of the system-on-chip; an obtaining module configured to obtain, in response to a number of accesses to a second register of the functional module being less than a threshold number, a count value within the second register, the count value indicating a number of outstanding accesses to the network-on-chip in the functional module; and a functional module reset module configured to reset, in response to the count value indicating that there is no outstanding access to the network-on-chip in the functional module, the functional module.

7. The apparatus of claim 6, further comprising: a system reset module configured to reset, in response to the number of accesses being equal to the threshold number, the system-on-chip.

8. The apparatus of claim 6, wherein the functional module reset module comprises: a comparing module configured to compare the count value to a threshold count value; and a determining module configured to determine, in response to the count value being the same as the threshold count value, that there is no outstanding access to the network-on-chip in the functional module. ​ ​ ​ ​ a first outstanding access determination module configured to determine, in response to the count value being the same as the threshold count value, that there is no outstanding access to the network-on-chip in the functional module.

9. The apparatus of claim 8, further comprising: a first outstanding access determination module configured to determine, in response to the count value being different from the threshold count value, that there is an outstanding access to the network-on-chip in the functional module; an increment module configured to increment the access count; and a re-determination module configured to determine, after a predetermined period of time, whether there is an outstanding access to the network-on-chip in the functional module based on the incremented access count and the re-acquired count value.

10. The apparatus of claim 6, further comprising: an exception information acquisition module configured to acquire information related to the exception from a status register of the functional module, the status register being different from the first register and the second register.

11. The apparatus of claim 6, further comprising: a sending module configured to send a task to the functional module that is reset.

12. A system-on-chip, comprising: at least one processor; a functional module, the functional module comprising at least a first register and a second register, and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

13. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, the computer instructions are for causing the computer to perform the method of any one of claims 1-5.

14. A computer program product comprising computer program which, when executed by a processor, implements the method of any one of claims 1-5.

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