Switch chip, switch, computing system and message transmission method

Abstract

The embodiment of the invention provides a switch chip, a switch, a computing system and a message transmission method. The scheme is suitable for the switch chip comprising a CISC instruction set, an RISC reduced instruction set (especially an RISC-V instruction set) or a VLIM instruction set architecture. The switch chip comprises an on-chip network, a plurality of port clusters and a plurality of physical layer ports, the port cluster comprises a plurality of switch ports, each switch port is connected with one physical layer port, and the switch ports are connected with the on-chip network; the physical layer port is used for sending the received message to the switch port connected with the physical layer port; and the switch port is used for caching the received message to an inlet end data caching unit included in the switch port, and sending the cached message to the output port through the network-on-chip after receiving permission information sent by the output port through the network-on-chip. According to the scheme, the message transmission delay of the switch chip can be reduced.

Description

Switch chips, switches, computing systems, and message transmission methods Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a switch chip, a switch, a computing system, and a message transmission method. Background Technology

[0002] General-purpose computing on graphics processing units (GPGPUs) are widely used in artificial intelligence (AI) training and inference tasks. Scale-up is a technique to enhance parallel computing capabilities by increasing the number of GPGPUs, memory bandwidth, and computing unit size. Switch chips are the core chips for achieving GPGPU scale-up.

[0003] Currently, the switch chip adopts a shared buffer structure. All packets received by all ports need to be stored in the shared buffer and then scheduled to the output port by the central traffic scheduler.

[0004] However, since all received messages are stored in a shared buffer and then uniformly scheduled to the corresponding output port by the central traffic scheduler, this will result in a large delay in message transmission. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a switch chip, a switch, a computing system, and a message transmission method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a switch chip is provided, comprising: an on-chip network, a plurality of port clusters, and a plurality of physical layer ports; the port cluster includes a plurality of switch ports, each of the switch ports being connected to one of the physical layer ports, and the switch ports being connected to the on-chip network; the physical layer ports are configured to send received packets to the connected switch ports; the switch ports are configured to, upon receiving the packet, cache the packet in an ingress data cache unit included in the switch port, and, upon receiving permission information sent by an output port through the on-chip network, send the cached packet to the output port through the on-chip network, wherein the output port is the destination switch port of the packet.

[0007] According to a second aspect of the present disclosure, a switch is provided, comprising: a printed circuit board and at least one switch chip as described in the first aspect above; the switch chip is electrically connected to the printed circuit board.

[0008] According to a third aspect of the present disclosure, a computing system is provided, comprising: a plurality of computing units and a plurality of switch chips as described in the first aspect above; the plurality of switch chips includes a plurality of first switch chips and a plurality of second switch chips; the plurality of computing units and the plurality of first switch chips constitute a plurality of computing clusters, each computing cluster including a plurality of computing units and a plurality of first switch chips, each first switch chip in a computing cluster being connected to a plurality of computing units included in the computing cluster, and each computing unit in a computing cluster being connected to a plurality of first switch chips included in the computing cluster; each first switch chip being connected to at least one second switch chip, such that any two computing units among the plurality of computing units are interconnected through the first switch chip or through the first switch chip and the second switch chip.

[0009] According to a fourth aspect of the present disclosure, a message transmission method is provided, applied to a switch chip. The switch chip includes an on-chip network, multiple port clusters, and multiple physical layer ports. The port clusters include multiple switch ports, each switch port is connected to one physical layer port, and the switch ports are connected to the on-chip network. The method includes: receiving a message through the physical layer port, and after converting the received message from a serial signal to a parallel signal, sending the converted message to the connected switch port; buffering the received message in an ingress data buffer unit included in the switch port through the switch port, and after receiving permission information sent by an output port through the on-chip network, sending the message to the output port through the on-chip network, wherein the output port is the destination switch port of the message.

[0010] According to the scheme provided in this disclosure, each switch port is connected to a physical layer port and is connected to an on-chip network. Each switch port includes a dedicated inbound data buffer unit. After receiving a packet, the physical layer port can send the packet to the connected switch port. The switch port can first buffer the packet in its inbound buffer unit, and after receiving permission information from the output port, it then sends the buffered packet to the output port via the on-chip network. Because the switch port has a dedicated inbound data buffer unit and can perform its own packet transmission arbitration process, distributed storage and arbitration of packets are implemented in the switch chip. Compared to shared memory network switching chips, this reduces the waiting time before packet forwarding, thereby reducing packet forwarding latency and improving packet forwarding efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 is a schematic diagram of a switch chip according to one embodiment of the present disclosure; Figure 2 is a schematic diagram of a switch chip according to another embodiment of the present disclosure; Figure 3 is a schematic diagram of a switch chip according to yet another embodiment of the present disclosure; Figure 4 is a schematic diagram of a switch port according to one embodiment of the present disclosure; Figure 5 is a schematic diagram of a computing system according to one embodiment of the present disclosure; Figure 6 is a flowchart of a message transmission method according to one embodiment of the present disclosure. Detailed Implementation

[0013] The present disclosure is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present disclosure below, certain specific details are described in detail. Those skilled in the art will fully understand the present disclosure even without these details. To avoid obscuring the substance of the present disclosure, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0014] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0015] Network on Chip (NoC): Network on Chip (NoC) is a novel communication method for System on Chip (SoC). NoC connects multiple nodes on a chip, enabling reliable communication between them. The topologies that can be formed by the nodes in a NoC include 2D / 3D mesh networks, torus networks, and ring networks.

[0016] Switch: A switch is a network device used for forwarding electrical (optical) signals. A switch can provide a dedicated electrical signal path for any two connected network nodes. In embodiments of this disclosure, the switch can be a network device used for forwarding signals between GPGPUs or Graphics Processing Units (GPUs).

[0017] Switch chip: A switch chip is a highly integrated application-specific integrated circuit (ASIC) and the core processing unit of a network switch. Its main task is to perform high-speed forwarding, filtering, flow control, and quality management of data packets at the data link layer or network layer according to network protocols.

[0018] switch chip Figure 1 shows a schematic block diagram of a switch chip 10 according to an embodiment of the present disclosure. As shown in Figure 1, the switch chip 10 includes an on-chip network 11, multiple port clusters 12, and multiple physical layer ports 13. The port clusters 12 include multiple switch ports 121, each switch port 121 is connected to a physical layer port 13, and the switch ports 121 are connected to the on-chip network 11.

[0019] Physical layer port 13 can send received packets to the connected switch port 121. After receiving the packet, switch port 121 buffers the packet in the ingress data buffer unit included in switch port 121, and after receiving the permission information sent by the output port through the on-chip network 11, it sends the buffered packet to the output port through the on-chip network 11. The output port is the destination switch port of the packet.

[0020] Physical layer port 13 is used to connect network nodes, such as GPGPUs. One GPGPU can send packets to another GPGPU through switch chip 10. After receiving a packet from the network node it is connected to, physical layer port 13 can forward the packet to the connected switch port 121. The packets sent by the network node to physical layer port 13 are usually serial signals. Physical layer port 13 needs to convert the packets from serial signals to parallel signals, and then send the converted parallel signals to the connected switch port 121.

[0021] After receiving a packet, switch port 121 can determine the destination switch port of the packet as the output port, that is, the output port is the switch port connected to the destination network node of the packet. Switch port 121 includes an inbound data buffer unit, and different switch ports 121 have their own independent inbound data buffer units. After receiving a packet, switch port 121 can first buffer the packet in its inbound data buffer unit.

[0022] After the switch port 121 buffers a packet in the inbound data buffer unit, it continues to buffer the packet in the inbound data buffer unit until it receives permission information from the output port. Upon receiving permission information from the output port, it retrieves the packet from the inbound data buffer unit and sends the retrieved packet to the output port via the on-chip network 11. After receiving the packet, the output port can send it to the connected physical layer port 13, which in turn sends the packet to the destination network node.

[0023] The permission information is used to indicate that the output port has sufficient storage space to accommodate the message. Before sending a message to the output port, switch port 121 needs to verify whether the output port has enough storage space. Once the output port determines that it has sufficient storage space, it sends permission information to switch port 121. Switch port 121 then sends the message to the output port only after receiving the permission information. This ensures that the output port can receive and buffer the message after it is transmitted, preventing message loss due to data overflow caused by insufficient storage space and ensuring reliable message transmission.

[0024] In this embodiment, each switch port 121 is connected to a physical layer port 13, and the switch port 121 is connected to the on-chip network 11. Each switch port 121 includes a dedicated inbound data buffer unit. After receiving a packet, the physical layer port 13 can send the packet to the connected switch port 121. The switch port 121 can first buffer the packet in its inbound buffer unit, and after receiving permission information from the output port, it then sends the buffered packet to the output port via the on-chip network 11. Because the switch port 121 has a dedicated inbound data buffer unit and can perform its own packet transmission arbitration process, distributed packet storage and arbitration are implemented in the switch chip 10. Compared to shared memory network switching chips, this reduces the waiting time before packet forwarding, thereby reducing packet forwarding latency and improving packet forwarding efficiency.

[0025] In one possible implementation, as shown in the schematic diagram of the switch chip 10 in Figure 2, the on-chip network 11 includes a global network unit 111 and multiple local network units 112, with each port cluster 12 corresponding to a local network unit 112.

[0026] The local network unit 112 can transmit communication data between switch ports 121 in the corresponding port cluster 12. The communication data may include messages and license information. That is, between different switch ports 121 in the same port cluster 12, messages and license information can be transmitted through the local network unit 112 corresponding to the port cluster 12.

[0027] The global network unit 111 can transmit communication data between switch ports 121 located in different port clusters 12. That is, between switch ports 121 located in different port clusters 12, messages and permission information can be transmitted through the global network unit 111.

[0028] In one example, when the output port corresponding to the message received by switch port 121 is located in the same port cluster 12 as switch port 121, switch port 121 verifies with the output port whether there is enough storage space to cache the message. After the output port determines that there is enough storage space to cache the message, it sends the permission information to switch port 121 through local network unit 112. After receiving the permission information, switch port 121 sends the message to the output port through local network unit 112.

[0029] In another example, when the output port corresponding to the message received by switch port 121 is located in a different port cluster 12 than switch port 121, switch port 121 verifies with the output port whether there is enough storage space to cache the message. After the output port determines that there is enough storage space to cache the message, it sends permission information to switch port 121 through global network unit 111. After receiving the permission information, switch port 121 sends the message to the output port through global network unit 111.

[0030] It should be noted that when switch ports 121 located in different port clusters 12 communicate, they can communicate directly through the global network unit 111, that is, switch ports 121 are directly connected to the global network unit 111, or they can communicate through the local network unit 112 and the global network unit 111, that is, the local network unit 112 is connected to the global network unit 111. However, switch ports 121 are not directly connected to the global network unit 111. This disclosure does not limit the specific connection of switch ports 121 to the global network unit 111.

[0031] It should be noted that the physical layer port 13 included in the switch chip 10 is not shown in Figure 2. The physical layer port 13 can be set around the port cluster 12 and the global network unit 111. For example, the physical layer ports 13 are distributed in a ring, and the port cluster 12 and the global network unit 111 are located inside the ring formed by the physical layer ports 13.

[0032] In this embodiment, the on-chip network 11 includes a global network unit 111 and multiple local network units 112. Each port cluster 12 corresponds to one local network unit 112. Switch ports 121 within a port cluster 12 can transmit communication data through the local network unit 112 corresponding to that port cluster 12. Switch ports 121 located in different port clusters 12 can transmit communication data through the global network unit 111. The switch ports 121 within the same port cluster 12 are arranged around the local network unit 112 corresponding to that port cluster 12. While ensuring the interconnection of all switch ports 121, this shortens the communication path between switch ports 121 within the same port cluster 12, thereby reducing the latency of message transmission between switch ports 121 within the same port cluster 12.

[0033] In one possible implementation, as shown in the schematic diagram of the switch chip 10 in Figure 3, the port cluster 12 includes multiple port groups 122, and each port group 122 includes N switch ports 121, where N is an integer greater than or equal to 2. The on-chip network 11 includes multiple port network units 113, and each port group 122 corresponds to one port network unit 113.

[0034] In one example, the switch chip 10 includes four port clusters 12, each port cluster 12 includes four port groups 122, and each port group 122 includes four switch ports 121. Therefore, the switch chip 10 includes 64 switch ports 121 and 64 physical layer ports 13. Each switch port 121 connects to one physical layer port 13, and different switch ports 121 connect to different physical layer ports 13. Correspondingly, the on-chip network 11 includes one global network unit 111, four local network units 112, and 16 port network units 113.

[0035] Local network unit 112 can transmit communication data between switch ports located in the same port cluster 12 but different port groups 122. Port network unit 113 can transmit communication data between switch ports 121 in the corresponding port group 122.

[0036] In one example, if the first switch port and the second switch port are located in the same port group 122, then the first switch port and the second switch port transmit messages and permission information through the port network unit 113 corresponding to the port group 122. If the first switch port and the third switch port are located in the same port cluster 12, but in different port groups 122, then the first switch port and the third switch port transmit messages and permission information through the local network unit 112 corresponding to their respective port cluster 12. If the first switch port and the fourth switch port are located in different port clusters 12, then the first switch port and the fourth switch port transmit messages and permission information through the global network unit 111.

[0037] It should be noted that the connection methods between switch port 121 and local network unit 112 and global network unit 111 are as follows: i. Switch port 121 is directly connected to the corresponding port network unit 113, local network unit 112 and global network unit 111 respectively; ii. Switch port 121 is directly connected to the corresponding port network unit 113, and through port network unit 113 it is connected to the corresponding local network unit 112 and global network unit 111 respectively; iii. Switch port 121 is directly connected to the corresponding port network unit 113, through port network unit 113 it is connected to the corresponding local network unit 112, and through port network unit 113 and local network unit 112 it is connected to global network unit 111.

[0038] When the switch port 121 that receives the message and the corresponding output port are located in the same port group 122: for connection type i, connection type ii and connection type iii, the switch port 121 bracket sends the message to the output port through the connected port network unit 113.

[0039] When the switch port 121 that receives the message and the corresponding output port are located in the same port cluster 12 but in different port groups 122: For connection type i, switch port 121 directly sends the message to the output port through the connected local network unit 112; for connection types ii and iii, switch port 121 first sends the message to the connected port network unit 113, and then the port network unit 113 sends the message to the port network unit 113 connected to the output port, and then the port network unit 113 connected to the output port sends the message to the output port.

[0040] When the switch port 121 receiving the message and the corresponding output port are located in different port clusters 12: For connection type i, switch port 121 directly sends the message to the output port through global network unit 111; for connection type ii, switch port 121 first sends the message to the connected port network unit 113, then the port network unit 113 sends the message to global network unit 111, then the global network unit 111 sends the message to the port network unit 113 connected to the output port, and then the port network unit 113 connected to the output port sends the message to the output port; for connection type i ii. Switch port 121 first sends the message to the connected port network unit 113, then the port network unit 113 sends the message to the connected local network unit 112, then the local network unit 112 sends the message to the global network unit 111, then the global network unit 111 sends the message to the local network unit 112 connected to the output port through port network unit 113, then the local network unit 112 connected to the output port through port network unit 113 sends the message to the port network unit 113 connected to the output port, and finally the port network unit 113 connected to the output port sends the message to the output port.

[0041] It should be noted that the physical layer port 13 included in the switch chip 10 is not shown in Figure 3. The physical layer port 13 can be set around the port cluster 12 and the global network unit 111. For example, the physical layer ports 13 are distributed in a ring, and the port cluster 12 and the global network unit 111 are located inside the ring formed by the physical layer ports 13.

[0042] In this embodiment of the disclosure, the on-chip network 11 includes a global network unit 111, multiple local network units 112, and multiple port network units 113. Each port cluster 12 corresponds to a local network unit 112, and each port group 122 corresponds to a port network unit 113. Switch ports 121 within a port group 122 can transmit communication data through the port network unit 113 corresponding to that port group 122. Switch ports 121 within a port cluster 12 can transmit communication data through the local network unit 112 corresponding to that port cluster 12. Switch ports 121 located in different port clusters 12 can transmit communication data through the global network unit 111. In the same port group 122, the switch ports 121 are positioned adjacent to the port network unit 113 corresponding to that port group 122. In the same port cluster 12, the port groups 122 are positioned around the local network unit 112 corresponding to that port cluster 12. Each port cluster 12 is positioned around the global network unit 111. While ensuring the interconnection of all switch ports 121, the communication path between switch ports 121 in the same port cluster 12 is shortened by setting the port network unit 113 and the local network unit 112. This reduces the latency of message transmission between switch ports 121 in the same port cluster 12 and improves the overall performance of the switch chip 10.

[0043] In one possible implementation, as shown in the schematic diagram of switch port 121 in Figure 4, switch port 121 includes a logic processing unit 123, a traffic management unit 124, and an inbound data buffer unit 125.

[0044] The logic processing unit 123 is connected to the physical layer port 13. After receiving a packet from the physical layer port 13, the logic processing unit 123 can cache the packet in the inbound data cache unit 125. After determining that the output port allows new requests, it sends a transmission request to the output port. Upon receiving the transmission request, if the transmission port can accept new request packets, it sends permission information to the flow management unit 124. After receiving the permission information from the output port, the flow management unit 124 can perform arbitration based on the permission information to obtain first arbitration result information that indicates the dequeue order of packets cached in the inbound data cache unit 125, and then send the first arbitration result information to the inbound data cache unit 125. Upon receiving the first arbitration result information, the inbound data cache unit 125 can send the cached packets to the corresponding output ports in order according to the first arbitration result information.

[0045] The logic processing unit 123 can perform protocol-related logic processing, such as processing the packet header and routing information. The logic processing unit 123 can obtain the destination address based on the packet header information and apply the destination address to the corresponding output port, thereby determining the output port corresponding to the packet. The inbound data buffer unit 125 can implement data buffering at the input end. Each switch port 121 has a separate inbound data buffer unit 125, and the inbound data buffer unit 125 is not shared between different switch ports 121.

[0046] Because the packet processing capacity of switch port 121 is limited, it is necessary to check whether the output port is capable of accepting new requests before sending a packet to the output port. Therefore, after buffering the packet in the ingress data buffer unit 125, the logic processing unit 123 first checks whether the corresponding output port allows accepting new requests. If the output port allows accepting new requests, a transmission request is sent to the output port to request packet transmission. If the output port does not currently allow accepting new requests, the transmission request is sent to the output port only after it has been allowed to accept new requests.

[0047] Provided that the output port is authorized to accept new requests, the logic processing unit 123 needs to send a transmission request to the output port to check if there is available space to accommodate the new message. If the output port has available space to accommodate the new message, the output port will return permission information to the corresponding input port, which is the switch port 121 that issued the transmission request.

[0048] Since switch port 121 can simultaneously receive permission information returned from multiple output ports, the traffic management unit 124 in the input port needs to arbitrate the multiple permission information to determine the dequeue order of the corresponding packets in the inbound data buffer unit 125, and then send the first arbitration result information that can indicate the dequeue order of the packets to the inbound data buffer unit 125. Based on the first arbitration result information, the inbound data buffer unit 125 schedules the packets buffered therein. The scheduled packets will undergo a dequeue operation, being read from the buffer and sent to the on-chip network 11 (one or more of port network unit 113, local network unit 112, and global network unit 111) for processing. Based on the destination port of the packet, the on-chip network 11 selects one or more of port network unit 113, local network unit 112, and global network unit 111 to send the packet to the destination port (output port).

[0049] The traffic management unit 124 can arbitrate the permission information based on the Deficit Weighted Round Robin (DWRR) scheduling algorithm or a similar algorithm to ensure the fairness of traffic between different output ports. The traffic management unit 124 can arbitrate the permission information based on any suitable arbitration algorithm, and this embodiment of the disclosure does not limit the arbitration algorithm used by the traffic management unit 124.

[0050] It should be noted that the transmission path for the input port to send a transmission request to the output port via the on-chip network 11 is the same as the transmission path for sending a message to the output port via the on-chip network 11. The transmission path for the output port to send permission information to the input port via the on-chip network 11 is the opposite of the transmission path for the input port to send a message to the output port via the on-chip network 11.

[0051] In this embodiment, the switch port 121 includes a logic processing unit 123, a traffic management unit 124, and an inbound data buffer unit 125. The logic processing unit 123 determines the output port corresponding to a packet and buffers the packet in the inbound data buffer unit 125. Then, after determining that the output port allows new requests, it sends a transmission request to the output port. Upon receiving permission information from the output port, the traffic management unit 124 arbitrates the permission information and sends the first arbitration result information to the inbound data buffer unit 125, enabling the inbound data buffer unit 125 to send the packet to the output port based on the first arbitration result information. By sending a transmission request to the output port only after determining that it can accept new requests, the logic processing unit 123 reduces the probability of head-of-line congestion and lowers end-to-end latency. The traffic management unit 124 arbitrates only after receiving permission information, reducing the number of arbitrations at the same clock frequency, lowering the power consumption of the switch chip, shortening the arbitration window, and finer-grained scheduling, thus reducing small flow tail latency. The entire system forms a closed-loop hard handshake of "request-permission-dequeue," moving the Pan-Asian signal forward before arbitration. This transforms the entire switching pipeline into an ideal state of "non-blocking input → congestion-free output → no idle cycles," improving throughput utilization while maintaining a low packet loss rate even with bursty traffic. The reverse handshake mechanism, which prioritizes obtaining permission before arbitration, solves the problems of head-of-queue blocking and buffer waste, thus achieving low latency, high throughput, and memory savings.

[0052] In one possible implementation, the logic processing unit 123 can determine whether the output port is allowed to accept new requests by checking the request signaling (credit) of the output port.

[0053] In this embodiment, the availability of sufficient buffer space at the output port is pre-determined based on the request signaling from the output port. This prevents the input port from forcibly sending data when the output port is unprepared, thus preventing data packet loss due to buffer overflow and improving the reliability of message transmission by the switch chip 10. The credit mechanism based on request signaling is a hardware-based, low-latency flow control method that allows the input port to send data only when it has "credit," thereby achieving precise and timely flow adjustment and avoiding network or bus congestion. Since the credit feedback mechanism can dynamically reflect the available resources of the output port, the input port can adjust its sending rhythm according to the actual situation, sending data quickly when the output port is idle and pausing when the output port is busy, thereby maximizing link utilization and avoiding performance degradation caused by blind retries or waiting for confirmation. The logic processing unit 123 sends a transmission request to the output port only after determining that the output port is allowed to receive new requests, avoiding data transmission attempts when the output port cannot handle the request, reducing invalid signal driving and retransmission mechanism triggering, thereby reducing the overall power consumption and processing overhead of the switch chip 10. Because the signaling mechanism makes data flow more controllable and predictable, the logic processing unit 123 sends a transmission request based on the request signaling check result, which helps to achieve deterministic latency and stable performance in the switch chip 10.

[0054] In one possible implementation, as shown in Figure 4, in addition to the logic processing unit 123, the traffic management unit 124, and the inbound data buffer unit 125, the switch port 121 may also include an outbound data buffer unit 126.

[0055] After receiving a transmission request from the input port, the traffic management unit 124 included in the output port can send permission information to the traffic management unit 124 in the input port according to preset scheduling rules. The input port is the switch port 121 that receives packets from the physical layer port 13; that is, the input port is the switch port 121 that receives packets and sends transmission requests and packets to the output port.

[0056] After receiving a message sent by the ingress data buffer unit 125 in the input port, the logic processing unit 123 of the output port buffers the message into the egress data buffer unit 126. Then, the egress data buffer unit 126 can send the buffered message to the physical layer port 13 connected to the output port.

[0057] The output data buffer unit 126 implements output data buffering, which can receive data from each input port and temporarily store it in the output buffer.

[0058] Since the traffic management unit 124 included in the output port can receive transmission requests from multiple input ports, it schedules these requests according to preset scheduling rules to ensure fairness in traffic flow between different input ports. After a transmission request is scheduled, the traffic management unit 124 checks if the egress data buffer unit 126 has sufficient space to accommodate the packet. If the egress data buffer unit 126 has enough storage space, it can accept the query request. If the egress data buffer unit 126 does not have enough storage space, it will delay arbitration of the transmission request. After receiving a query request, the traffic management unit 124 sends permission information to the corresponding input port.

[0059] The output port includes a traffic management unit 124 that can schedule transmission requests from different input ports based on the principle of fairness. For example, it can schedule transmission requests from different input ports based on the DWRR scheduling algorithm or a similar algorithm. The traffic management unit 124 can schedule transmission requests from different input ports based on any suitable scheduling algorithm. This embodiment of the disclosure does not limit the scheduling algorithm used by the traffic management unit 124.

[0060] It should be noted that the same switch port 121 can be used as both an input port and an output port. For any switch port 121, if the physical layer port 13 connected to the switch port 121 sends a message to the switch port 121, then the switch port 121 is used as an input port; if the switch port 121 is the destination port of a message, then the switch port 121 is used as an output port for that message.

[0061] In this embodiment, since the output port can receive transmission requests from multiple input ports, the traffic management unit 124 included in the output port can schedule transmission requests from different input ports according to preset scheduling rules. For the scheduled transmission request, the traffic management unit 124 will send permission information to the corresponding input port so that the input port can send packets through the on-chip network 11, ensuring the fairness of traffic between different input ports, thereby ensuring that each computing unit connected to the switch chip 10 can transmit packets fairly and ensuring the performance of the entire system. After receiving a packet from the input port, the logic processing unit 123 in the output port buffers the packet in the egress data buffer unit 126, and then sequentially dequeues the packets buffered in the egress data buffer unit 126 to avoid packet loss due to the inability to transmit packets to the physical layer port 13 in time when there are many packets, thereby ensuring the reliability of packet transmission by the switch chip 10.

[0062] In one possible implementation, the traffic management unit 124 can send a second arbitration result to the egress data buffer unit 126 according to a preset scheduling rule. The second arbitration result can indicate the dequeue order of the packets buffered by the egress data buffer unit 126. The egress data buffer unit 126 can then send the buffered packets to the connected physical layer port 13 according to the second arbitration result.

[0063] Since the logic processing unit 123 in the output port buffers packets from multiple input ports into the egress data buffer unit 126, to ensure the fairness of traffic across input ports, the traffic management unit 124 in the output port arbitrates the packets buffered in the egress data buffer unit 126 according to preset scheduling rules. This arbitration results instructs the packets in the egress data buffer unit 126 to obtain a second arbitration result, which in turn sends this result to the egress data buffer unit 126. The egress data buffer unit 126 can then schedule the packets in the buffer based on the second arbitration result. The scheduled packets will be dequeued, read from the buffer, and sent to the connected physical layer port 13.

[0064] The traffic management unit 124 in the output port can arbitrate the packets cached by the egress data buffer unit 126 based on the DWRR scheduling algorithm or a similar algorithm to ensure the fairness of traffic between different input ports. The traffic management unit 124 can arbitrate the packets cached by the egress data buffer unit 126 based on any suitable scheduling algorithm. This embodiment of the disclosure does not limit the scheduling algorithm used by the traffic management unit 124.

[0065] In this embodiment, the traffic management unit 124 in the output port arbitrates the packets cached by the egress data caching unit 126 to obtain second arbitration result information that can indicate the dequeue order of the packets cached by the egress data caching unit 126. Then, the second arbitration result information is sent to the egress data caching unit 126, so that the egress data caching unit 126 sends the packets cached therein to the connected physical layer port 13 according to the second arbitration result information, thus ensuring the traffic fairness of different input ports and ensuring the overall performance of the switch chip 10.

[0066] In one possible implementation, both the on-chip network 11 and the switch port 121 use a cut-through mode to process the received communication data. The communication data includes messages and permission information, etc.

[0067] The on-chip network 11 includes a global network unit 111, a local network unit 112, and a port network unit 113. All three units (global, local, and port) process the received communication data using a pass-through forwarding mode. The switch port 121 includes a logic processing unit 123, a traffic management unit 124, an inbound data buffer unit 125, and an outbound data buffer unit 126. All three units (logic processing unit 123, traffic management unit 124, inbound data buffer unit 125, and outbound data buffer unit 126) process the received communication data using a pass-through forwarding mode.

[0068] In this embodiment, the pass-through forwarding mode allows forwarding to begin before the data packet has been fully received. That is, the packet is processed immediately after the packet header is received, instead of waiting for the entire packet to be buffered before processing. Both the on-chip network 11 and the switch port 121 adopt the pass-through forwarding mode. During the packet forwarding process, complex protocol processing, packet slicing, shared buffer processing and scheduling are eliminated. Packets of any size can be sent to the output port as long as they obtain permission information from the output port, which reduces the packet forwarding latency and increases the bandwidth of the switch chip 10 for packet forwarding.

[0069] In one possible implementation, the traffic management unit 124 implements traffic management functions. Each switch port 121 instantiates a traffic management unit 124 to arbitrate requests for access to that switch port 121 and the granting of permissions from different ports. The traffic management unit 124 ensures fairness of traffic between ports. Unlike traditional Ethernet switch chips that use a single top-level traffic management unit to handle the scheduling and forwarding of traffic across all ports, in this embodiment, the traffic management units 124 are distributed across each switch port 121, responsible only for scheduling their own port. They distribute scheduling information to other switch ports 121 through the control network, thereby increasing the scheduling rate and solving the problem of low packet scheduling rates.

[0070] switch This disclosure provides a switch that includes a printed circuit board and at least one switch chip 10 as described in any of the above embodiments, the switch chip 10 being electrically connected to the printed circuit board.

[0071] It should be noted that the switch in this embodiment is a specific application of the switch chip 10 in the foregoing embodiments. The specific working process of the switch can be found in the description of the foregoing switch chip embodiments, and it has the beneficial effects of the switch chip embodiments, which will not be repeated here.

[0072] Computing SystemFigure 5 shows a schematic block diagram of a computing system 100 according to an embodiment of the present disclosure. As shown in Figure 5, the computing system 100 includes a plurality of computing units 20 and a plurality of switch chips 10 provided in any of the above embodiments. The switch chips 10 included in the computing system 100 are divided into first switch chips 101 and second switch chips 102. There are multiple first switch chips 101 and multiple second switch chips 102, and the first switch chips 101 and the second switch chips 102 may have the same structure.

[0073] Multiple computing units 20 and multiple first switch chips 101 constitute multiple computing clusters 110. Each computing cluster 110 includes multiple computing units 20 and multiple first switch chips 101. Each first switch chip 101 in the computing cluster 110 is connected to the multiple computing units 20 included in the computing cluster 110, and each computing unit 20 in the computing cluster 110 is connected to the multiple first switch chips 101 included in the computing cluster 110.

[0074] Each first switch chip 101 is connected to at least one second switch chip 102, so that any two computing units 20 in the computing system 100 are interconnected through the first switch chip 101 or through the first switch chip 101 and the second switch chip 102.

[0075] In one example, the number of first switch chips 101 and computing units 20 included in computing cluster 110 can be determined based on the number of physical layer ports 13 included in switch chip 10 and the number of ports in computing unit 20. For example, if switch chip 10 includes 64 physical layer ports 13 and computing unit 20 includes 8 ports, then each computing cluster 110 can include 8 first switch chips 101 and 32 computing units 20. Each first switch chip 101 is connected to 32 computing units 20, and each computing unit 20 is connected to 8 first switch chips 101. It should be understood that the number of physical layer ports 13 included in switch chip 10 and the number of ports in computing unit 20 determine the upper limit of the number of first switch chips 101 and computing units 20 included in computing cluster 110. In practical applications, the number of first switch chips 101 and computing units 20 included in computing cluster 110 can be less than or equal to the corresponding upper limit.

[0076] In one example, the number of computing clusters 110 and second switch chips 102 can be determined based on the number of physical layer ports 13 included in the switch chip 10. For example, if the switch chip 10 includes 64 physical layer ports 13, then the computing system 100 may include 64 computing clusters 110 and 32 second switch chips 102. The i-th second switch chip 102 among the 32 second switch chips 102 is connected to the i-th first switch chip 101 in each computing cluster 110, where i is a positive integer less than or equal to 32.

[0077] It should be noted that the connection relationship between the first switch chip 101, the second switch chip 102 and the computing unit 20 in the computing system 100 is only an example of the computing system 100. Under the premise that any two computing units 20 can communicate, the first switch chip 101, the second switch chip 102 and the computing unit 20 can be interconnected in any way.

[0078] The computing unit 20 can be a device such as a GPGPU that needs to communicate with each other.

[0079] It should be noted that the computing system in this embodiment is a specific application of the switch chip 10 in the aforementioned embodiment. The process of data exchange between computing units in the computing system can be referred to the description in the aforementioned switch chip embodiment, and has the beneficial effects of the switch chip embodiment, which will not be repeated here.

[0080] Message transmission method Based on the switch chip 10 in the foregoing embodiments, this disclosure provides a message transmission method that can be executed by the switch chip 10 in the above embodiments. The message transmission method will be described in detail below through several embodiments.

[0081] Figure 6 is a flowchart of a message transmission method according to an embodiment of the present disclosure. As shown in Figure 6, the message transmission method includes the following steps: Step 601: Receive a message through a physical layer port, and after converting the received message from a serial signal to a parallel signal, send the converted message to a connected switch port; Step 602: Through the switch port, after receiving the message and buffering it in the ingress data buffer unit included in the switch port, and after receiving the permission information sent by the output port through the on-chip network, send the message to the output port through the on-chip network, where the output port is the destination switch port of the message.

[0082] In this embodiment, each switch port is connected to a physical layer port and is connected to an on-chip network. Each switch port includes a dedicated inbound data buffer unit. After receiving a packet through the physical layer port, the packet is sent to the connected switch port. The switch port first buffers the packet in its inbound buffer unit. After receiving permission information from the output port, it then sends the buffered packet to the output port via the on-chip network. Because the switch port has a dedicated inbound data buffer unit and can perform its own packet transmission arbitration process, distributed packet storage and arbitration are implemented within the switch chip. Compared to shared memory network switching chips, this reduces the waiting time before packet forwarding, thereby reducing packet forwarding latency and improving packet forwarding efficiency.

[0083] In one possible implementation, when the switch port includes a logic processing unit, a traffic management unit, and an inbound data buffer unit, the logic processing unit can send a transmission request to the output port after determining that the output port is allowed to accept new requests. After receiving the permission information sent by the output port in response to the transmission request, the traffic management unit sends a first arbitration result information to the inbound data buffer unit. The first arbitration result information is used to indicate the dequeue order of the packets buffered in the inbound data buffer unit. The inbound buffer unit sends the packets buffered therein to the output port according to the first arbitration result information.

[0084] In this embodiment, the logic processing unit determines that the output port can accept a new request before sending a transmission request to the output port, which reduces the probability of head-of-line congestion and end-to-end latency. The traffic management unit arbitrates after receiving the permission information, reducing the number of arbitrations at the same clock frequency, lowering the power consumption of the switch chip, shortening the arbitration window, and finer-grained scheduling, thus reducing small flow tail latency. The entire system forms a hard handshake closed loop of "request-permission-dequeue," moving the pan-Asian signal before arbitration, making the entire switching pipeline an ideal state of "no-blocking input → no-congestion output → no idle cycles," improving throughput utilization while maintaining a low packet loss rate even with burst traffic. The reverse handshake mechanism of obtaining permission before arbitration solves the problems of head-of-line congestion and buffer waste, thereby achieving low latency, high throughput, and memory saving.

[0085] In one possible implementation, the logic processing unit checks the request requests at the output port to determine whether the output port is allowed to accept new requests.

[0086] In this embodiment, the availability of sufficient buffer space at the output port is pre-determined based on the request signaling from the output port. This prevents the input port from forcibly sending data when the output port is unprepared, thus preventing data packet loss due to buffer overflow and improving the reliability of message transmission. The credit mechanism based on request signaling is a hardware-based, low-latency flow control method that allows the input port to send data only when it has "credit," thereby achieving precise and timely flow adjustment and avoiding network or bus congestion. Since the credit feedback mechanism dynamically reflects the available resources of the output port, the input port can adjust its sending rhythm according to the actual situation, sending quickly when the output port is idle and pausing when the output port is busy, thereby maximizing link utilization and avoiding performance degradation caused by blind retries or waiting for confirmation. A transmission request is only sent to the output port after it is determined that the output port is allowed to receive new requests, avoiding data transmission attempts when the output port cannot handle them. This reduces invalid signal driving and retransmission mechanism triggering, thereby reducing the overall power consumption and processing overhead of the message transmission process. Because signaling mechanisms make data flow more controllable and predictable, sending transmission requests based on the results of request signaling checks helps to achieve deterministic delays and stable performance during message transmission.

[0087] In one possible implementation, the switch port may further include an egress data buffer unit. When the switch port acts as an output port, it can receive transmission requests sent by the logic processing unit in the input port through the traffic management unit, and send permission information to the traffic management unit in the input port according to preset scheduling rules. Then, after receiving a packet sent by the ingress data buffer unit in the input port through the logic processing unit, the logic processing unit buffers the packet in the egress data buffer unit. Here, the input port is the switch port that receives packets from the physical layer port.

[0088] In this embodiment, since the output port can receive transmission requests from multiple input ports, the traffic management unit included in the output port can schedule transmission requests from different input ports according to preset scheduling rules. For each scheduled transmission request, permission information is sent to the corresponding input port, enabling the input port to send packets through the on-chip network. This ensures fairness in traffic between different input ports, thereby guaranteeing fair packet transmission for each computing unit connected to the switch chip and ensuring overall system performance. After receiving a packet from an input port, the logic processing unit in the output port buffers the packet in the egress data buffer unit. Then, it sequentially dequeues the buffered packets in the egress data buffer unit. This prevents packet loss due to insufficient time to transmit packets to the physical layer port when there are many packets, thus ensuring the reliability of packet transmission by the switch chip.

[0089] In one possible implementation, the traffic management unit in the output port can send the second arbitration result information to the egress data buffer unit in the output port according to the preset scheduling rules. The second arbitration result information can indicate the dequeue order of the packets buffered by the egress data buffer unit. Then, the egress buffer unit in the input port can send the buffered packets to the connected physical layer port according to the second arbitration result information.

[0090] In this embodiment of the disclosure, the traffic management unit in the output port arbitrates the packets cached by the egress data buffer unit to obtain second arbitration result information that can indicate the dequeue order of the packets cached by the egress data buffer unit. Then, the egress data buffer unit in the output port can send the packets cached therein to the connected physical layer port according to the second arbitration result information, thus ensuring the traffic fairness of different input ports and guaranteeing the overall performance of packet transmission.

[0091] It should be noted that the message transmission method in this embodiment is implemented based on the switch chip in the foregoing embodiment and has the beneficial effects of the switch chip embodiment, which will not be described again here.

[0092] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0093] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.

[0094] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for performing the methods shown herein.

[0095] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments disclosed herein.

[0096] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.

Claims

1. A switch chip, comprising: The system comprises an on-chip network, multiple port clusters, and multiple physical layer ports. The port clusters include multiple switch ports, each of which is connected to one physical layer port, and the switch ports are connected to the on-chip network. The physical layer ports are used to send received packets to the connected switch ports. After receiving a packet, the switch ports are used to cache the packet in an ingress data cache unit included in the switch port, and after receiving permission information sent by an output port through the on-chip network, send the cached packet to the output port through the on-chip network. The output port is the destination switch port of the packet.

2. The switch chip according to claim 1, wherein, The on-chip network includes a global network unit and multiple local network units, with each port cluster corresponding to one local network unit; the local network unit is used to transmit communication data between the switch ports in the corresponding port cluster, and the communication data includes the message and the permission information. The global network unit is used to transmit communication data between the switch ports located in different port clusters.

3. The switch chip according to claim 2, wherein, The port cluster includes multiple port groups, and each port group includes multiple switch ports; the on-chip network includes multiple port network units, and each port group corresponds to one port network unit; the local network unit is used to transmit communication data between switch ports located in different port groups. The port network unit is used to transmit the communication data between the switch ports in the corresponding port group.

4. The switch chip according to claim 1, wherein, The switch port includes a logic processing unit, a traffic management unit, and an inbound data cache unit. The logic processing unit, upon receiving a packet from the physical layer port, caches the packet in the inbound data cache unit and, after determining that the output port allows new requests, sends a transmission request to the output port. The traffic management unit, upon receiving permission information sent by the output port in response to the transmission request, sends a first arbitration result to the inbound data cache unit, the first arbitration result indicating the dequeue order of packets cached in the inbound data cache unit. The inbound data cache unit sends the packet to the output port according to the first arbitration result.

5. The switch chip according to claim 4, wherein, The logic processing unit is configured to determine whether the output port is allowed to accept new requests by checking the request signaling of the output port.

6. The switch chip according to claim 4, wherein, The switch port includes: an egress data caching unit; and a traffic management unit, configured to, upon receiving the transmission request sent by the logic processing unit in the input port, send the permission information to the traffic management unit in the input port according to a preset scheduling rule, wherein the input port is the switch port that receives the packet from the physical layer port; and the logic processing unit, configured to, upon receiving the packet sent by the ingress caching unit in the input port, cache the packet in the egress data caching unit.

7. The switch chip according to claim 6, wherein, The traffic management unit is used to send a second arbitration result information to the egress data caching unit according to a preset scheduling rule. The second arbitration result information is used to indicate the dequeue order of the packets cached by the egress data caching unit. The egress data caching unit is used to send the cached packets to the connected physical layer port according to the second arbitration result information.

8. The switch chip according to any one of claims 1-7, wherein, The on-chip network and the switch port use a pass-through forwarding mode to process the received communication data.

9. A switch, comprising a printed circuit board and at least one switch chip as described in any one of claims 1-8; the switch chip being electrically connected to the printed circuit board.

10. A computing system, comprising: Multiple computing units and multiple switch chips as described in any one of claims 1-8; The plurality of switch chips includes a plurality of first switch chips and a plurality of second switch chips; the plurality of computing units and the plurality of first switch chips constitute a plurality of computing clusters, each computing cluster including a plurality of computing units and a plurality of first switch chips, each first switch chip in the computing cluster being connected to a plurality of computing units included in the computing cluster, and each computing unit in the computing cluster being connected to a plurality of first switch chips included in the computing cluster; each first switch chip is connected to at least one second switch chip, such that any two computing units in the plurality of computing units are interconnected through the first switch chip or through the first switch chip and the second switch chip.

11. A message transmission method applied to a switch chip, the switch chip including an on-chip network, multiple port clusters and multiple physical layer ports, the port cluster including multiple switch ports, each switch port connected to one physical layer port, and the switch port connected to the on-chip network, the method comprising: The system receives packets through the physical layer port, converts the received packets from serial signals to parallel signals, and sends the converted packets to the connected switch port. The system also buffers the received packets in the ingress data buffer unit of the switch port, and after receiving permission information from the output port through the on-chip network, sends the packets to the output port through the on-chip network. The output port is the destination switch port of the packets.

12. The method according to claim 11, wherein, The switch port includes a logic processing unit, a traffic management unit, and an inbound data buffer unit. The step of receiving permission information from the output port via the on-chip network and then sending the packet to the output port via the on-chip network includes: the logic processing unit, after determining that the output port allows accepting new requests, sending a transmission request to the output port; the traffic management unit, after receiving permission information from the output port regarding the transmission request, sending first arbitration result information to the inbound data buffer unit, the first arbitration result information indicating the dequeue order of packets buffered by the inbound data buffer unit; and the inbound buffer unit, sending the packet to the output port according to the first arbitration result information.

13. The method according to claim 12, further comprising: By examining the request signaling of the output port, it can be determined whether the output port is allowed to accept new requests.

14. The method according to claim 12, wherein, The switch port further includes an egress data buffer unit, and the method further includes: after receiving a transmission request sent by the logic processing unit in the input port through the traffic management unit, sending permission information to the traffic management unit in the input port according to a preset scheduling rule, wherein the input port is a switch port that receives packets from a physical layer port; and after receiving a packet sent by the ingress buffer unit in the input port through the logic processing unit, caching the received packet in the egress data buffer unit.

15. The method according to claim 14, further comprising: The traffic management unit sends a second arbitration result to the egress data caching unit according to a preset scheduling rule. The second arbitration result is used to indicate the dequeue order of the packets cached by the egress data caching unit. The egress caching unit then sends the cached packets to the connected physical layer port according to the second arbitration result.

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