Programmable logic device layout optimization method, device and related equipment

Abstract

The present invention discloses a method for optimizing the layout of a programmable logic device, which is applied to the field of FPGA chip design and is used to optimize the timing of the global layout results of the FPGA chip. The method provided by the present invention includes: obtaining design units that do not meet the preset timing regulations from the user netlist to generate a design unit set; selecting the design units with poor timing performance from the design unit set as key units to generate a key unit set; constructing candidate position points for the key units in the key unit set according to a preset calculation method and generating a candidate position point set; determining the candidate position points with the best timing performance from the candidate position point set for layout; looping the above steps until the design units all meet the preset timing regulations and stop, and obtaining the optimization result of the global layout.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic devices (PLDs), and in particular to a programmable logic device layout optimization method, device, computer equipment and storage medium. Background Art

[0002] In the EDA (Electronic Design Automation) tool of the FPGA chip in the programmable logic device, the layout algorithm optimizes the timing performance of the chip design in the detailed layout process, which is to optimize the timing performance of the results obtained by the global layout process. In the detailed layout process, the timing optimization only makes small adjustments to the results of the legal layout, and the layout adjustment at this time must ensure that the adjusted position can be successfully laid out.

[0003] The above restrictions will result in the inability to obtain good timing design results after optimizing the timing during the detailed layout process, and the overall timing performance of the user netlist will not meet the requirements. Summary of the invention

[0004] The embodiments of the present invention provide a programmable logic device layout optimization method, apparatus, computer equipment and storage medium to solve the problem that the overall timing performance of the user netlist after the detailed layout process timing optimization in the traditional FPGA chip design cannot be satisfied.

[0005] A programmable logic device layout optimization method, comprising:

[0006] Acquire design units that do not meet preset timing requirements from a user netlist, sort the design units in descending or ascending order according to timing performance, and then classify them to generate a set of design units;

[0007] Selecting the design units with poor timing performance as key units according to a preset ratio from the sorted design unit set, and classifying the key units to generate a key unit set;

[0008] Constructing candidate position points for the key units in the key unit set and generating a set of candidate position points according to a preset calculation method;

[0009] Determine a candidate location point with the best timing performance from the candidate location point set for layout;

[0010] The steps of obtaining the design units that do not meet the preset timing requirements from the user netlist to determining the candidate position points with the best timing performance from the candidate position point set for layout are looped until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirements, thereby obtaining the optimal result of the global layout.

[0011] A programmable logic device layout optimization device, comprising:

[0012] A design unit classification module is used to obtain design units that do not meet the preset timing requirements from the user netlist, and classify the design units after arranging them in descending or ascending order according to the timing performance to generate a design unit set;

[0013] A key unit classification module, used for selecting the design units with poor timing performance from the design unit set according to a preset ratio as key units, and classifying the key units to generate a key unit set;

[0014] A candidate position point calculation module, used to construct candidate position points for the key units in the key unit set and generate a candidate position point set according to a preset calculation method;

[0015] An optimal candidate location point layout module, used to determine the candidate location point with the best timing performance from the candidate location point set for layout;

[0016] A loop module is used to loop the steps of obtaining the design units that do not meet the preset timing requirements from the user netlist to determining the candidate position points with the best timing performance from the candidate position point set for layout, until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirements, to obtain the optimization result of the global layout.

[0017] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned programmable logic device layout optimization method when executing the computer program.

[0018] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned programmable logic device layout optimization method are implemented.

[0019] The above-mentioned programmable logic device layout optimization method, device, computer equipment and storage medium classify the design units with poor timing performance in the global layout process, obtain the optimal candidate position points through a preset calculation method for adjustment, and finally obtain the global layout result with the most optimized timing performance. The global layout process before the detailed layout process performs timing performance optimization in advance, which ensures that the overall timing performance of the global layout result before the detailed layout is more optimized than that in the traditional technology, and reduces the possibility that the overall timing performance of the user netlist after the detailed layout cannot meet the standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0021] Figure 1 is a flow chart of a programmable logic device layout optimization method according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a boundary box of a programmable logic device layout optimization method according to an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of the structure of a programmable logic device layout optimization device in one embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a computer device in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In one embodiment, if Figure 1 As shown, a programmable logic device layout optimization method is provided, comprising the following steps S101 to S105:

[0027] S101. Obtain design units that do not meet preset timing requirements from a user netlist, arrange the design units in descending or ascending order according to their timing performance, and then classify them to generate a design unit set.

[0028] In this embodiment, an FPGA chip, which is one of the programmable logic devices, is taken as an example for description.

[0029] Among them, in the traditional technology, when optimizing the timing of FPGA chip design, the timing cannot be further optimized after several rounds of iterative adjustment, that is, the timing of the collected candidate points is not better than the existing layout position; at this time, the design units that do not meet the preset timing requirements in the user netlist are classified, and then arranged in ascending or descending order according to the timing performance of the design units, and finally a sorted design unit set is obtained; when the number of iterative adjustments meets the preset number of iterations, the design units that do not meet the preset timing requirements are obtained from the user netlist, and the design units are arranged in descending or ascending order according to the timing performance and then classified to generate a design unit set.

[0030] After the design units are classified, the relative relationship of the existing layout positions of the classified design units will be stored, and in the subsequent layout adjustment process, the relative relationship will be retrieved and the design units will be moved as a whole according to the relative relationship.

[0031] S102: Selecting the design units with poor timing performance as key units according to a preset ratio from the sorted design unit set, and classifying the key units to generate a key unit set.

[0032] Among them, after the design units in the design unit set are sorted according to the timing performance, the design unit with the worst timing performance in the design unit set can be clearly judged; then the number of the design units that need to be taken out is calculated according to the number of the design units in the design unit set and the preset ratio; finally, in the design unit set, the design units are taken out in sequence according to the timing performance from worst to best until the number of the design units that have been taken out reaches the number of the design units that need to be taken out.

[0033] S103: construct candidate position points for the key units in the key unit set according to a preset calculation method and generate a candidate position point set.

[0034] Furthermore, the step of constructing candidate position points for the key units in the key unit set according to a preset calculation method and generating a set of candidate position points includes:

[0035] Acquire an input unit and an output unit connected to the key unit and having a timing to the key unit that is less than a preset first timing value, and calculate unweighted average coordinates of the input unit and the output unit;

[0036] Calculating weights according to the timing information of the key units, and then calculating weighted average coordinates of the input unit and the output unit according to the weights and the unweighted average coordinates;

[0037] A bounding box is constructed according to the weighted average coordinates of the input unit and the output unit, and a center point of the bounding box is used as the candidate position point.

[0038] Furthermore, the step of calculating the weight according to the timing information of the key unit includes:

[0039] The timing information after the key unit transformation is calculated by the following formula:

[0040]

[0041] Wherein, t represents the initial timing information of the key unit, and T represents the timing information after the key unit is transformed;

[0042] The weight of the key unit is calculated by the following formula:

[0043]

[0044] Among them, w j represents the weight of the jth key unit.

[0045] Further, the step of calculating the weighted average coordinates of the input unit and the output unit according to the weight and the unweighted average coordinate comprises:

[0046] The control variable in the x-axis direction is calculated according to the following formula:

[0047]

[0048] Among them, flag x Represents the control scalar in the x-axis direction, t d represents the timing information of the input unit or the output unit, x d represents the x-axis coordinate of the input unit or the output unit, x c represents the x-axis coordinate of the key unit;

[0049] The control variable in the y-axis direction is calculated according to the following formula:

[0050]

[0051] Among them, flag y Represents the control scalar in the y-axis direction, y d represents the y-axis coordinate of the input unit or the output unit, y c represents the y-axis coordinate of the key unit;

[0052] The x-axis coordinate of the weighted average coordinate is calculated according to the following formula:

[0053] x'j =(1+flag x *w j )*x j

[0054] Among them, x j represents the unweighted x-axis average coordinate of the input unit and the output unit, x' j represents the weighted x-axis average coordinates of the input unit and the output unit;

[0055] The y-axis coordinate of the weighted average coordinate is calculated according to the following formula:

[0056] y' j =(1+flag y *w j )*y j

[0057] Among them, y j represents the unweighted y-axis average coordinate of the input unit and the output unit, y' j Represents the weighted y-axis average coordinate of the input unit and the output unit.

[0058] Furthermore, the step of constructing a bounding box according to the weighted average coordinates of the input unit and the output unit and taking the center point of the bounding box as the candidate position point includes:

[0059] Filter out the input unit and the output unit whose timing of the candidate position point is less than a preset second timing threshold, and obtain a boundary unit set;

[0060] constructing a bounding box according to weighted average coordinates of the input unit and the output unit in the bounding unit set;

[0061] The center point of the bounding box is calculated and used as the candidate position point.

[0062] Among them, Figure 2 As shown, 204 is an output unit greater than a preset second timing threshold, 201, 202, are output units less than the preset second timing threshold, 203, 205 are input units less than the preset second timing threshold; the boundary unit set is generated according to the output unit 201, the output unit 202, the input unit 203 and the input unit 205; 207 is a bounding box constructed according to the weighted average coordinates of the input unit and the output unit in the boundary unit set; 206 is the center point of the bounding box 207, and the center point 206 is used as the candidate position point.

[0063] Among them, for the candidate position point, the candidate position point is added into the candidate position point set only when the timing performance of the candidate position point is better than the original layout position.

[0064] S104: Determine a candidate location point with the best timing performance from the candidate location point set for layout.

[0065] Furthermore, the step of determining a candidate location point with the best timing performance from the candidate location point set for layout further includes:

[0066] The user netlist obtained after layout of the candidate position points with the best timing performance is saved in the user netlist set.

[0067] S105, looping the steps of obtaining the design units that do not meet the preset timing requirements from the user netlist to determining the candidate position points with the best timing performance from the candidate position point set for layout, until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirements, to obtain the optimization result of the global layout.

[0068] Furthermore, after the loop is finished, a user netlist with the best timing performance is obtained from the user netlist set as an optimization result of the global layout.

[0069] Among them, during the loop process, as long as the overall timing of the user netlist is within the preset timing tolerance range, the user netlist adjusted in the current round of loop will be placed in the user netlist set and used as the initial user netlist for adjustment in the next round of loop.

[0070] Among them, the above-mentioned programmable logic device layout optimization method will be executed during the global layout process of the FPGA chip design, and will also be executed after the global layout process of the FPGA chip design is completed, to ensure that the timing performance of the final global layout is the most optimized result.

[0071] Among them, it should be pointed out in particular that the number of executions of the programmable logic device layout optimization method is not limited, that is, the programmable logic device layout optimization method is executed at least once during the global layout process of the FPGA chip design, and at least once after the global layout process of the FPGA chip design is completed.

[0072] The programmable logic device layout optimization method proposed in this embodiment is executed once during the global layout process of FPGA chip design and once after the global layout process. The design units with poor timing performance in the user netlist are classified, and then the weighted average coordinates of the input units and output units connected to the design units are obtained by a preset calculation method. After screening the input units and the output units, a bounding box is constructed to determine the center point as the pre-adjusted candidate position point. Finally, the only candidate position point with the best timing is determined as the adjusted position point, and the user netlist with the best overall timing in the iterative adjustment process of the user netlist is used as the final user netlist layout result. The timing performance optimization performed in the detailed layout process of the traditional FPGA chip design is advanced to the global layout process, and the restriction conditions of the candidate position points are narrowed to obtain more candidate position points, so that a global layout result with more optimized timing performance can be obtained, that is, the layout result obtained by using the programmable logic device layout optimization method of this embodiment in the global layout process of the traditional FPGA chip design has a more optimized timing performance than the layout result obtained by directly performing the original global layout process in the traditional technology.

[0073] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0074] In one embodiment, a programmable logic device layout optimization device 30 is provided, and the programmable logic device layout optimization device 30 corresponds one-to-one to the programmable logic device layout optimization method in the above embodiment. Figure 3 As shown, the programmable logic device layout optimization device 30 includes a design unit classification module 301, a key unit classification module 302, a candidate location point calculation module 303, an optimal candidate location point layout module 304 and a loop module 305. The functional modules are described in detail as follows:

[0075] The design unit classification module 301 is used to obtain design units that do not meet the preset timing requirements from the user netlist, and classify the design units after arranging them in descending or ascending order according to the timing performance to generate a design unit set;

[0076] A key unit classification module 302 is used to select the design units with poor timing performance from the design unit set according to a preset ratio as key units, and classify the key units to generate a key unit set;

[0077] A candidate location point calculation module 303, configured to construct candidate location points for the key units in the key unit set and generate a candidate location point set according to a preset calculation method;

[0078] The optimal candidate position point layout module 304 is used to determine the candidate position point with the best timing performance from the candidate position point set for layout;

[0079] The loop module 305 is used to loop the steps of obtaining the design units that do not meet the preset timing requirements from the user netlist to determining the candidate position points with the best timing performance from the candidate position point set for layout, until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirements, to obtain the optimization result of the global layout.

[0080] Furthermore, the candidate location point set generation module 303 includes:

[0081] An unweighted average coordinate calculation submodule, used to obtain an input unit and an output unit connected to the key unit and having a timing to the key unit less than a preset first timing value, and calculate the unweighted average coordinates of the input unit and the output unit;

[0082] A weighted average coordinate calculation submodule, used to calculate the weight according to the timing information of the key unit, and then calculate the weighted average coordinates of the input unit and the output unit according to the weight and the unweighted average coordinate;

[0083] The candidate position point calculation submodule is used to construct a bounding box according to the weighted average coordinates of the input unit and the output unit, and use the center point of the bounding box as the candidate position point.

[0084] Furthermore, the weighted average coordinate calculation submodule also includes:

[0085] The timing transformation calculation subunit is used to calculate the timing information after the transformation of the key unit by the following formula:

[0086]

[0087] Wherein, t represents the initial timing information of the key unit, and T represents the timing information after the key unit is transformed;

[0088] The weight calculation subunit is used to calculate the weight of the key unit by the following formula:

[0089]

[0090] Among them, w j Represents the weight of the jth key unit.

[0091] Furthermore, the weighted average coordinate calculation submodule also includes:

[0092] The x-axis control variable calculation subunit is used to calculate the control variable in the x-axis direction according to the following formula:

[0093]

[0094] Among them, flag x Represents the control scalar in the x-axis direction, t d represents the timing information of the input unit or the output unit, x d represents the x-axis coordinate of the input unit or the output unit, x c represents the x-axis coordinate of the key unit;

[0095] The y-axis control variable calculation subunit is used to calculate the control variable in the y-axis direction according to the following formula:

[0096]

[0097] Among them, flag y Represents the control scalar in the y-axis direction, y d represents the y-axis coordinate of the input unit or the output unit, y c represents the y-axis coordinate of the key unit;

[0098] The x-axis weighted average coordinate calculation subunit is used to calculate the x-axis coordinate of the weighted average coordinate according to the following formula:

[0099] x' j =(1+flag x *w j )*x j

[0100] Among them, x j represents the unweighted x-axis average coordinate of the input unit and the output unit, x' j represents the weighted x-axis average coordinates of the input unit and the output unit;

[0101] The y-axis weighted average coordinate calculation subunit is used to calculate the y-axis coordinate of the weighted average coordinate according to the following formula:

[0102] y' j =(1+flag y *w j )*y j

[0103] Among them, y j represents the unweighted y-axis average coordinate of the input unit and the output unit, y' j Represents the weighted y-axis average coordinate of the input unit and the output unit.

[0104] Furthermore, the candidate position point calculation submodule also includes:

[0105] A boundary unit set generation subunit is configured to screen out the input unit and the output unit whose timing of the candidate position point is less than a preset second timing threshold, and obtain a boundary unit set;

[0106] A bounding box construction subunit, constructing a bounding box according to weighted average coordinates of the input unit and the output unit in the bounding unit set;

[0107] The candidate position point determination subunit calculates the center point of the bounding box and uses the center point as the candidate position point.

[0108] Furthermore, the optimal candidate location point layout module 304 further includes:

[0109] A user netlist set storage subunit saves the user netlist obtained after layout of the candidate position points determined each time into the user netlist set during the loop process;

[0110] The global layout optimal result determination subunit obtains the user netlist with the best timing performance in the user netlist set as the optimization result of the global layout after the cycle is completed.

[0111] The meaning of "first" and "second" in the above modules / units is only to distinguish different modules / units, and is not used to define which module / unit has a higher priority or other limiting meanings. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules in this application is only a logical division, and there may be other division methods when implemented in actual applications.

[0112] For the specific definition of the programmable logic device layout optimization device, please refer to the definition of the programmable logic device layout optimization method above, which will not be repeated here. Each module in the above-mentioned programmable logic device layout optimization device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0113] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the programmable logic device layout optimization method in the above embodiment are implemented, such as Figure 1 Steps S101 to S105 and other extensions of the method and related steps are shown. Alternatively, when the processor executes the computer program, the functions of each module / unit of the programmable logic device layout optimization device in the above embodiment are realized, for example Figure 3 The functions of modules 301 to 305 are shown in Figure 3. To avoid repetition, they are not described here.

[0114] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the computer device, and various interfaces and lines are used to connect various parts of the entire computer device.

[0115] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the computer device by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a text editing function, an image drawing function, etc.), etc.; the data storage area can store data created according to the use of the computer device (such as text data, image data, etc.), etc.

[0116] The memory may be integrated into the processor or may be arranged separately from the processor.

[0117] In one embodiment, a computer-readable storage medium is provided on which a computer program is stored. When the computer program is executed by a processor, the steps of the programmable logic device layout optimization method in the above embodiment are implemented, such as Figure 1Alternatively, when the computer program is executed by a processor, the functions of each module / unit of the programmable logic device layout optimization device in the above embodiment are realized, for example, Figure 3 The functions of modules 301 to 305 are shown in Figure 3. To avoid repetition, they are not described here.

[0118] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0119] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0120] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for optimizing the layout of a programmable logic device, characterized in that: include: Acquire design units that do not meet preset timing requirements from a user netlist, sort the design units in descending or ascending order according to timing performance, and then classify them to generate a set of design units; Selecting the design units with poor timing performance as key units according to a preset ratio from the sorted design unit set, and classifying the key units to generate a key unit set; Constructing candidate position points for the key units in the key unit set and generating a set of candidate position points according to a preset calculation method; Determine a candidate location point with the best timing performance from the candidate location point set for layout; The steps of obtaining the design unit that does not meet the preset timing requirement from the user netlist to determining the candidate position point with the best timing performance from the candidate position point set for layout are repeated until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirement, thereby obtaining the optimization result of the global layout; Among them, the step of constructing candidate position points for the key units in the key unit set according to a preset calculation method and generating a set of candidate position points includes: obtaining an input unit and an output unit that are connected to the key unit and whose timing to the key unit is less than a preset first timing value, and calculating the unweighted average coordinates of the input unit and the output unit; calculating the weight according to the timing information of the key unit, and then calculating the weighted average coordinates of the input unit and the output unit according to the weight and the unweighted average coordinates; constructing a bounding box according to the weighted average coordinates of the input unit and the output unit, and taking the center point of the bounding box as the candidate position point.

2. The programmable logic device layout optimization method according to claim 1, characterized in that: The step of calculating the weight according to the timing information of the key unit comprises: The timing information after the key unit transformation is calculated by the following formula: Wherein, t represents the initial timing information of the key unit, and T represents the timing information after the key unit is transformed; The weight of the key unit is calculated by the following formula: Among them, w j Represents the weight of the jth key unit.

3. The programmable logic device layout optimization method according to claim 2, characterized in that: The step of calculating the weighted average coordinates of the input unit and the output unit according to the weights and the unweighted average coordinates comprises: The control variable in the x-axis direction is calculated according to the following formula: Among them, flag x Represents the control scalar in the x-axis direction, t d represents the timing information of the input unit or the output unit, x d represents the x-axis coordinate of the input unit or the output unit, x c represents the x-axis coordinate of the key unit; The control variable in the y-axis direction is calculated according to the following formula: Among them, flag y Represents the control scalar in the y-axis direction, y d represents the y-axis coordinate of the input unit or the output unit, y c represents the y-axis coordinate of the key unit; The x-axis coordinate of the weighted average coordinate is calculated according to the following formula: x' j =(1+flag x *w j )*x j Among them, x j represents the unweighted x-axis average coordinate of the input unit and the output unit, x' j represents the weighted x-axis average coordinates of the input unit and the output unit; The y-axis coordinate of the weighted average coordinate is calculated according to the following formula: y' j =(1+flag y *w j )*y j Among them, y j represents the unweighted y-axis average coordinate of the input unit and the output unit, y' j Represents the weighted y-axis average coordinate of the input unit and the output unit.

4. The programmable logic device layout optimization method according to claim 1, characterized in that: The step of constructing a bounding box according to the weighted average coordinates of the input unit and the output unit and taking the center point of the bounding box as the candidate position point comprises: Filter out the input unit and the output unit whose timing of the candidate position point is less than a preset second timing threshold, and obtain a boundary unit set; constructing a bounding box according to weighted average coordinates of the input unit and the output unit in the bounding unit set; The center point of the bounding box is calculated and used as the candidate position point.

5. The programmable logic device layout optimization method according to claim 1, characterized in that: The step of determining a candidate location point with the best timing performance from the candidate location point set for layout further includes: In the loop process, the user netlist obtained after layout of the candidate position points determined each time is saved in the user netlist set; After the loop is finished, the user netlist with the best timing performance is obtained from the user netlist set as the optimization result of the global layout.

6. A programmable logic device layout optimization device, characterized in that: include: A design unit classification module is used to obtain design units that do not meet the preset timing requirements from the user netlist, and classify the design units after arranging them in descending or ascending order according to the timing performance to generate a design unit set; A key unit classification module, used for selecting the design units with poor timing performance as key units according to a preset ratio from the sorted design unit set, and classifying the key units to generate a key unit set; A candidate position point calculation module, used to construct candidate position points for the key units in the key unit set and generate a candidate position point set according to a preset calculation method; An optimal candidate location point layout module, used to determine the candidate location point with the best timing performance from the candidate location point set for layout; A loop module, used for looping the steps of obtaining the design unit that does not meet the preset timing requirement from the user netlist to determining the candidate position point with the best timing performance from the candidate position point set for layout, until the number of iterations reaches the preset maximum number of iterations, or the design units all meet the preset timing requirement, and obtaining the optimization result of the global layout; Among them, the candidate position point calculation module includes: an unweighted average coordinate calculation submodule, which is used to obtain an input unit and an output unit that are connected to the key unit and whose timing to the key unit is less than a preset first timing value, and calculate the unweighted average coordinates of the input unit and the output unit; a weighted average coordinate calculation submodule, which is used to calculate the weight according to the timing information of the key unit, and then calculate the weighted average coordinates of the input unit and the output unit according to the weight and the unweighted average coordinate; the candidate position point calculation submodule, which is used to construct a bounding box according to the weighted average coordinates of the input unit and the output unit, and take the center point of the bounding box as the candidate position point.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the programmable logic device layout optimization method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the programmable logic device layout optimization method according to any one of claims 1 to 5 are implemented.

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