Circuit Design Method, Platform and Terminal Device

Abstract

Embodiments of the present application provide a circuit design method, platform and terminal device. Among them, the method includes: determining the initial coordinates of unknown nodes according to the initial coordinates of known nodes; mapping all nodes to the area to be laid out according to the initial coordinates of all nodes to generate a layout diagram; evenly dividing the area to be laid out into several sub-areas; moving the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number, so as to update the layout diagram, making the quality of the layout higher and without the need for manual intervention.

Description

Technical Field

[0001] This application belongs to the technical field of circuit design, and particularly relates to a circuit design method, platform and terminal device. Background Art

[0002] When performing layout and routing design, it is necessary to layout each logic module of the designed circuit, that is, the corresponding placement positions of each logic module or device on the silicon wafer, and then electrically connect each logic unit with wires, that is, the routing process, to complete the layout design of the integrated circuit.

[0003] Common layout and routing methods are generally divided into three types: automatic layout and routing. For example, after setting relevant rule requirements in the design software, the design software automatically performs layout and routing; manual layout and routing, that is, all layout and routing are completed manually by the designer, which requires high requirements for the designer and is extremely time-consuming; interactive layout and routing, which is between the first two methods, is to perform manual intervention by the designer on the basis of automatic layout and routing, or automatically perform part of the layout and routing, and the remaining part is completed manually by the designer. In recent years, with the rapid development of circuit manufacturing technology, the circuit integration level and complexity have been continuously increasing, the number of wire networks integrated in a circuit has been continuously increasing and the density has been continuously increasing, making the routing more and more difficult.

[0004] Existing circuit layout or routing algorithms need to be continuously iterated, with slow speed, and cannot achieve layout or automatic routing. In many cases, the layout or routing results still require manual intervention. Therefore, designing an effective method that can handle layout or routing with the number of units reaching the million level has become a key issue in circuit electronic design automation. Summary of the Invention

[0005] The embodiments of this application provide a circuit design method, platform and terminal device, which can effectively improve the efficiency of circuit layout and routing.

[0006] In the first aspect, the embodiments of this application provide a circuit design method, including:

[0007] Determine the initial coordinates of unknown nodes according to the initial coordinates of known nodes;

[0008] Map all nodes to the area to be laid out according to the initial coordinates of all nodes to generate a layout diagram;

[0009] Evenly divide the area to be laid out into several sub-areas;

[0010] Move the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout diagram.

[0011] In the second aspect, the embodiments of this application provide a circuit design platform, including:

[0012] A coordinate module, configured to determine the initial coordinates of unknown nodes according to the initial coordinates of known nodes;

[0013] A mapping module, configured to map all nodes to the area to be laid out according to the initial coordinates of all nodes, and generate a layout diagram;

[0014] A zoning module, configured to evenly divide the area to be laid out into several sub-areas;

[0015] An adjustment module, configured to move nodes according to the number of nodes in each sub-area, so that the total number of nodes in all sub-areas does not exceed a preset number, to update the layout diagram.

[0016] In a third aspect, an embodiment of the present application provides a terminal device, a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the circuit design method according to any one of the above first aspects is implemented.

[0017] In a fourth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a terminal device, the terminal device is enabled to execute the circuit design method according to any one of the above first aspects.

[0018] It can be understood that the beneficial effects of the above second aspect to the fourth aspect can refer to the relevant descriptions in the above first aspect, and will not be repeated here.

[0019] The beneficial effect of the embodiment of the present application compared with the prior art is:

[0020] In the embodiment of the present application, the initial coordinates of unknown nodes are determined according to the initial coordinates of known nodes; according to the initial coordinates of all nodes, all nodes are mapped to the area to be laid out to generate a layout diagram; the area to be laid out is evenly divided into several sub-areas; according to the number of nodes in each sub-area, the nodes are moved so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout diagram, so that the quality of the layout is higher and no manual intervention is required. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0022] Figure 1 It is a schematic flowchart of a circuit design method provided by an embodiment of the present application;

[0023] Figure 2 It is a schematic diagram of node coordinates of a circuit design method provided by an embodiment of the present application;

[0024] Figure 3 It is a schematic diagram of node movement of a circuit design method provided by an embodiment of the present application;

[0025] Figure 4 It is a schematic diagram of the structure of a circuit design platform provided by an embodiment of the present application;

[0026] Figure 5 It is a schematic diagram of the structure of a terminal device provided by an embodiment of the present application. Detailed implementation manners

[0027] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system architectures and technologies are presented in order to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0028] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0029] It should also be understood that the term "and / or" as used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0030] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if the described condition or event is detected" can be interpreted as meaning "once determined", "in response to determining", "once the described condition or event is detected", or "in response to detecting the described condition or event" according to the context.

[0031] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" in the description of the present application mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0033] In the embodiments of the present application, the pins to be connected in the circuit to be laid out are regarded as a node within the circuit layout range.

[0034] As Figure 1 shown in the schematic flowchart of the circuit design method provided by an embodiment of the present application, which includes:

[0035] Step S101: Determine the initial coordinates of the unknown nodes according to the initial coordinates of the known nodes. Specifically, it includes:

[0036] First, obtain the initial coordinates of the nodes with determined positions. For a chip, among all the nodes to be laid out and wired, the positions of some nodes are determined in advance, and the positions of some nodes are to be laid out. Usually, the input / output IO modules need to be determined in advance according to the design requirements. For example, according to the needs of the application scenario, the power input position has been uniquely specified, or its signal output position has been uniquely specified. Then the node coordinate positions corresponding to the power input or signal output are determined, and the corresponding coordinates are known in advance. In the subsequent adjustment and iteration, the coordinates of the nodes in the IO module will not change either.

[0037] Then, based on the initial coordinates of the known nodes, generate the initial coordinates corresponding to the unknown nodes to be laid out.

[0038] As Figure 2 shown in the schematic diagram of the node coordinates, where A, B, E, and F are nodes with determined positions, and the known coordinates of A, B, E, and F are (Xa, Ya), (Xb, Yb), (Xe, Ye), and (Xf, Yf) respectively, and C and D are nodes to be laid out, and the logical unit coordinates corresponding to C and D are (Xc, Yc) and (Xd, Yd) respectively.

[0039] Φ = (Xc - Xa) 2 + 2(Xc - Xb) 2 +(Xd - Xe) 2 + 2(Xd - Xf) 2

[0040] Take the partial derivatives of \(X_c\) and \(X_d\) respectively, and set the partial derivatives to 0, that is:

[0041]

[0042]

[0043] The abscissas of points C and D can be solved.

[0044] Similarly, \(\varPhi\) ＇ =(Y_c - Y_a) 2 + 2(Y_c - Y_b) 2 +(Y_d - Y_e) 2 + 2(Y_d - Y_f) 2

[0045] Take the partial derivatives of \(Y_c\) and \(Y_d\) respectively, and set the partial derivatives to 0, that is:

[0046]

[0047]

[0048] The ordinates of points C and D can be solved

[0049] At this time, A, B, C, D, E, and F are all nodes with determined positions, and the corresponding coordinates are known coordinates. Furthermore, the logical unit coordinates corresponding to all the nodes to be placed can be obtained by iterating multiple times, thereby determining the initial coordinates of all the nodes to be routed in the layout.

[0050] When the initial coordinates of an unknown node are required, at least two known fixed points are needed. Optionally, the initial coordinates of each node are calculated by the same number of fixed points. For example, each node is calculated according to 2 known fixed points or all are calculated according to 4 known fixed points.

[0051] Step S102: Map all the nodes to the area to be laid out according to the initial coordinates of all the nodes, and generate a layout diagram.

[0052] Step S103: Divide the area to be laid out into several sub-areas on average.

[0053] In the embodiment of the present application, the entire area to be laid out is evenly divided into several sub-areas according to the area. Each sub-area can also be called a BOX. The maximum number of nodes that each BOX can accommodate is limited. In the embodiment of the present application, the maximum number of nodes that a BOX can accommodate is called the capacity.

[0054] Step S104: Move the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed the preset number, so as to update the layout diagram.

[0055] If, after mapping according to the initial coordinates, the total number of nodes in some BOXes exceeds the preset number, it is considered that there are dense nodes in the BOX, and the dense nodes need to be moved to other BOXes with fewer nodes. The dense nodes can be called nodes to be moved, so that all nodes are reasonably dispersed on the area to be laid out, rather than concentrated in a few BOXes. Specifically, it includes:

[0056] Step S1041: If the total number of nodes in any sub-region exceeds the preset number, determine the number of nodes to be moved in the any sub-region.

[0057] The preset number can be flexibly set. For example, it can be the capacity of the sub-region or less than the capacity of the sub-region.

[0058] Optionally, as Figure 3 shown in the schematic diagram of node movement:

[0059]

[0060] Where M is the number of nodes to be moved that need to be moved, Ln is the sum of the number of nodes in the BOXes on the left side of the cutting line, Rn is the sum of the number of nodes in the BOXes on the right side of the cutting line, Lb is the capacity of the BOX on the left side of the cutting line, and Rb is the capacity of the BOX on the right side of the cutting line.

[0061] Step S1042: Determine the first new coordinates of the nodes to be moved according to the number of the nodes to be moved.

[0062] Then the following equations can be established for the nodes on both sides of the cutting line respectively:

[0063] Left:

[0064] Right:

[0065] Where W is the width of a single BOX, and C b represents the capacity of a single BOX.

[0066] Where x max , x min respectively represent the leftmost coordinate of the BOX grid in the sub-region on the left side of the cutting line and the rightmost coordinate of the BOX grid in the sub-region on the right side of the cutting line, and x ori , x new respectively represent the initial coordinates and the first new coordinates of the nodes. Then the distance that the nodes need to move is: |x new - x ori |.

[0067] Optionally, dense nodes to be moved are randomly selected. For example, if the number of nodes in the BOX on the left side of the cutting line is 2 more than the capacity, then 2 nodes are randomly selected from all the nodes in the left BOX and moved to the right. If the number of nodes in the BOX on the right side of the cutting line is 2 more than the preset capacity, then 2 nodes are randomly selected from all the nodes in the right BOX and moved to the left.

[0068] Optionally, after moving the dense nodes, the difference in the number of all BOX nodes on both sides of the cutting line meets a preset condition, and the preset condition is Ln - Rn ≤ N, where N can be flexibly set according to the actual situation and is optionally a natural number greater than 1 and less than 5. That is, after each node is moved, the number of nodes in the BOXes on both sides of the dotted line meets this preset condition simultaneously before moving the next node. By setting this preset condition, the distribution of nodes can be made more reasonable and uniform, and at the same time, the balance of the number of nodes in the BOXes on both sides of the dotted line does not need to be strictly emphasized.

[0069] Step S1043: If when the node to be moved moves from the initial coordinate to the first new coordinate, the component to which the node to be moved belongs coincides with other components, adjust the first new coordinate.

[0070] The specific adjustment steps include:

[0071] Set a first virtual point in a first direction separated from the first new coordinate, and the difference between the coordinates of the first virtual point and the first new coordinate is equal to the difference between the first new coordinate and the initial coordinate of the node to be moved |x new -x ori |.

[0072] Determine the second new coordinate of the node to be moved according to the first distance formula and the coordinates of the first virtual point;

[0073] If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs does not coincide with other components, update the coordinate of the node to be moved to the second new coordinate;

[0074] If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs coincides with other components and F f +F r > 0, return to the step of determining the second new coordinate of the node to be moved according to the first distance formula and the coordinates of the first virtual point, that is, continue to update the value of d f to continue adjusting the position of the node;

[0075] If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs coincides with other components and Ff +F r ≤0, reset the position of the node, and set a second virtual point in a second direction separated from the first new coordinate. The second direction is perpendicular to the first direction. The virtual point is set in a direction that can separate the coincident nodes, optionally the left - right direction or the up - down direction. For example, when adjusting the node position along the left - right direction, if F f +F r ≤0 and the components to which different nodes belong still coincide, reset the position of the node and set the second virtual point in the up - down direction. In the embodiments of the present application, the virtual point is not directly set in a direction with an angle, because the combination of the left - right direction and the horizontal movement is a movement in a direction with an angle.

[0076] Determine the third new coordinate of the node to be moved according to the second distance formula and the coordinates of the second virtual point;

[0077] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs does not coincide with other components, update the coordinate of the node to be moved to the third new coordinate;

[0078] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r >0, return to the step of determining the third new coordinate of the node to be moved according to the second distance formula and the coordinates of the second virtual point, that is, continue to adjust the position of the node;

[0079] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r ≤0, move the node to be moved from the second new coordinate to the sparse sub - region of the to - be - laid - out region. The sparse sub - region is a sub - region in the to - be - laid - out region where the number of nodes is less than a preset threshold or the blank area is larger than the area of the component to which the node to be moved belongs. Optionally, traverse the to - be - laid - out region and preferentially select a sub - region with a small number of nodes and a large blank area.

[0080] Among them, the first distance formula is:

[0081]

[0082] The second distance formula is:

[0083]

[0084] F f =ω f*d fn ,F f＇ = ω f＇ *d fn＇ , -3 < ω f < 0, -3 < ω f＇ < 0

[0085] d fn is the distance between the first virtual point and the second new coordinate, d fn The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, d fn＇ is the distance between the second virtual point and the third new coordinate, d fn＇ The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, Fr is the total fixing force received by the coincident nodes to be moved, and the second direction is perpendicular to the first direction.

[0086] F F and F f＇ are virtual forces and are negative values.

[0087] Among them, if there are n corresponding known nodes associated with it, Fn is the fixing force between the node and the associated known nodes, Fr is the total fixing force received by the node, and the total fixing force

[0088] If a node has two corresponding known nodes associated with it, then there are two sets of corresponding fixing forces. We assume that the fixing forces between the two nodes associated with the node are F1 and F2 respectively. Finally, the total fixing force received by this node can be expressed as:

[0089]

[0090] Fr is a positive value and can be regarded as an inherent property of the coincident nodes.

[0091] In the embodiments of the present application, when the components to which different nodes belong coincide, the two different nodes corresponding thereto are called coincident nodes. In the embodiments of the present application, by setting virtual points, d f is continuously increased f to increase the virtual force, push the coincident nodes in the direction of separating from the coincidence, and then pull apart the coincident components. It can be understood that as long as the position of any one of the coincident nodes is changed, the coincident nodes are no longer coincident. Each time the value of d f is updated, that is, the position of the node is adjusted once. After each adjustment, it is judged whether the components to which different nodes belong coincide. If they do not coincide, the process stops. During this process, if F r≤0, and still unable to achieve non - overlap, then reset the position of the node, set the virtual point in the other direction, and repeat the above operations again. For example: for the first time, the components are pulled apart horizontally. If the goal of separating the overlapping components is not achieved, the overlapping components can be pulled apart vertically.

[0092] Step S105: Determine the escape route for each node according to the cost function, so as to route the updated layout diagram.

[0093] For all the nodes to be laid out and routed, the escape routes need to be determined. We need to determine the escape routes of each node one by one. The specific process is as follows:

[0094] Step S1051: For any node, select available resource points in the escape direction from the node to the boundary point.

[0095] Step S1052: According to the cost function, calculate the escape cost of each resource point, and save the resource point corresponding to the minimum escape cost into the resource point set.

[0096] Cost(i)=(1 - ω)·G(i)+ω·D(i)

[0097] Among them, G(i) is the real movement cost of the node, that is, the real movement cost from the node to the resource point, D(i) is the estimated movement cost from the resource point to the termination node. Optionally, the movement cost is the Manhattan distance between two nodes, and the termination node is the boundary point.

[0098]

[0099] Step S1053: If the resource point corresponding to the minimum escape cost is the boundary point, connect the resource points in the resource point set in the order of saving the resource point corresponding to the minimum escape cost to complete the route optimization of the node; if the resource point corresponding to the minimum escape cost is not the boundary point, update the resource point corresponding to the minimum escape cost as the node, and return to execute Step S1041: Select available resource points in the escape direction from the node to the boundary point.

[0100] If the quality of layout and routing meets the preset conditions, end;

[0101] If the quality of layout and routing does not meet the preset conditions, then move any two nodes with logical relationships in turn to shorten the wire length between the two nodes. According to the circuit design diagram, it can be known whether there is a logical relationship between each node. In the embodiment of the present application, two nodes with logical relationships are taken as a logical group, and the two nodes with logical relationships in the group are moved in turn. For example, if node 1 has logical relationships with nodes 2, 5, and 11, then take 1 and 2 as a group, 1 and 5 as a group, and 1 and 11 as a group in turn, and move each node in the group to shorten the wire length between the two nodes in the group. Specifically, it includes:

[0102] In the embodiment of the present application, the escape direction of node A is the boundary direction. Node A is connected to the boundary through a connection line, and the intersection point of the connection line and the boundary is used as boundary point a, X a is the abscissa of boundary point a, Y a is the ordinate of boundary point a, X A is the abscissa of node A, Y A is the ordinate of node A. Among them, the connection line is a straight line perpendicular to the boundary.

[0103] The process of determining the escape order is as follows:

[0104] First, according to the estimation function, determine the escape estimation cost of node A.

[0105] The estimation function is: Cost A =|X A -X a |+|Y A- Y a |

[0106] Among them, Cost A represents the escape estimation cost of the node A to be escaped.

[0107] Then, sort all the nodes to be escaped in ascending order of the escape estimation cost as the escape order of the nodes.

[0108] Select the node with the lowest escape cost in the i-th movement order set as the minimum node, and move each logical group corresponding to the minimum node in turn in groups. The logical group includes two nodes with logical relationships, specifically including:

[0109] Set up a first candidate box based on the minimum node in the i-th movement order set, and move the first candidate box towards the boundary with a first preset step length; if there is no available node in the candidate box, keep the minimum node still; if there is an available node in the candidate box and the escape cost of the available node is greater than the escape cost of the minimum node, continue to move the first candidate box until an available node with an escape cost less than the escape cost of the minimum node is encountered. The size of the first candidate box can be set flexibly and can optionally be equal to the size of the component to which the node belongs.

[0110] Set up a second candidate box based on another node in the logical grouping corresponding to the smallest node, and move the second candidate box towards the boundary with a second preset step size; if there is no available node within the second candidate box, keep the other node stationary; if there is an available node within the second candidate box and the escape cost of the available node is greater than the escape cost of the other node, continue to move the second candidate box until an available node with an escape cost less than that of the other node is encountered.

[0111] For example, if the escape directions of two logically related nodes are both left and right, the candidate box moves up or down simultaneously; if the escape directions of two logically related nodes are both up and down, the candidate box moves left or right simultaneously; if the escape directions of two logically related nodes are left and up respectively, the candidate box moves up and left respectively; if the escape directions of two logically related nodes are left and down respectively, the candidate box moves down and left respectively; if the escape directions of two logically related nodes are right and up respectively, the candidate box moves up and right respectively; if the escape directions of two logically related nodes are right and down respectively, the candidate box moves down and right respectively.

[0112] It can be understood that the above two steps do not need to limit the order.

[0113] Remove the smallest node from the i-th movement order set, update the i-th movement order set, and take the node with the lowest escape cost in the updated i-th movement order set as the new smallest node;

[0114] Return to execute the step of selecting the node with the lowest escape cost in the i-th movement order set as the smallest node, and move each logical grouping corresponding to the smallest node in turn in groups until there are no nodes in the updated i-th movement order set;

[0115] Where i = 1, 2, 3, 4, all nodes are divided into 4 sets according to the escape direction, and the average value of the escape costs of all nodes in each set is calculated respectively. For example, take the side closest to the boundary of the node as the escape direction. For example, the nodes closer to the left side with the escape direction all being left are in the left set, the nodes closer to the right side with the escape direction all being right are in the right set, the nodes closer to the upper side with the escape direction all being up are in the upper set, and the nodes closer to the lower side with the escape direction all being down are in the lower set. Optionally, the order from low to high of the average values is used as the order of movement of each set. After all the nodes in a set are processed, the remaining sets are processed in turn. Optionally, skip the nodes that have already been moved and only operate on the nodes that have not been moved. After moving each pair of logically related nodes through the above operations, a wiring diagram with optimized layout and wiring will be obtained.

[0116] In the embodiment of the present application, the escape estimation cost is calculated and sorted from low to high to determine the escape order of the nodes, so that the nodes with low escape cost escape first, occupying less resources. If the random escape is adopted instead of this order, the nodes with high cost escape first, occupying more resources, which may occupy the escape path of the nodes with low cost, making the escape path of the nodes with low cost longer, and there may also be path intersections, resulting in escape failure.

[0117] Optionally, in the embodiment of the present application, the ratio η of the actual delay after routing to the expected delay requ is used to represent the quality of the layout:

[0118] η = T / T requ

[0119] where T represents the actual delay after routing, and T requ represents the expected delay that is expected to be achieved. If η < 1, the layout quality meets the preset conditions; otherwise, the layout quality does not meet the preset conditions.

[0120] The routing tree reveals the logical relationships between components in the entire routing graph. Starting from the source node, which nodes are connected to the next level of the source node and whether there are logical connection relationships between nodes can all be obtained from the routing tree. Generally speaking, on a circuit starting from the source node, which node is connected first and then which node it leads to, then these nodes have a sequence on this circuit, and this relationship will be intuitively reflected in the routing tree.

[0121] Among them, S represents the source node (the node where the input power supply is located), and n1, n2, n3, n4 represent the nodes of other chips. Then the delay of the source node S can be expressed by the following formula:

[0122] T del (S) = 0.5·S c ·S r

[0123] Among them, S c , S r represent the capacitance and resistance of the source node itself respectively. Then the delay of other nodes in the routing tree can be expressed by the following formula:

[0124] T del (n) = ∑T del (n pre ) + 0.5·n C ·n R

[0125] n C , n R represent the capacitance and resistance of the current node respectively, and n preis the upper-level node of the current node. For each routing tree, we can use Equation T tree = ∑T del (n) represents the delay of the delay routing graph of the current routing tree, which is not only related to the capacitance and resistance of the components themselves, but also related to the distance between the components. The components are as close as possible within the allowable range, and the time required for current conduction is faster. In the embodiments of the present application, T is used to represent the delay in the entire routing graph:

[0126]

[0127] where T length represents the total bus length in the routing graph, C represents the perimeter of the entire layout range, and n represents the number of nodes.

[0128] It should be noted that other sorting schemes that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should also be within the protection scope of the present invention, and will not be elaborated here one by one.

[0129] See Figure 4 , which is a schematic diagram of a circuit design platform provided by an embodiment of the present application. For the sake of convenience of description, only the parts related to the embodiments of the present invention are shown, including:

[0130] A coordinate module 41, configured to determine the initial coordinates of unknown nodes according to the initial coordinates of known nodes;

[0131] A mapping module 42, configured to map all nodes to the area to be laid out according to the initial coordinates of all nodes, and generate a layout diagram;

[0132] A zoning module 43, configured to evenly divide the area to be laid out into several sub-areas;

[0133] An adjustment module 44, configured to move the nodes according to the number of nodes in each sub-area, so that the total number of nodes in all sub-areas does not exceed a preset number, to update the layout diagram.

[0134] The adjustment module 44 is further configured to, if the total number of nodes in any sub-area exceeds the preset number, determine the number of nodes to be moved in the any sub-area;

[0135] According to the number of nodes to be moved, determine the first new coordinates of the nodes to be moved;

[0136] If the component to which the node to be moved belongs coincides with other components when the node to be moved moves from the initial coordinates to the first new coordinates, adjust the first new coordinates.

[0137] The determining the number of nodes to be moved in the any sub-area includes:

[0138]

[0139] Determining the first new coordinates of the node to be moved according to the number of the nodes to be moved includes:

[0140]

[0141]

[0142] Where M is the number of nodes to be moved, Ln is the sum of the number of nodes in the sub-region BOX on the left side of the cutting line, Rn is the sum of the number of nodes in the sub-region BOX on the right side of the cutting line, Lb is the capacity of the sub-region BOX on the left side of the cutting line, Rb is the capacity of the sub-region BOX on the right side of the cutting line, x max , x min respectively represent the leftmost coordinate of the grid in the sub-region BOX on the left side of the cutting line and the rightmost coordinate of the grid in the sub-region BOX on the right side of the cutting line, and x ori , x new respectively represent the initial coordinates and the first new coordinates of the node.

[0143] The adjustment module 44 is further configured to set a first virtual point in a first direction separated from the first new coordinates, and a difference between coordinates of the first virtual point and the first new coordinates is equal to a difference between the first new coordinates and the initial coordinates of the node to be moved;

[0144] Determine a second new coordinate of the node to be moved according to a first distance formula and coordinates of the first virtual point;

[0145] If when the node to be moved moves from the first new coordinates to the second new coordinates, an element to which the node to be moved belongs does not coincide with other elements, update the coordinates of the node to be moved to the second new coordinates;

[0146] If when the node to be moved moves from the first new coordinates to the second new coordinates, the element to which the node to be moved belongs coincides with other elements and F f + F r > 0, return to the step of determining the second new coordinate of the node to be moved according to the first distance formula and the coordinates of the first virtual point;

[0147] If when the node to be moved moves from the first new coordinates to the second new coordinates, the element to which the node to be moved belongs coincides with other elements and F f + F r ≤ 0, set a second virtual point in a second direction separated from the first new coordinates;

[0148] Determine a third new coordinate of the node to be moved according to a second distance formula and coordinates of the second virtual point;

[0149] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs does not coincide with other components, the coordinate of the node to be moved is updated to the third new coordinate;

[0150] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r > 0, return the step of determining the third new coordinate of the node to be moved according to the second distance formula and the coordinate of the second virtual point;

[0151] If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r ≤0, move the node to be moved from the second new coordinate to the sparse sub-region within the region to be laid out, where the sparse sub-region is a sub-region in the region to be laid out with the number of nodes less than a preset threshold or a sub-region with a blank area larger than the area of the component to which the node to be moved belongs;

[0152] Among them, the first distance formula is:

[0153]

[0154] The second distance formula is:

[0155]

[0156] F f = ω f *d fn F f＇ = ω f＇ *d fn＇ , -3 < ω f < 0, -3 < ω f＇ < 0

[0157] d fn is the distance between the first virtual point and the second new coordinate, d fn The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, d fn＇ is the distance between the second virtual point and the third new coordinate, d fn＇ The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, Fr is the total fixed force received by the coincident nodes to be moved, and the second direction is perpendicular to the first direction.

[0158] The routing module is used to determine the escape route of each node according to the cost function for routing the updated layout graph.

[0159] The routing module is further used to select available resource points in the escape direction from a node to a boundary point for any node;

[0160] Calculate the escape cost of each resource point according to the cost function, and save the resource point corresponding to the minimum escape cost to the resource point set;

[0161] If the resource point corresponding to the minimum escape cost is a boundary point, connect the resource points in the resource point set in the order in which the resource point corresponding to the minimum escape cost is saved to the resource point set;

[0162] If the resource point corresponding to the minimum escape cost is not a boundary point, update the resource point corresponding to the minimum escape cost to a node, and return to execute the step of selecting available resource points in the escape direction from the node to the boundary point.

[0163] The cost function is:

[0164] Cost(i) = (1 - ω)·G(i) + ω·D(i)

[0165]

[0166] where G(i) is the actual movement cost of the node, and D(i) is the estimated movement cost from the resource point to the boundary point.

[0167] The routing module is further used to end if the layout routing quality meets the preset conditions;

[0168] If the layout routing quality does not meet the preset conditions, move any two nodes with a logical relationship in sequence to shorten the wire length between the two nodes.

[0169] The moving any two nodes with a logical relationship in sequence to shorten the wire length between the two nodes includes:

[0170] Select the node with the lowest escape cost in the i-th movement order set as the minimum node, and move each logical group corresponding to the minimum node in sequence as a group, where the logical group includes two nodes with a logical relationship;

[0171] Remove the minimum node from the i-th movement order set, update the i-th movement order set, and use the node with the lowest escape cost in the updated i-th movement order set as the new minimum node;

[0172] Return the node with the lowest escape cost in the selected set of the i-th movement order as the minimum node, and move each logical grouping corresponding to the minimum node in groups in turn until there are no nodes in the updated i-th movement order set;

[0173] where i = 1, 2, 3, 4.

[0174] The selection of the node with the lowest escape cost in the i-th movement order set as the minimum node and the sequential movement of each logical grouping corresponding to the minimum node in groups includes:

[0175] Set up a first candidate box based on the minimum node in the i-th movement order set, and move the first candidate box towards the boundary with a first preset step size;

[0176] If there are no available nodes in the candidate box, keep the minimum node unmoved;

[0177] If there are available nodes in the candidate box and the escape cost of the available nodes is greater than the escape cost of the minimum node, continue to move the first candidate box until an available node with an escape cost less than the escape cost of the minimum node is encountered;

[0178] Set up a second candidate box based on another node in the logical grouping corresponding to the minimum node, and move the second candidate box towards the boundary with a second preset step size;

[0179] If there are no available nodes in the second candidate box, keep the other node unmoved;

[0180] If there are available nodes in the second candidate box and the escape cost of the available nodes is greater than the escape cost of the other node, continue to move the second candidate box until an available node with an escape cost less than the escape cost of the other node is encountered.

[0181] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above-mentioned division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the mobile terminal is divided into different functional units or modules to complete all or part of the functions described above. Each functional module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of each functional module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working process of the modules in the above mobile terminal can refer to the corresponding process in the foregoing method embodiment and will not be elaborated here.

[0182] Figure 5 This is a schematic diagram of a terminal device provided by an embodiment of the present invention. As Figure 5 shown, the terminal device 5 of this embodiment includes: a processor 50, a memory 51, and a computer program 52 stored in the memory 51 and executable on the processor 50. When the processor 50 executes the computer program 52, the steps of the above circuit design method are implemented, such as Figure 1 the steps 101 to 104 shown. Alternatively, when the processor 50 executes the computer program 52, the functions of each module / unit in the above device embodiments are implemented, such as Figure 4 the functions of the modules 41 to 44 shown.

[0183] Exemplarily, the computer program 52 can be divided into one or more modules / units. The one or more modules / units are stored in the memory 51 and executed by the processor 50 to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program 52 in the terminal device 5.

[0184] The terminal device 5 can be a computing device such as a desktop computer, a notebook, or a palm computer. The terminal device may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art can understand that Figure 5 this is only an example of the terminal device 5 and does not constitute a limitation on the terminal device 5. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the terminal device may further include input / output devices, network access devices, a bus, etc.

[0185] The so-called processor 50 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0186] The memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk equipped on the terminal device 5, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory 51 may also include both the internal storage unit and the external storage device of the terminal device 5. The memory 51 is used to store the computer program and other programs and data required by the terminal device. The memory 51 may also be used to temporarily store the data that has been output or will be output.

[0187] An embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented.

[0188] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned various method embodiments when executed.

[0189] Those skilled in the art can clearly understand that for the convenience and conciseness of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present invention. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0190] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0191] Those of ordinary skill in the art will realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present invention.

[0192] In the embodiments provided by the present invention, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0193] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0194] In addition, the functional units in each embodiment of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0195] When the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0196] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A circuit design method, characterized in that, Including: Determine the initial coordinates of unknown nodes based on the initial coordinates of known nodes; Map all nodes to the area to be laid out according to the initial coordinates of all nodes to generate a layout diagram; Evenly divide the area to be laid out into several sub-areas; Move the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout diagram; The moving the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number includes: If the total number of nodes in any sub-area exceeds the preset number, determine the number of nodes to be moved in the any sub-area; Determine the first new coordinates of the nodes to be moved according to the number of the nodes to be moved; If the component to which the node to be moved belongs coincides with other components when the node to be moved moves from the initial coordinates to the first new coordinates, adjust the first new coordinates; The adjusting the first new coordinates includes: Set a first virtual point in a first direction separated from the first new coordinates, and the difference between the coordinates of the first virtual point and the first new coordinates is equal to the difference between the first new coordinates and the initial coordinates of the node to be moved; Determine the second new coordinates of the node to be moved according to the first distance formula and the coordinates of the first virtual point; If the component to which the node to be moved belongs does not coincide with other components when the node to be moved moves from the first new coordinates to the second new coordinates, update the coordinates of the node to be moved to the second new coordinates; If when the node to be moved moves from the first new coordinate to the second new coordinate, the element to which the node to be moved belongs coincides with other elements and F f +F r > 0, return to the step of determining the second new coordinate of the node to be moved according to the first distance formula and the coordinates of the first virtual point, and continue to update the value of d f to continue adjusting the position of the node; If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs coincides with other components and F f +F r ≤0, a second virtual point is set in a second direction separated from the first new coordinate; Determine the third new coordinates of the node to be moved according to the second distance formula and the coordinates of the second virtual point; If the component to which the node to be moved belongs does not coincide with other components when the node to be moved moves from the first new coordinates to the third new coordinates, update the coordinates of the node to be moved to the third new coordinates; If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r > 0, return to the step of determining the third new coordinate of the node to be moved according to the second distance formula and the coordinates of the second virtual point, and continue to adjust the position of the node; If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r ≤0, move the node to be moved from the second new coordinate to the sparse sub-region within the region to be laid out, where the sparse sub-region is a sub-region in the region to be laid out with the number of nodes less than a preset threshold or a sub-region with a blank area larger than the area of the component to which the node to be moved belongs; Wherein, the first distance formula is: The second distance formula is: F f = ω f * d fn ,F f＇ = ω f＇ * d fn＇ , - 3 < ω f <0, - 3 < ω f＇ <0 d fn is the distance between the first virtual point and the second new coordinate, d fn The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, d fn＇ is the distance between the second virtual point and the third new coordinate, d fn＇ The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, Fr is the total fixing force received by the coincident nodes to be moved, and the second direction is perpendicular to the first direction; F F and F f＇ are virtual forces and are negative values.

2. The circuit design method according to claim 1, characterized in that, The determining the number of nodes to be moved in the any sub-area includes: The determining the first new coordinates of the nodes to be moved according to the number of the nodes to be moved includes: Where M is the number of nodes to be moved, Ln is the sum of the number of nodes in the sub-region BOX on the left side of the cutting line, Rn is the sum of the number of nodes in the sub-region BOX on the right side of the cutting line, Lb is the capacity of the sub-region BOX on the left side of the cutting line, and Rb is the capacity of the sub-region BOX on the right side of the cutting line. respectively represent the leftmost coordinate of the grid in the sub-region BOX on the left side of the cutting line and the rightmost coordinate of the grid in the sub-region BOX on the right side of the cutting line. respectively represent the initial coordinate of the node and the first new coordinate; Among them, , is the width of a single BOX, represents the capacity of a single BOX.

3. The circuit design method according to claim 1, characterized in that, After the moving the nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout diagram, includes: Determine the escape route of each node according to the cost function to route the updated layout diagram.

4. The circuit design method according to claim 3, wherein The determining the escape route of each node according to the cost function to route the updated layout diagram includes: For any node, select available resource points in the escape direction from the node to the boundary point; Calculate the escape cost of each resource point according to the cost function, and save the resource point corresponding to the minimum escape cost to the resource point set; If the resource point corresponding to the minimum escape cost is a boundary point, connect the resource points in the resource point set in the order in which the resource point corresponding to the minimum escape cost is saved to the resource point set; If the resource point corresponding to the minimum escape cost is not a boundary point, update the resource point corresponding to the minimum escape cost to a node, and return to execute the step of selecting available resource points in the escape direction from the node to the boundary point.

5. The circuit design method according to claim 4, wherein The cost function is as follows: Among them, is the true movement cost of the node, is the estimated movement cost from the resource point to the boundary point.

6. The circuit design method according to claim 4, wherein After connecting the resource points in the resource point set according to the order of the resource points corresponding to the minimum escape cost and saving them to the resource point set, it further includes: If the layout and routing quality meets the preset conditions, end; If the layout and routing quality does not meet the preset conditions, then move any two nodes with logical relationships in sequence to shorten the wire length between the two nodes.

7. The circuit design method according to claim 6, wherein The step of moving any two nodes with logical relationships in sequence to shorten the wire length between the two nodes includes: Select the node with the lowest escape cost in the i-th moving order set as the minimum node, and move each logical group corresponding to the minimum node in sequence in groups, where the logical group includes two nodes with logical relationships; Remove the minimum node in the i-th moving order set, update the i-th moving order set, and use the node with the lowest escape cost in the updated i-th moving order set as the new minimum node; Return to execute the step of selecting the node with the lowest escape cost in the i-th moving order set as the minimum node, and moving each logical group corresponding to the minimum node in sequence in groups until there are no nodes in the updated i-th moving order set; where i = 1, 2, 3, 4.

8. The circuit design method according to claim 7, wherein The step of selecting the node with the lowest escape cost in the i-th moving order set as the minimum node and moving each logical group corresponding to the minimum node in sequence in groups includes: Set up a first candidate box based on the minimum node in the i-th moving order set, and move the first candidate box towards the boundary with a first preset step size; If there are no available nodes in the candidate box, keep the minimum node stationary; If there are available nodes in the candidate box and the escape cost of the available nodes is greater than the escape cost of the minimum node, continue to move the first candidate box until an available node with an escape cost less than the escape cost of the minimum node is encountered; Set up a second candidate box based on the other node in the logical group corresponding to the minimum node, and move the second candidate box towards the boundary with a second preset step size; If there are no available nodes in the second candidate box, keep the other node stationary; If there are available nodes in the second candidate box and the escape cost of the available nodes is greater than the escape cost of the other node, continue to move the second candidate box until an available node with an escape cost less than the escape cost of the other node is encountered.

9. A circuit design platform, wherein It includes: A coordinate module for determining the initial coordinates of unknown nodes according to the initial coordinates of known nodes; A mapping module for mapping all nodes to the area to be laid out according to the initial coordinates of all nodes to generate a layout diagram; A zoning module for evenly dividing the area to be laid out into several sub-areas; An adjustment module for moving nodes according to the number of nodes in each sub-area so that the total number of nodes in all sub-areas does not exceed a preset number to update the layout diagram; The adjustment module is further configured to, if the total number of nodes in any sub-area exceeds the preset number, determine the number of nodes to be moved in the any sub-area; Determine the first new coordinates of the nodes to be moved according to the number of nodes to be moved. When the node to be moved moves from the initial coordinate to the first new coordinate, if the component to which the node to be moved belongs coincides with other components, adjust the first new coordinate; The adjustment module is further configured to set a first virtual point in a first direction separated from the first new coordinate, and a difference between coordinates of the first virtual point and the first new coordinate is equal to a difference between the first new coordinate and the initial coordinate of the node to be moved; Determine a second new coordinate of the node to be moved according to a first distance formula and coordinates of the first virtual point; When the node to be moved moves from the first new coordinate to the second new coordinate, if the component to which the node to be moved belongs does not coincide with other components, update the coordinate of the node to be moved to the second new coordinate; If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs coincides with other components and F f +F r > 0, return to the step of determining the second new coordinate of the node to be moved according to the first distance formula and the coordinates of the first virtual point, and continue to update the value of d f to continue to adjust the position of the node; If when the node to be moved moves from the first new coordinate to the second new coordinate, the component to which the node to be moved belongs coincides with other components and F f +F r ≤0, a second virtual point is set in a second direction separated from the first new coordinate; Determine a third new coordinate of the node to be moved according to a second distance formula and coordinates of the second virtual point; When the node to be moved moves from the first new coordinate to the third new coordinate, if the component to which the node to be moved belongs does not coincide with other components, update the coordinate of the node to be moved to the third new coordinate; If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r > 0, return to the step of determining the third new coordinate of the node to be moved according to the second distance formula and the coordinates of the second virtual point, and continue to adjust the position of the node; If when the node to be moved moves from the first new coordinate to the third new coordinate, the component to which the node to be moved belongs coincides with other components and F f＇ +F r ≤0, move the node to be moved from the second new coordinate to the sparse sub-region within the region to be laid out, where the sparse sub-region is a sub-region in the region to be laid out with the number of nodes less than a preset threshold or a sub-region with a blank area larger than the area of the component to which the node to be moved belongs; Wherein, the first distance formula is: The second distance formula is: F f = ω f * d fn ,F f＇ = ω f＇ * d fn＇ , - 3 < ω f <0, - 3 < ω f＇ <0 d fn is the distance between the first virtual point and the second new coordinate, d fn The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, d fn＇ is the distance between the second virtual point and the third new coordinate, d fn＇ The initial value is the difference between the first new coordinate and the initial coordinate of the node to be moved, Fr is the total fixing force received by the coincident nodes to be moved, and the second direction is perpendicular to the first direction; F F and F f＇ are virtual forces and are negative values.

10. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the circuit design method according to any one of claims 1 to 8.

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