Semiconductor package including bottom filler

Abstract

A semiconductor package is disclosed. The semiconductor package includes: a substrate; an interposer located on the substrate; a first underfill located between the substrate and the interposer; at least one logic chip and at least one memory stack located on the interposer; and a molding material located on the interposer while surrounding side surfaces of the at least one logic chip and the at least one memory stack. The molding material includes regions having different heights. The first underfill covers a portion of the molding material.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0085061, filed on Jul. 10, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosed exemplary embodiments relate to a semiconductor package and a method of manufacturing a semiconductor package. Background Art

[0003] For next-generation high-performance communication devices, semiconductor packages having logic devices and memory devices (with high-bandwidth memory (HBM)) are attracting attention. Such a semiconductor package may include an interposer mounted on a substrate and a logic chip and a plurality of memory stacks mounted on the interposer.

[0004] Specifically, semiconductor packages designed to be suitable for mobile communication are manufactured to be thin, and thus may be very weak against external physical stresses such as warping. Summary of the Invention

[0005] The disclosed exemplary embodiments provide a semiconductor package in which generation of cracks between internal devices is minimized and a method of manufacturing a semiconductor package.

[0006] According to an embodiment, a semiconductor package includes: a substrate; an interposer located on the substrate; a first underfill located between the substrate and the interposer; at least one logic chip and at least one memory stack located on the interposer; and a molding material located on the interposer while surrounding side surfaces of the at least one logic chip and side surfaces of the at least one memory stack. The molding material includes regions having different heights. The first underfill covers a part of the molding material.

[0007] According to an embodiment, a semiconductor package includes: at least one logic chip and a plurality of memory stacks; a molding material surrounding side surfaces of the at least one logic chip and side surfaces of the plurality of memory stacks; and an underfill surrounding a periphery of the molding material while overlapping with a part of the molding material. The molding material includes a reference region and at least one recessed region. The reference region includes a part having a maximum height. A height of the at least one recessed region is lower than the maximum height of the part of the reference region. When viewed in a plane, the molding material includes a plurality of sides and a plurality of corners. Each of the plurality of corners is defined by two adjacent sides of the plurality of sides. The at least one recessed region includes the plurality of corners.

[0008] According to an embodiment, a semiconductor package includes: a substrate; an interposer located on the substrate; underfill located between the substrate and the interposer; a logic chip located on the interposer; a first memory stack and a second memory stack located on the interposer; and a molding material located on the interposer while surrounding side surfaces of the logic chip, side surfaces of the first memory stack, and side surfaces of the second memory stack. The first memory stack and the second memory stack are symmetrically arranged relative to the logic chip and are arranged in parallel. The molding material includes a reference region, a first recessed region, and a second recessed region, and the first recessed region and the second recessed region have a height lower than that of the reference region. The underfill overlaps with the first recessed region and the second recessed region on side surfaces of the molding material and is located on the first recessed region and the second recessed region. The height of the underfill is higher than the height of the first recessed region and lower than the height of the reference region.

[0009] According to an embodiment, a method for manufacturing a semiconductor package includes: forming at least one logic chip and a plurality of memory stacks on an interposer; coating uncured molding material on the interposer; curing the uncured molding material to provide a cured molding material; forming regions with different heights at the cured molding material through a process of removing a part of the cured molding material; mounting the interposer on a substrate; and forming underfill between the substrate and the interposer, on an outer side of a periphery of the cured molding material, and on a part of the region of the cured molding material.

[0010] The disclosed exemplary embodiments provide a semiconductor package having a structure capable of reducing an effective stress formed in a horizontal direction between a molding material and an underfill and / or a method for manufacturing a semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic top view of a semiconductor package according to the disclosed exemplary embodiments.

[0012] Figure 2 is along Figure 1 a schematic cross-sectional view of the semiconductor package taken along line I-I' in

[0013] Figure 3 is Figure 2 an enlarged view of region II in

[0014] Figure 4 is Figure 2 an enlarged view of region III in

[0015] Figures 5 to 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor package according to the disclosed exemplary embodiments.

[0016] Figures 10 to 16 is a schematic top view in projection of a semiconductor package according to an exemplary embodiment disclosed.

[0017] Figures 17 to 19 are views schematically showing cross-sections of parts of a semiconductor package according to an exemplary embodiment disclosed, respectively.

[0018] Figure 20 is a cross-sectional view schematically showing a step in a method for manufacturing a semiconductor package according to an exemplary embodiment disclosed. DETAILED DESCRIPTION

[0019] When the term “about” or “substantially” is used in combination with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operating tolerances in the vicinity of the stated value (e.g., ±10%). Further, when the words “generally” and “substantially” are used in combination with a geometric shape, it is intended that the precision of the geometric shape is not required, but the boundaries of the shape are within the disclosed range. Further, whether the numerical value or the shape is modified by “about” or “substantially”, it will be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances in the vicinity of the stated numerical value or shape (e.g., ±10%).

[0020] Figure 1 is a schematic top view in projection of a semiconductor package according to an exemplary embodiment disclosed. Figure 2 is along Figure 1 a schematic cross-sectional view of the semiconductor package taken along line I-I' in Figure 3 is Figure 2 an enlarged view of region II in Figure 4 is Figure 2 an enlarged view of region III in

[0021] Referring to Figure 1 , the semiconductor package 1 includes a substrate 10, one or more logic chips 31 and 32 disposed on the substrate 10, one or more memory stacks 41 to 48, a molding material 20 surrounding the logic chips 31 and 32 and the memory stacks 41 to 48, and a first underfill 50. The upward direction of the semiconductor package 1 is referred to as “third direction DR3”. For ease of description, when viewed in Figure 1 , the first direction DR1 is defined to represent an upward or downward direction, the second direction DR2 is defined to represent a left or right direction, and the third direction DR3 is defined to represent a direction orthogonal to the plane defined by the first direction DR1 and the second direction DR2. Of course, it can be understood that the first direction DR1, the second direction DR2, and the third direction DR3 intersect with each other, but are not limited to the above definitions.

[0022] The substrate 10 may be a base component of the semiconductor package 1. The substrate 10 may be selected from a printed circuit board (PCB), a flexible printed circuit board (FPCB), a silicon-based substrate, a ceramic substrate, a glass substrate, and an insulated circuit board. In an embodiment, the substrate 10 may be a printed circuit board or a flexible printed circuit board.

[0023] In an embodiment, the semiconductor package 1 may include a first logic chip 31 and a second logic chip 32. The first logic chip 31 and the second logic chip 32 may be arranged side by side in a first direction DR1 such that the first logic chip 31 and the second logic chip 32 are disposed adjacent to each other on the substrate 10. Each of the first logic chip 31 and the second logic chip 32 may include one of a core processor, an application specific integrated circuit (ASIC), a mobile application processor (AP), and other processing chips. The first logic chip 31 and the second logic chip 32 may be horizontally disposed at the same level.

[0024] In an embodiment, the semiconductor package 1 may include a first memory stack 41 to an eighth memory stack 48. The first memory stack 41 to the fourth memory stack 44 may be arranged side by side relative to the first logic chip 31 in a second direction DR2 that intersects the first direction DR1. The fifth memory stack 45 to the eighth memory stack 48 may be arranged side by side relative to the second logic chip 32 in the second direction DR2.

[0025] In some embodiments, the first memory stack 41 to the eighth memory stack 48 may include a stack of interconnected semiconductor chips (e.g., DRAM). In some embodiments, the semiconductor package 1 (and Figures 10 to 16 the semiconductor packages 1-1, 1-2, 1-3, 1-4, 2, 3, and 4 described therein) may comply with the high bandwidth memory (HBM) standard and future evolutions / releases of the HBM standard issued by JEDEC (Joint Electron Device Engineering Council).

[0026] According to an embodiment, the first memory stack 41 to the fourth memory stack 44 may be symmetrically disposed on opposite sides of the first logic chip 31 in the second direction DR2 while being parallelly arranged.

[0027] For example, the first memory stack 41 and the second memory stack 42 can be arranged adjacent to one side surface (the left side in the figure) of the first logic chip 31. The third memory stack 43 and the fourth memory stack 44 can be arranged adjacent to the other side surface (the right side in the figure) of the first logic chip 31. The first memory stack 41 and the second memory stack 42 can be arranged side by side in the first direction DR1 while being aligned with each other in the first direction DR1. Similarly, the third memory stack 43 and the fourth memory stack 44 can be arranged side by side in the first direction DR1 while being aligned with each other in the first direction DR1.

[0028] For example, the fifth memory stack 45 and the sixth memory stack 46 can be arranged adjacent to one side surface (the left side in the figure) of the second logic chip 32. The seventh memory stack 47 and the eighth memory stack 48 can be arranged adjacent to the other side surface (the right side in the figure) of the second logic chip 32. The fifth memory stack 45 and the sixth memory stack 46 can be arranged side by side in the first direction DR1 while being aligned with each other in the first direction DR1. Similarly, the seventh memory stack 47 and the eighth memory stack 48 can be arranged side by side in the first direction DR1 while being aligned with each other in the first direction DR1.

[0029] The logic chips 31 and 32 can be arranged very closely adjacent to each other. The first logic chip 31 and the second logic chip 32 can be spaced apart from each other or adjacent to each other by a distance of about 0.04 mm to 0.08 mm. In an exemplary embodiment, the distance between the first logic chip 31 and the second logic chip 32 can be about 0.06 mm.

[0030] For example, the minimum distance between the logic chips 31 and 32 can be smaller than the minimum distance between the logic chips 31 and 32 and the memory stacks 41 to 48. The logic chips 31 and 32 and the memory stacks 41 to 48 can be spaced apart from each other or adjacent to each other by a distance of about 0.5 mm to 0.9 mm. In an exemplary embodiment, the distance between the logic chips 31 and 32 and the memory stacks 41 to 48 can be about 0.7 mm.

[0031] The molding material 20 can surround the side surfaces of the logic chips 31 and 32 and the side surfaces of the memory stacks 41 to 48. The molding material 20 can fill the space between the logic chips 31 and 32 and the memory stacks 41 to 48. The upper surface of each of the logic chips 31 and 32 and the memory stacks 41 to 48 can be exposed and not covered by the molding material 20. According to an embodiment, the height of the upper surfaces of the logic chips 31 and 32 and the memory stacks 41 to 48 can be equal to the height of the uppermost surface of the molding material 20. The molding material 20 can include an epoxy molding compound (EMC).

[0032] In an embodiment, the periphery of the molding material 20 may have a planar quadrilateral shape. The molding material 20 may include four sides SD1 to SD4 and four corners EG1 to EG4 at the planar periphery, and each corner is defined by a point where two adjacent sides of the four sides SD1 to SD4 meet. For example, the molding material 20 may include a first side SD1 and a third side SD3, and a second side SD2 and a fourth side SD4. The first side SD1 and the third side SD3 extend in a first direction DR1 and are arranged parallel to each other in the first direction DR1. The second side SD2 and the fourth side SD4 extend in a second direction DR2 and are arranged parallel to each other in the second direction DR2. When viewed in Figure 1 it, the first side SD1 may be disposed on the left side of the third side SD3, and the second side SD2 may be disposed on the upper side of the fourth side SD4. The first side SD1 and the second side SD2 include a point at the junction of the first side SD1 and the second side SD2. This point may be defined as the first corner EG1. The second side SD2 and the third side SD3 include a point at the junction of the second side SD2 and the third side SD3. This point may be defined as the second corner EG2. The third side SD3 and the fourth side SD4 include a point at the junction of the third side SD3 and the fourth side SD4. This point may be defined as the third corner EG3. The fourth side SD4 and the first side SD1 include a point at the junction of the fourth side SD4 and the first side SD1. This point may be defined as the fourth corner EG4.

[0033] In an embodiment, the first side SD1 to the fourth side SD4 of the molding material 20 may have a length of about 15 mm or greater.

[0034] In an embodiment, the molding material 20 may include a reference region RFA and a plurality of recessed regions RCA1 to RCA4. The reference region RFA may be defined as a region including a part of the molding material 20 where the molding material 20 has the maximum height. Each of the recessed regions RCA1 to RCA4 may be defined as a region having a height relatively lower than the height of the reference region RFA.

[0035] In an embodiment, the plurality of recessed regions RCA1 to RCA4 may include a first recessed region RCA1, a second recessed region RCA2, a third recessed region RCA3, and a fourth recessed region RCA4. For example, the first recessed region RCA1 may include the first corner EG1, the second recessed region RCA2 may include the second corner EG2, the third recessed region RCA3 may include the third corner EG3, and the fourth recessed region RCA4 may include the fourth corner EG4. In an exemplary embodiment, each recessed region may have a planar quadrilateral shape.

[0036] In an embodiment, the width w1 of each recessed region may be equal to or less than the length w2 of each side of the molding material 20. For example, the width w1 of the recessed region may be equal to or greater than about 50 μm.

[0037] In an embodiment, when viewed in a plane, the area occupied by the plurality of recessed regions may be about 0.2% to 20% of the area of the molding material.

[0038] In an embodiment, when viewed in a plane, the first underfill 50 may be formed to surround at least a part of each side surface of the molding material 20. The first underfill 50 may be formed to cover at least a part of the upper surface in each of the recessed regions RCA1 to RCA4.

[0039] In an embodiment, the logic chips 31 and 32 and the memory stacks 41 to 48 may be disposed within a reference region RFA of the molding material 20.

[0040] Referring to Figure 1 and Figure 2 , in an embodiment, the semiconductor package 1 may include a substrate 10, a first underfill 50 disposed on the substrate 10, an interposer 60 disposed on the first underfill 50, a molding material 20 and a second underfill 70 disposed on the interposer 60, and logic chips 31 and 32 and memory stacks 41 to 48 disposed on the second underfill 70. Additionally, the semiconductor package 1 may further include substrate bumps SB, interposer bumps IB, and chip bumps CB. The substrate bumps SB may be disposed under the substrate 10. The interposer bumps IB may be disposed under the interposer 60 while being positioned between the substrate 10 and the interposer 60. The chip bumps CB may be disposed under the logic chips 31 and 32 and the memory stacks 41 to 48. Each chip bump CB may be positioned between a corresponding one of the logic chips 31 and 32 and the interposer 60, or between a corresponding one of the memory stacks 41 to 48 and the interposer 60.

[0041] The interposer 60 may be mounted on the substrate 10. The interposer 60 may be selected from a printed circuit board (PCB), a flexible PCB (FPCB), a silicon-based substrate, a ceramic substrate, a glass substrate, and an insulated circuit board. For example, the substrate 10 may be selected from a PCB and an FPCB. In an embodiment, the interposer 60 may be a silicon-based substrate.

[0042] The logic chips 31 and 32 and the memory stacks 41 to 48 may be mounted on the upper surface of the interposer 60. The interposer 60 may be a substrate 10 including a redistribution structure. The interposer 60 may electrically connect each of the logic chips 31 and 32 to the substrate 10, and may electrically connect each of the memory stacks 41 to 48 to the substrate 10.

[0043] The semiconductor package 1 may include a substrate bump pad SP disposed under the substrate 10 and an interposer bump pad IP disposed on the substrate 10. The substrate bump pad SP and the interposer bump pad IP may be electrically connected through wirings formed in the substrate 10 in a vertical direction and wirings formed in the substrate 10 in a horizontal direction. The substrate bump pad SP may contact the substrate bump SB, and thus may be electrically connected to an external circuit board. The interposer bump pad IP may contact the interposer bump IB, and thus may be electrically connected to the interposer 60.

[0044] In an embodiment, the semiconductor package 1 may include a first underfill 50 disposed between the substrate 10 and the interposer 60. In an embodiment, the first underfill 50 may be formed over the entire lower surface of the interposer 60 except for the region where the interposer bumps IB are formed. The first underfill 50 may surround the interposer bumps IB. Additionally, when viewed in a plane, the first underfill 50 may be formed to surround the periphery of the interposer 60. Further, when viewed in a plane, the first underfill 50 may be formed to have a height greater than the height of the lowermost surface of the molding material 20 while surrounding the periphery of the molding material 20.

[0045] In an embodiment, the first underfill 50 may be formed to overflow onto at least a portion of the molding material 20. In the specification, "overflow" means that a second component disposed under a first component is formed to cover a part of the side surface and the upper surface of the first component. For example, the first underfill 50 may be provided to cover at least a part of the upper surface of the recessed regions RCA1 to RCA4 in the molding material 20. According to an embodiment, the first underfill 50 may be disposed on the recessed regions RCA1 to RCA4 of the molding material 20, but not on the reference region RFA.

[0046] In an embodiment, the portion of the first underfill 50 formed to overflow onto at least a portion of the molding material 20 may have a height lower than the height of the reference region RFA of the molding material 20. In an embodiment, the first underfill 50 may be formed to extend up to a part of the height of the boundary interface between the reference region RFA and each of the recessed regions RCA1 to RCA4 and contact that height portion.

[0047] The first underfill 50 may provide a bonding force between the substrate 10 and the interposer 60. In an embodiment, the first underfill 50 may include a thermosetting resin.

[0048] A second bottom filler 70 may be formed between the interposer 60 and the logic chips 31 and 32 and between the interposer 60 and the memory stacks 41 to 48 to surround the chip bumps CB. The second bottom filler 70 may provide a bonding force between the interposer 60 and the logic chips 31 and 32 and between the interposer 60 and the memory stacks 41 to 48. In an embodiment, the second bottom filler 70 may include a thermosetting resin.

[0049] In an embodiment, a molding material 20 may be disposed on the interposer 60. According to an embodiment, the molding material 20 may be formed such that the upper surface of the interposer 60 is not exposed. For example, the molding material 20 may be formed to overlap the entire portion of the interposer 60. The molding material 20 may be directly disposed on the interposer 60 to surround the side surfaces of the logic chips 31 and 32 and the side surfaces of the memory stacks 41 to 48.

[0050] In an embodiment, the total height or total thickness of the semiconductor package 1 may be about 2.7 mm to 3.3 mm. For example, the substrate 10 may have a thickness of about 1.5 mm to 2 mm. The diameter or thickness of the substrate bumps SB may be about 0.2 mm to 0.8 mm. In an embodiment, the interposer 60 may be thinner than the substrate 10. For example, the interposer 60 may have a thickness of about 0.5 mm to 1.5 mm. The diameter or thickness of the interposer bumps IB may be about 0.05 mm to 0.1 mm, which is smaller than the diameter or thickness of the substrate bumps SB. In an embodiment, the diameter or thickness of the chip bumps CB may be smaller than the diameter or thickness of the interposer bumps IB. For example, the diameter or thickness of the chip bumps CB may be about 0.02 mm to 0.05 mm. For example, the thicknesses of the logic chips 31 and 32 and the memory stacks 41 to 48 may be about 0.65 mm to 0.72 mm. For example, the total thickness including the interposer bumps IB, the interposer 60, the chip bumps CB, and the logic chips 31 and 32 may be about 0.8 mm to 1.0 mm.

[0051] Referring Figures 1 to 3 , each of the recessed regions RCA1 to RCA4 may have a height lower than the height of the reference region RFA. In the following description, the plurality of recessed regions RCA1 to RCA4 will be described with reference to the first recessed region RCA1. That is, the description of the first recessed region RCA1 may be applied to the second recessed region RCA2 to the fourth recessed region RCA4. According to an embodiment, the content given with reference to the height may be applied to the description given with reference to the thickness.

[0052] For example, as shown, the molding material 20 may have a recessed shape in a region adjacent to a corner (e.g., the recessed regions RCA1 to RCA4). In another example, the molding material 20 may have a shape including a notch or a groove in a region adjacent to a corner.

[0053] In the specification, the height of each region of the molding material 20 (e.g., each of regions RFA and RCA1 to RCA4) can be defined with reference to the upper surface of the interposer 60 (see Figure 2 ). In an embodiment, the reference region RFA can have substantially the same height at all of its locations. According to an embodiment, the reference region RFA can have the maximum thickness at the molding material 20. According to an embodiment, the plurality of recessed regions RCA1 to RCA4 can have a thickness smaller than the thickness of the reference region RFA.

[0054] In an embodiment, the height h2 of the first recessed region RCA1 can be about 5% to 50% of the height h1 of the reference region RFA. For example, the height h1 of the molding material 20 (which is the height from the upper surface of the interposer 60 in the reference region RFA) can be about 0.5 mm to 1 mm, and the height h2 of the molding material 20 (which is the height from the upper surface of the interposer 60 in the first recessed region RCA1) can be about 25 μm to 500 μm. For example, the height difference h3 between the reference region RFA and the first recessed region RCA1 can be about 500 μm to 975 μm.

[0055] In an exemplary embodiment, the boundary between the first recessed region RCA1 and the reference region RFA can be set outside the position where the interposer bump IB is formed.

[0056] In an embodiment, the first underfill 50 can be disposed to cover at least a portion of the outer surface and the upper surface of the first recessed region RCA1. The first underfill 50 can be formed to contact the substrate 10 while having an inclined shape at the outside of the first recessed region RCA1. In an exemplary embodiment, the first underfill 50 can include an inclined surface 50L at its periphery. Although the inclined surface 50L is shown as a planar surface, the inclined surface 50L can include a curved surface, but is not limited to the shown shape.

[0057] In an embodiment, the thickness h4 of the portion of the first underfill 50 disposed on the upper surface of the first recessed region RCA1 (i.e., the height from the upper surface of the first underfill 50) can be smaller than the height difference h3 between the height h1 of the reference region RFA of the molding material 20 and the height h2 of the first recessed region RCA1 from the upper surface of the interposer 60.

[0058] In an embodiment, the surface of the first underfill 50 that contacts the upper surface of the first recessed region RCA1 can include a portion other than a vertical surface. For example, the surface of the first underfill 50 that contacts the upper surface of the first recessed region RCA1 can include a horizontal surface (see Figure 3The horizontal surface can reduce the external stress (e.g., tensile stress) formed in the horizontal direction at the surface of the first underfill 50 that contacts the molding material 20. For example, when the surface of the first underfill 50 that contacts the upper surface of the first recessed area RCA1 is a horizontal surface, most of the stress acts in the vertical direction on the surface of the first underfill 50 that contacts the upper surface of the molding material 20. Thus, the effective stress formed in the horizontal direction can be reduced.

[0059] Referring to Figures 1 to 4 , each of the memory stacks 41 to 48 may include a plurality of stacked memory chips 40a to 40d, through-silicon vias (also known as "vias through silicon") VIA, and an adhesive film AF. The memory chips 40a to 40d in each of the memory stacks 41 to 48 may include non-volatile memory chips, such as dynamic random access memory (DRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PRAM), and flash memory, or various other memory chips.

[0060] In the following description, a plurality of memory stacks 41 to 48 will be described with reference to the third memory stack 43. In an embodiment, the bottom-most memory chip 40a may include a base die. The base die may include test logic circuits (such as design for test (DFT), joint test action group (JTAG), or memory built-in self-test (MBIST)), signal interface circuits (such as PHY), etc., instead of memory cell chips. When the bottom-most memory chip 40a is a base die, the number of stacked memory chips may be 4 or more. In the drawings, only three memory chips 40b to 40d are shown. The through-silicon vias VIA may vertically extend through the memory chips 40a to 40d while being connected to the corresponding chip bumps CB among the chip bumps CB. The chip bumps CB may respectively contact the chip pads CP formed on the upper surface of the interposer 60. The chip bumps CB and the through-silicon vias VIA may be vertically aligned. In an embodiment, connection bumps may be provided at the through-silicon vias VIA to electrically connect adjacent memory chips among the memory chips 40a to 40d. Each adhesive film AF may be disposed between adjacent memory chips among the stacked memory chips 40a to 40d. Each adhesive film AF may include a die attach film (DAF). In an embodiment, each adhesive film AF may include an underfill material.

[0061] Hereinafter, a method for manufacturing the semiconductor package 1 according to the disclosed exemplary embodiments will be described.

[0062] Figures 5 to 9 is a cross-sectional view schematically showing a method for manufacturing a semiconductor package according to the disclosed exemplary embodiments.

[0063] Referring to Figures 5 to 9 , a method for manufacturing a semiconductor package 1 may include the following steps: forming a logic chip and a memory stack on an interposer (S110); forming a molding material (S120); forming a recessed area (S130); mounting the resulting structure on a substrate (S140); and forming a first underfill (S150).

[0064] First, the step of forming a logic chip and a memory stack on an interposer may be performed (S110). The step of forming a logic chip and a memory stack on an interposer (S110) corresponds to the following steps: disposing logic chips 31 and 32 and memory stacks 41 to 48 on the interposer 60; coating a second underfill 70 between each of the logic chips 31 and 32 and the interposer 60; coating a second underfill 70 between each of the memory stacks 41 to 48 and the interposer 60; and curing the second underfill 70.

[0065] Next, the step of forming a molding material may be performed (S120). The step of forming a molding material (S120) corresponds to a molding process of directly coating a molding material 20a on the interposer 60 and curing the molding material 20a. The molding material 20a may be referred to as an uncured molding material 20a before performing the step of curing the molding material 20a, and may be referred to as a cured molding material 20a after performing the step of curing the molding material 20a. An encapsulation process of mounting the logic chips 31 and 32 and the memory stacks 41 to 48 on the interposer 60 and forming a molding material 20a on the interposer 60 may be performed. The stiffness of the semiconductor package 1 may be maintained by the molding process. In an exemplary embodiment, the upper surface of the molding material 20a may be flat.

[0066] In an embodiment, the molding material 20a may be coated such that the periphery of the molding material 20a corresponds to the periphery of the interposer 60. For example, the molding material 20a may be coated such that when viewed in a plane, the periphery of the molding material 20a has a quadrilateral shape, such as the shape of the interposer 60. Additionally, the molding material 20a may be coated such that the upper surfaces of the logic chips 31 and 32 and the upper surfaces of the memory stacks 41 to 48 are exposed. As a result, after coating the molding material 20a, the upper surface of the interposer 60 may not be exposed due to the molding material 20a, the logic chips 31 and 32, and the memory stacks 41 to 48.

[0067] Meanwhile, when performing a molding process, warping, deterioration of the filling of the first underfill 50, formation of cracks between the die and the molding material 20a, etc. may occur due to differences in the coefficient of thermal expansion (CTE) between the molding material 20a and adjacent components or for other reasons.

[0068] Subsequently, a step (S130) of forming a recessed region may be performed. The step (S130) of forming a recessed region corresponds to a step of forming at least one recessed region RCA1 or RCA2 in the molding material 20a. To form the recessed region (S130), a part of the molding material 20a may be removed. For example, the upper part of the region including each corner of the molding material 20a may be partially removed. Figure 7 The molding material 20a before forming at least one recessed region is shown. Figure 8 The remaining molding material 20 after forming at least one recessed region RCA1 or RCA2 by removing a part of the molding material 20a is shown.

[0069] In an embodiment, the step (S130) of forming a recessed region may include a laser process. For example, a part of the molding material 20a may be removed by a laser process to provide the molding material 20. For example, a laser is irradiated onto the regions of the molding material 20a that will respectively form the recessed regions RCA1 to RCA4, thereby partially removing the upper part of the molding material 20a to provide the molding material 20.

[0070] Subsequently, a step (S140) of mounting the resulting structure on a substrate may be performed. The step (S140) of mounting the resulting structure on a substrate corresponds to the following step: mounting an interposer 60 on which a logic chip 31, memory stacks 41 and 43 are mounted and which is provided with a molding material 20 on a substrate, the molding material 20 having recessed regions RCA1 and RCA2 formed in its upper part. Interposer bumps IB provided under the interposer 60 may contact interposer bump pads IP provided on the substrate 10 such that the interposer bumps IB respectively correspond to the interposer bump pads IP.

[0071] Thereafter, a step of forming a first bottom filler (S150) may be performed. The step of forming the first bottom filler (S150) corresponds to the following steps: coating the first bottom filler 50 between the substrate 10 and the interposer 60, on the periphery of the interposer 60 and the outer side of the periphery of the molding material 20, and on the recessed areas RCA1 and RCA2 of the molding material 20, and curing the first bottom filler 50. A bottom filler material having a desired viscosity and / or (optionally) a predetermined viscosity may be coated between the substrate 10 and the interposer 60, on the side surface of the interposer 60, on the periphery of the molding material 20, and on the recessed areas RCA1 and RCA2 of the molding material 20, and then the bottom filler material may be cured. At the same time, by forming the first bottom filler 50 so that the first bottom filler 50 covers up to the upper surface of a portion of the molding material 20, the possibility of forming cracks between the molding material 20 and the first bottom filler 50 contacting the molding material 20 may be minimized.

[0072] Next, a semiconductor package or a method for manufacturing a semiconductor package according to another example embodiment of the disclosure will be described. Figures 1 to 9 The same constituent elements will be described below, and the same or similar reference numerals will be designated for the constituent elements.

[0073] Figures 10 to 16 is a projection top view schematically illustrating a semiconductor package according to an example embodiment of the disclosure.

[0074] Figures 10 to 16 Each embodiment of Figure 1 The embodiments of the present invention differ in that the arrangement of at least one logic chip and at least one memory stack is changed, other chips are added, or the shape and position of the recessed area are changed.

[0075] Reference Figure 10 , the semiconductor package 1 - 1 according to the embodiment may further include reinforcement chips 81 and 82 .

[0076] The reinforcing chips 81 and 82 may be disposed to be aligned and overlapped with the boundary area (boundary line) between the memory stacks 41 to 44 at the upper side and the memory stacks 45 to 48 at the lower side in the second direction DR2. The reinforcing chips 81 and 82 may include a first reinforcing chip 81 disposed at the left side and a second reinforcing chip 82 disposed at the right side.

[0077] The first reinforcing chip 81 may be aligned with the first to sixth memory stacks 41, 42, 45, and 46 in the first direction DR1. For example, the first reinforcing chip 81 may be disposed between the second to fifth memory stacks 42 and 45.

[0078] The second reinforcement chip 82 can be aligned with the third memory stack 43, the fourth memory stack 44, the seventh memory stack 47, and the eighth memory stack 48 in the first direction DR1. For example, the second reinforcement chip 82 can be disposed between the fourth memory stack 44 and the seventh memory stack 47.

[0079] In an embodiment, the area of each of the reinforcement chips 81 and 82 can be smaller than the area of each of the memory stacks 41 to 48. For example, the length of the shorter side of the reinforcement chips 81 and 82 can be 1 / 2 or less than the length of the longer side of the memory stacks 41 to 48. According to an embodiment, the length of the longer side of the reinforcement chips 81 and 82 can be smaller than the length of the shorter side of the memory stacks 41 to 48.

[0080] Although not clearly shown, the reinforcement chips 81 and 82 can have a hexahedral or solid shape. In an embodiment, each of the reinforcement chips 81 and 82 can include a solid dummy chip or a plurality of stacked dummy chips. That is, each of the reinforcement chips 81 and 82 can include a chip stack. The reinforcement chips 81 and 82 can include a part of a silicon wafer (silicon die), a part of a printed circuit board, a metal or ceramic die, an epoxy compound, a cured polymer resin, an inorganic material such as glass, or other hard materials.

[0081] Since the semiconductor package 1-1 further includes the reinforcement chips 81 and 82, the semiconductor package 1-1 can have excellent physical stress resistance, such as warpage.

[0082] Referring to Figure 11 , in the semiconductor package 1-2 according to an embodiment, referring to the imaginary center of the molding material 20 when viewed in a plane, the first logic chip 31 can be disposed at the upper left side, the first memory stacks 41 to the fourth memory stacks 44 can be disposed at the upper right side, the fifth memory stacks 45 to the eighth memory stacks 48 can be disposed at the lower left side, and the second logic chip 32 can be disposed at the lower right side.

[0083] In an embodiment, the first memory stacks 41 to the fourth memory stacks 44 can be arranged in a 2×2 matrix, and the fifth memory stacks 45 to the eighth memory stacks 48 can be arranged in a 2×2 matrix.

[0084] Referring to Figure 12, in the semiconductor package 1-3 according to the embodiment, the logic chips 31 and 32 can be arranged side by side at one side, and the memory stacks can be arranged in a matrix (e.g., 4×2 matrix or 2×4 matrix) at the other side. For example, with reference to the imaginary center of the molding material 20 when viewed in the plane, the first logic chip 31 can be arranged at the upper left side, the second logic chip 32 can be arranged at the upper right side, the first to fourth memory stacks 41 to 44 can be arranged at the lower left side, and the fifth to eighth memory stacks 45 to 48 can be arranged at the lower right side.

[0085] In the embodiment, the first logic chip 31 and the second logic chip 32 can be arranged to be aligned and stacked with each other in the second direction DR2. The first memory stack 41 and the second memory stack 42, the third memory stack 43 and the fourth memory stack 44, the fifth memory stack 45 and the sixth memory stack 46, and the seventh memory stack 47 and the eighth memory stack 48 can be arranged to be aligned and stacked with each other in the first direction DR1. The first memory stack 41, the third memory stack 43, the fifth memory stack 45, and the seventh memory stack 47 can be arranged to be aligned and stacked with each other in the second direction DR2. The second memory stack 42, the fourth memory stack 44, the sixth memory stack 46, and the eighth memory stack 48 can be arranged to be aligned and stacked with each other in the second direction DR2.

[0086] Referring to Figure 13 , the semiconductor package 1-4 according to the embodiment can include one logic chip and multiple memory stacks 41 to 48. In the exemplary embodiment, the first to eighth memory stacks 41 to 48 can be symmetrically arranged at the opposite side of the first logic chip 31 while being arranged in parallel.

[0087] Referring to Figure 14, in semiconductor package 2 according to an embodiment, when viewed in a plane, the molding material 20 may include recessed regions RCA1 to RCA4 having a triangular shape. For example, the first recessed region RCA1 may have a right-angled triangle shape formed by a first side SD1, a second side SD2, and a line connecting a point on the first side SD1 and a point on the second side SD2. The second recessed region RCA2 may have a right-angled triangle shape formed by the second side SD2, a third side SD3, and a line connecting a point on the second side SD2 and a point on the third side SD3. The third recessed region RCA3 may have a right-angled triangle shape formed by the third side SD3, a fourth side SD4, and a line connecting a point on the third side SD3 and a point on the fourth side SD4. The fourth recessed region RCA4 may have a right-angled triangle shape formed by the fourth side SD4, the first side SD1, and a line connecting a point on the fourth side SD4 and a point on the first side SD1.

[0088] Referring to Figure 15 , in semiconductor package 3 according to an embodiment, when viewed in a plane, the molding material 20 may include recessed regions RCA1 to RCA4 having a shape with two sides and a curve. For example, when viewed in a plane, the recessed regions RCA1 to RCA4 may have a fan shape. The first recessed region RCA1 may have a fan shape formed by a first side SD1, a second side SD2, and a curve connecting a point on the first side SD1 and a point on the second side SD2. The second recessed region RCA2 may have a fan shape formed by the second side SD2, a third side SD3, and a curve connecting a point on the second side SD2 and a point on the third side SD3. The third recessed region RCA3 may have a fan shape formed by the third side SD3, a fourth side SD4, and a curve connecting a point on the third side SD3 and a point on the fourth side SD4. The fourth recessed region RCA4 may have a fan shape formed by the fourth side SD4, the first side SD1, and a curve connecting a point on the fourth side SD4 and a point on the first side SD1.

[0089] Referring to Figure 16 , in semiconductor package 4 according to an embodiment, the molding material 20 may include one recessed region RCA having a quadrilateral frame shape. The recessed region RCA may include a first corner EG1 to a fourth corner EG4 of the molding material 20 and a first side SD1 to a fourth side SD4 of the molding material 20.

[0090] Figures 17 to 19 are views schematically showing cross-sections of parts of semiconductor packages according to the disclosed exemplary embodiments, respectively.

[0091] Figures 17 to 19 Each embodiment of Figure 3The embodiment is different in that: the cross-sectional shapes of the recessed regions RCA1 to RCA4 are changed. The following description will be given with reference to the first recessed region RCA1.

[0092] Referring to Figure 17 , in the embodiment, the first recessed region RCA1 may include a first sub-region RCA1a and a second sub-region RCA1b having different heights. For example, the first sub-region RCA1a may be a region provided outside the second sub-region RCA1b. The height h5 of the first sub-region RCA1a may be lower than the height h6 of the second sub-region RCA1b. For example, the height h6 of the second sub-region RCA1b may be lower than the height h1 of the reference region RFA. According to the embodiment, the height h6 of the second sub-region RCA1b may be approximately twice the height h5 of the first sub-region RCA1a.

[0093] The first bottom filler 50 may overflow until the first sub-region RCA1a and the second sub-region RCA1b.

[0094] Referring to Figure 18 , in the embodiment, the first recessed region RCA1 may include an inclined surface 20L. The first bottom filler 50 may overflow until a part of the inclined surface 20L of the first recessed region RCA1.

[0095] Referring to Figure 19 , in the embodiment, the first recessed region RCA1 may include a first sub-region RCA1a and a second sub-region RCA1b having different heights, and the second sub-region RCA1b provided inside the first sub-region RCA1a may include an inclined surface.

[0096] The first bottom filler 50 may overflow until a part of the inclined surface 20L of the first sub-region RCA1a and the second sub-region RCA1b.

[0097] Figure 20 is a cross-sectional view schematically showing one step in a method for manufacturing a semiconductor package according to an exemplary embodiment disclosed.

[0098] Referring to Figure 20 , this embodiment is different from the Figure 7 embodiment in that: in the step (S130-1) of forming the recessed region, the recessed regions RCA1 to RCA4 are formed by a sawing process.

[0099] In an embodiment, a cutting member 90 having a desired strength and / or (optionally) a predetermined strength may be used to remove portions of the corners of the cured molding material 20. For example, the upper portion of the molding material 20 may be partially removed by physically removing the areas of the molding material 20 that will form the recessed regions RCA1 to RCA4 using a rotatable cutting member 90.

[0100] According to the disclosed exemplary embodiments, the effective stress formed in the horizontal direction between the molding material and the underfill may be reduced, and thus the possibility of damage to the resulting semiconductor package may be reduced.

[0101] Although the disclosed embodiments have been described with reference to the accompanying drawings, those skilled in the art should understand that various modifications can be made without departing from the scope of the disclosure and without changing its essential features. Therefore, the above embodiments should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A semiconductor package, the semiconductor package comprising: A substrate; An interposer located on the substrate; A first underfill located between the substrate and the interposer; At least one logic chip and at least one memory stack located on the interposer; And A molding material located on the interposer while surrounding side surfaces of the at least one logic chip and side surfaces of the at least one memory stack, The molding material includes a reference region and at least one recessed region, the at least one recessed region having a height different from that of the reference region, and the first underfill covers a part of the molding material, Wherein, when viewed in a plane, the molding material has a quadrilateral shape, The quadrilateral shape includes four sides and four corners, each of the four corners being defined by two adjacent sides of the four sides, The quadrilateral shape includes four recessed regions such that the at least one recessed region includes the four recessed regions, the four recessed regions respectively include the four corners, and When viewed in a plane, the area occupied by the four recessed regions is 0.2% to 20% of the area of the molding material.

2. The semiconductor package according to claim 1, wherein, The height of the at least one recessed region is lower than the height of the reference region; and The at least one recessed region is located outside the reference region.

3. The semiconductor package according to claim 2, wherein, The height of the at least one recessed region is 5% to 50% of the height of the reference region.

4. The semiconductor package according to claim 2, wherein, The first underfill overflows until the at least one recessed region.

5. The semiconductor package according to claim 4, wherein, The thickness of the first underfill located on the recessed region is smaller than the height difference between the reference region and the at least one recessed region.

6. The semiconductor package according to claim 4, wherein, The surface of the first underfill contacting the upper surface of the at least one recessed region includes a horizontal surface.

7. The semiconductor package according to claim 2, wherein, The at least one logic chip and the at least one memory stack are located within the reference region.

8. The semiconductor package according to claim 2, wherein, Each of the at least one recessed region includes a plurality of sub-regions having different heights.

9. The semiconductor package according to claim 2, wherein, The recessed region includes an inclined surface.

10. The semiconductor package according to claim 2, wherein: Relative to the upper surface of the interposer, the reference region has the maximum height; Relative to the upper surface of the interposer, the maximum height is 0.5 mm to 1 mm; and Relative to the upper surface of the interposer, the height of the recessed region is 25 μm to 500 μm.

11. The semiconductor package according to claim 1, wherein, The first underfill includes an inclined surface at its periphery.

12. The semiconductor package according to claim 1, the semiconductor package further comprising: A second underfill, wherein, The second underfill is located between each of the at least one logic chip and the interposer, or the second underfill is located between each of the at least one memory stack and the interposer.

13. The semiconductor package according to claim 1, wherein, The molding material includes an epoxy molding compound.

14. A semiconductor package, the semiconductor package comprising: At least one logic chip; A plurality of memory stacks; A molding material surrounds the side surfaces of the at least one logic chip and the side surfaces of the plurality of memory stacks. The molding material includes a reference region and at least one recessed region. The reference region includes a portion having a maximum height, and the height of the at least one recessed region is lower than the maximum height of the portion of the reference region. When viewed in a plane, the molding material has a quadrilateral shape that includes four sides and four corners. Each of the four corners is defined by two adjacent sides of the four sides, and the quadrilateral shape includes four recessed regions such that the at least one recessed region includes the four recessed regions, and the four recessed regions respectively include the four corners; and An underfill surrounds the periphery of the molding material and overlaps a portion of the molding material at the same time, wherein, when viewed in a plane, the area occupied by the four recessed regions is 0.2% to 20% of the area of the molding material.

15. The semiconductor package according to claim 14, wherein, The underfill is located on the at least one recessed region and not on the reference region.

16. The semiconductor package according to claim 14, wherein, Each of the four recessed regions has a width of 50 μm or more.

17. The semiconductor package according to claim 14, wherein, Some of the plurality of memory stacks are arranged in parallel and symmetrically arranged with respect to the corresponding logic chip among the at least one logic chip.

18. A semiconductor package, the semiconductor package includes: A substrate; An interposer located on the substrate; An underfill located between the substrate and the interposer; A logic chip located on the interposer; A first memory stack and a second memory stack located on the interposer, the first memory stack and the second memory stack are symmetrically arranged with respect to the logic chip and arranged in parallel at the same time; And A molding material located on the interposer and surrounding the side surfaces of the logic chip, the side surface of the first memory stack, and the side surface of the second memory stack at the same time, wherein the molding material includes a reference region and at least one recessed region, and wherein the molding material has a quadrilateral shape, when viewed in a plane, the quadrilateral shape includes four sides and four corners, the quadrilateral shape includes four recessed regions such that the at least one recessed region of the molding material includes the four recessed regions, the recessed regions respectively include corners, and when viewed in a plane, the area occupied by the four recessed regions is 0.2% to 20% of the area of the molding material, wherein each of the four recessed regions has a width of 50 μm or more, and wherein the at least one recessed region includes a first recessed region and a second recessed region, and the first recessed region and the second recessed region have a height lower than the height of the reference region, the underfill overlaps and is located on the first recessed region and the second recessed region on the side surface of the molding material, and the height of the underfill is higher than the height of the first recessed region and lower than the height of the reference region.

19. The semiconductor package according to claim 18, wherein, The underfill extends until a portion of the height of the boundary interface between the reference region and each of the first recessed region and the second recessed region such that the underfill contacts the portion of the height of the boundary interface.

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