Monitoring structure and its manufacturing method

Abstract

The present invention discloses a monitoring structure and a manufacturing method thereof. The monitoring structure includes a substrate, a plurality of critical dimension monitoring patterns, a plurality of resistance monitoring patterns, a first dummy gate structure, and a second dummy gate structure. The substrate has a first region and a second region. The critical dimension monitoring patterns are disposed on the first region of the substrate, and the resistance monitoring patterns are disposed on the second region of the substrate. The first dummy gate structure is disposed on the first region of the substrate and is located between the substrate and the critical dimension monitoring patterns in the vertical direction. The second dummy gate structure is disposed on the second region of the substrate and is located between the substrate and the resistance monitoring patterns in the vertical direction.

Description

Technical Field

[0001] The present invention relates to a monitoring structure and a manufacturing method thereof, and in particular, to a monitoring structure including a critical dimension monitoring pattern and a resistance monitoring pattern and a manufacturing method thereof. Background Art

[0002] With the progress of technology, the integrated circuit manufacturing process technology has also been continuously refined, so various electronic circuits can be integrated / fabricated on a chip. The semiconductor manufacturing process for manufacturing a chip includes many steps, such as a deposition process for forming a thin film, a photoresist coating process for forming a patterned photoresist, an exposure and development process, an etching process for patterning the thin film, etc. In order to ensure the process conditions of each manufacturing process, the layout design on the semiconductor wafer includes many types of monitoring patterns, such as monitoring patterns for measuring the critical dimension (CD), monitoring patterns for measuring the resistance condition of the conductive layer, and monitoring patterns for measuring the alignment condition between patterns of different layers. Different types of monitoring patterns have different structural requirements due to different corresponding measurement methods. Generally speaking, different types of monitoring patterns also vary in structure and / or their corresponding front-layer conditions. Summary of the Invention

[0003] The present invention provides a monitoring structure and a manufacturing method thereof. By providing a dummy gate structure under the critical dimension monitoring pattern and the resistance monitoring pattern, the difference in topography of the respective corresponding regions before forming the critical dimension monitoring pattern and the resistance monitoring pattern is reduced, thereby improving the correlation between the measurement results of critical dimension monitoring and resistance monitoring, which is helpful for related manufacturing process control and / or manufacturing process adjustment.

[0004] An embodiment of the present invention provides a monitoring structure, including a substrate, a plurality of critical dimension monitoring patterns, a plurality of resistance monitoring patterns, a first dummy gate structure, and a second dummy gate structure. The substrate has a first region and a second region. The plurality of critical dimension monitoring patterns are disposed on the first region of the substrate. The plurality of resistance monitoring patterns are disposed on the second region of the substrate. The first dummy gate structure is disposed on the first region of the substrate and is located between the substrate and the critical dimension monitoring patterns in a vertical direction. The second dummy gate structure is disposed on the second region of the substrate and is located between the substrate and the resistance monitoring patterns in the vertical direction.

[0005] An embodiment of the present invention provides a method for manufacturing a monitoring structure, including the following steps. Form a first dummy gate structure and a second dummy gate structure on a substrate. The first dummy gate structure is formed on a first region of the substrate, and the second dummy gate structure is formed on a second region of the substrate. Form a plurality of critical dimension monitoring patterns on the first region of the substrate. The first dummy gate structure is located between the substrate and the critical dimension monitoring patterns in a vertical direction. Form a plurality of resistance monitoring patterns on the second region of the substrate. The second dummy gate structure is located between the substrate and the resistance monitoring patterns in the vertical direction. Description of the Drawings

[0006] Figure 1 Schematic diagram of the monitoring structure according to the first embodiment of the present invention;

[0007] Figure 2 Schematic diagram of the method for manufacturing the monitoring structure according to an embodiment of the present invention;

[0008] Figure 3 Schematic diagram of the monitoring structure according to the second embodiment of the present invention;

[0009] Figure 4 Schematic diagram of the monitoring structure according to the third embodiment of the present invention;

[0010] Figure 5 Schematic diagram of the monitoring structure according to the fourth embodiment of the present invention.

[0011] Description of the Main Element Symbols

[0012] 10 Substrate

[0013] 12 Isolation Structure

[0014] 20 Gate Material

[0015] 20A First Dummy Gate Structure

[0016] 20B Second Dummy Gate Structure

[0017] 20C Gate Structure

[0018] 22 Source / Drain Region

[0019] 30 Dielectric Layer

[0020] 32 Dielectric Layer

[0021] 34 Dummy Metal Pattern

[0022] 34A First Dummy Metal Pattern

[0023] 34B Second Dummy Metal Pattern

[0024] 40 Dielectric Layer

[0025] 50 Conductive material

[0026] 50A Critical dimension monitoring pattern

[0027] 50B Resistance monitoring pattern

[0028] 101 Monitoring structure

[0029] 102 Monitoring structure

[0030] 103 Monitoring structure

[0031] 104 Monitoring structure

[0032] 10B Bottom surface

[0033] 10T Top surface

[0034] BS1 Bottom surface

[0035] BS2 Bottom surface

[0036] DS1 Distance

[0037] DS2 Distance

[0038] PC1 Pitch

[0039] PC2 Pitch

[0040] R1 First region

[0041] R2 Second region

[0042] R3 Third region

[0043] S1 Step

[0044] S2 Step

[0045] TK1 Thickness

[0046] TK2 Thickness

[0047] TS1 Top surface

[0048] TS2 Top surface

[0049] Z Vertical direction Detailed implementation manners

[0050] The following detailed description of the present invention has disclosed sufficient details to enable those skilled in the art to practice the present invention. The embodiments described below should be considered illustrative rather than restrictive. It will be obvious to those of ordinary skill in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the present invention.

[0051] Before further describing the embodiments, specific terms used throughout the text are described below.

[0052] The terms "on", "above", and "over" shall be construed in the broadest sense such that "on" not only means "directly on" something but also includes the meaning of being on something with other intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but may also include the meaning of being "above" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0053] Ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify elements of the claims. Unless otherwise specified, they do not inherently imply or represent that the claimed element has any previous ordinal number, nor do they represent the order of one claimed element with respect to another, or the order in a manufacturing method. The use of these ordinal numbers is only to clearly distinguish one claimed element having a certain name from another claimed element having the same name.

[0054] The term "etch" is generally used herein to describe a fabrication process for patterning a material such that at least a portion of the material remains after etching. When "etching" a material, at least a portion of the material can be retained after etching. In contrast, when "removing" a material, substantially all of the material can be removed during the process. However, in some embodiments, "removing" may be considered a broad term and include etching.

[0055] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any viable layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0056] Please refer to Figure 1 。 Figure 1 A schematic diagram of the monitoring structure 101 according to the first embodiment of the present invention is shown. As Figure 1As shown, the monitoring structure 101 includes a substrate 10, a plurality of critical dimension (CD) monitoring patterns 50A, a plurality of resistance monitoring patterns 50B, a first dummy gate structure 20A, and a second dummy gate structure 20B. The substrate 10 has a first region R1 and a second region R2. The plurality of critical dimension monitoring patterns 50A are disposed on the first region R1 of the substrate 10. The plurality of resistance monitoring patterns 502B are disposed on the second region R2 of the substrate 10. The first dummy gate structure 20A is disposed on the first region R1 of the substrate 10 and is located between the substrate 10 and the critical dimension monitoring patterns 50A in a vertical direction Z. The second dummy gate structure 20B is disposed on the second region R2 of the substrate 10 and is located between the substrate 10 and the resistance monitoring patterns 50B in the vertical direction Z.

[0057] In some embodiments, the substrate 10 may have an upper surface 10T and a bottom surface 10B opposite to each other in its thickness direction (such as the vertical direction Z described above), and the critical dimension monitoring patterns 50A, the resistance monitoring patterns 50B, the first dummy gate structure 20A, and the second dummy gate structure 20B may be disposed on one side of the upper surface 10T, but not limited thereto. The horizontal direction substantially orthogonal to the vertical direction Z may be substantially parallel to the upper surface 10T or / and the bottom surface 10B of the substrate 10, but not limited thereto. In addition, the distance in the vertical direction Z between a relatively higher position or / and component described herein and the bottom surface 10B of the substrate 10 may be greater than the distance in the vertical direction Z between a relatively lower position or / and component and the bottom surface 10B of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10B of the substrate 10 in the vertical direction Z than the upper part or top of this component. Another component above a certain component may be regarded as being relatively farther from the bottom surface 10B of the substrate 10 in the vertical direction Z, and another component below a certain component may be regarded as being relatively closer to the bottom surface 10B of the substrate 10 in the vertical direction Z, but not limited thereto.

[0058] In some embodiments, the monitoring structure 101 may further include a dielectric layer 30 disposed on the upper surface 10T of the substrate 10 and covering the first dummy gate structure 20A and the second dummy gate structure 20B, and the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B may be disposed on the dielectric layer 30. By respectively disposing the first dummy gate structure 20A and the second dummy gate structure 20B under the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B, the difference between the topography under the critical dimension monitoring pattern 50A and the topography under the resistance monitoring pattern 50B can be reduced, thereby improving the correlation between the measurement results of the critical dimension monitoring and the resistance monitoring, which is helpful for the relevant fabrication process control and / or fabrication process adjustment. For example, when there is no dummy gate structure under the critical dimension monitoring pattern 50A and there is a dummy gate structure under the resistance monitoring pattern 50B, affected by the loading effect of the fabrication process, the lower surface of the critical dimension monitoring pattern 50A will be significantly lower than the lower surface of the resistance monitoring pattern 50B, resulting in different thicknesses of the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B, thereby affecting the deviation of the correlation between the measurement results of the critical dimension monitoring and the resistance monitoring.

[0059] In some embodiments, the substrate 10 may include a semiconductor substrate such as a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. In addition, in some embodiments, the first dummy gate structure 20A and the second dummy gate structure 20B may be formed together by the same fabrication process, so the material composition of the first dummy gate structure 20A may be the same as that of the second dummy gate structure 20B and have substantially the same height, but this is not limited thereto. In some embodiments, the first dummy gate structure 20A and the second dummy gate structure 20B may respectively include a gate material 20, and the gate material 20 may include a gate dielectric layer (not shown) and a conductive material layer (not shown) stacked in sequence in the vertical direction Z. In some embodiments, the above-mentioned gate dielectric layer may include an oxide layer such as a silicon oxide layer or other suitable dielectric materials, and the above-mentioned conductive material layer may include a silicon-containing conductive material such as a doped polysilicon material or other suitable conductive materials such as metal conductive materials. In some embodiments, the dielectric layer 30 may include multiple layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable dielectric materials.

[0060] In some embodiments, the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B may be formed together by the same manufacturing process, so the material composition of each critical dimension monitoring pattern 50A may be the same as that of each resistance monitoring pattern 50B. For example, in some embodiments, the monitoring structure 101 may further include a dielectric layer 40 disposed on the dielectric layer 30, and the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B may be formed by a conductive material 50 disposed in the dielectric layer 40. The dielectric layer 40 may include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride, fluorosilicate glass (FSG), low dielectric constant (low-k) dielectric materials, or other suitable dielectric materials.

[0061] In some embodiments, the conductive material 50 may include a barrier layer (not shown) and a low-resistance material (not shown) disposed on the barrier layer. The low-resistance material may include materials with relatively low resistivity, such as copper, aluminum, tungsten, etc., and the barrier layer may include titanium nitride, tantalum nitride, or other suitable barrier materials, but is not limited thereto. It is worth noting that in this embodiment, a first dummy gate structure 20A and a second dummy gate structure 20B may be respectively disposed below the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B, thereby reducing the difference between the topography below the critical dimension monitoring pattern 50A and the topography below the resistance monitoring pattern 50B. Moreover, the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B may be formed together by the same manufacturing process, so the thickness TK1 of each critical dimension monitoring pattern 50A in the vertical direction Z and the thickness TK2 of each resistance monitoring pattern 50B in the vertical direction Z may be substantially equal, and the position of each critical dimension monitoring pattern 50A in the vertical direction Z and the position of each resistance monitoring pattern 50B in the vertical direction Z may be substantially at the same height.

[0062] For example, the bottom surface BS1 of at least one of the plurality of critical dimension monitoring patterns 50A and the bottom surface BS2 of at least one of the plurality of resistance monitoring patterns 50B can be substantially coplanar, and the top surface TS1 of at least one of the plurality of critical dimension monitoring patterns 50A and the top surface TS2 of at least one of the plurality of resistance monitoring patterns 50B can be substantially coplanar. In addition, the thickness TK1 of each critical dimension monitoring pattern 50A in the vertical direction Z can also be regarded as the length of each critical dimension monitoring pattern 50A in the vertical direction Z, and the thickness TK2 of each resistance monitoring pattern 50B in the vertical direction Z can also be regarded as the length of each resistance monitoring pattern 50B in the vertical direction Z. In some embodiments, considering the influence of manufacturing process uniformity, the length of at least one of the plurality of critical dimension monitoring patterns 50A in the vertical direction Z can be substantially equal to the length of at least one of the plurality of resistance monitoring patterns 50B in the vertical direction Z with a tolerance of ±5%, but not limited thereto.

[0063] In addition, the distance DS1 in the vertical direction Z between the bottom surface BS1 of at least one of the plurality of critical dimension monitoring patterns 50A and the top surface 10T of the substrate 10 can be substantially equal to the distance DS2 in the vertical direction Z between the bottom surface BS2 of at least one of the plurality of resistance monitoring patterns 50B and the top surface 10T of the substrate 10. However, in some embodiments, considering the influence of manufacturing process uniformity, the distance DS1 in the vertical direction Z between the bottom surface BS1 of at least one of the plurality of critical dimension monitoring patterns 50A and the top surface 10T of the substrate 10 can be substantially equal to the distance DS2 in the vertical direction Z between the bottom surface BS2 of at least one of the plurality of resistance monitoring patterns 50B and the top surface 10T of the substrate 10 with a tolerance of ±5%, but not limited thereto.

[0064] In some embodiments, the critical dimension monitoring pattern 50A can be used to monitor the fabrication status (such as line width and / or thickness) of components (such as a wire) formed of the conductive material 50 in the integrated circuit structure, while the resistance monitoring pattern 50B can be used to monitor the conductive properties of this component. In some embodiments, the critical dimension monitoring pattern 50A can be used for optical measurements, such as SCD (spectroscopic critical dimension) measurements performed using spectroscopic ellipsometry and / or reflectometry, but not limited thereto. Therefore, although the length of each critical dimension monitoring pattern 50A in the vertical direction Z may be substantially equal to the length of each resistance monitoring pattern 50B in the vertical direction Z, the arrangement of multiple critical dimension monitoring patterns 50A and the arrangement of multiple resistance monitoring patterns 50B can be different from each other according to the requirements of the above measurement methods. For example, the distance between two adjacent critical dimension monitoring patterns 50A can be different from the distance between two adjacent such resistance monitoring patterns 50B, and when multiple critical dimension monitoring patterns 50A are arranged in an equally spaced design and multiple resistance monitoring patterns 50B are also arranged in an equally spaced design, the pitch PC1 in the horizontal direction between multiple critical dimension monitoring patterns 50A can be different from the pitch PC2 in the horizontal direction between multiple resistance monitoring patterns 50B, but not limited thereto.

[0065] In some embodiments, the monitoring structure 101 may further include an isolation structure 12 disposed in the substrate 10, and at least a part of the isolation structure 12 may be disposed in the second region R2 of the substrate 10, while the second dummy gate structure 20B may be disposed on the isolation structure 12 in the vertical direction Z. The isolation structure 12 may include a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride, or other suitable insulating materials. In some embodiments, the monitoring structure 101 may further include a gate structure 20C and source / drain regions 22. Another part of the isolation structure 12 may be disposed in a third region R3 of the substrate 10 to define an active region corresponding to a transistor structure in the third region R3 of the substrate 10. The gate structure 20C may be disposed on this active region and the source / drain regions 22 may be disposed in this active region, thereby forming a transistor structure. In other words, the gate structure 20C and the source / drain regions 22 may be part of the transistor structure, while the first dummy gate structure 20A and the second dummy gate structure 20B may be dummy pattern structures respectively and may be in an electrically floating state respectively, but not limited thereto. In addition, the above dielectric layer 30 and dielectric layer 40 may also be disposed on the third region R3 of the substrate 10, and the gate structure 20C may be formed together with the first dummy gate structure 20A and the second dummy gate structure 20B by the same manufacturing process and have the same material composition.

[0066] In some embodiments, the first dummy gate structure 20A may be directly disposed on the substrate 10, that is, the above isolation structure 12 may not be disposed below the first dummy gate structure 20A and the critical dimension monitoring pattern 50A, thereby reducing the interference during the measurement of the critical dimension monitoring pattern 50A and / or reducing the measurement calculation complexity of the critical dimension monitoring pattern 50A, especially when the critical dimension monitoring pattern 50A is measured by the above optical method, but not limited thereto.

[0067] Please refer to Figure 1 and Figure 2 。 Figure 2 FIG. is a schematic diagram showing a manufacturing method of the monitoring structure according to an embodiment of the present invention. As Figure 1, the manufacturing method of the monitoring structure 101 in this embodiment may include the following steps. Form a first dummy gate structure 20A and a second dummy gate structure 20B on the substrate 10. The first dummy gate structure 20A is formed on the first region R1 of the substrate 10, and the second dummy gate structure 20B is formed on the second region R2 of the substrate 10. Form a plurality of critical dimension monitoring patterns 50A on the first region R1 of the substrate 10. The first dummy gate structure 20A is located between the substrate 10 and the critical dimension monitoring patterns 50A in the vertical direction Z. Form a plurality of resistance monitoring patterns 50B on the second region R2 of the substrate 10. The second dummy gate structure 20B is located between the substrate 10 and the resistance monitoring patterns 50B in the vertical direction Z.

[0068] Further illustration, the manufacturing method of this embodiment may include but is not limited to the following steps. As Figure 1 shown in Figure 2 , in step S1, the first dummy gate structure 20A, the second dummy gate structure 20B, and the gate structure 20C may be formed on the substrate 10 by the same manufacturing process, and the first dummy gate structure 20A, the second dummy gate structure 20B, and the gate structure 20C may be respectively formed on the first region R1, the second region R2, and the third region R3 of the substrate 10. In addition, the manufacturing method of this embodiment may further include forming an isolation structure 12 in the substrate 10 and forming source / drain regions 22 in the substrate 10 of the third region R3. At least a part of the isolation structure 12 may be located in the second region R2 of the substrate 10, and the second dummy gate structure 20B may be formed on the isolation structure 12 in the vertical direction Z, while the first dummy gate structure 20A may be directly formed on the substrate 10. Then, a dielectric layer 30 may be formed to cover the substrate 10 and the first dummy gate structure 20A, the second dummy gate structure 20B, and the gate structure 20C on the substrate 10.

[0069] After that, step S2 may be performed. A dielectric layer 40 is formed on the dielectric layer 30, and critical dimension monitoring patterns 50A and resistance monitoring patterns 50B are formed in the dielectric layer 40, and the critical dimension monitoring patterns 50A and the resistance monitoring patterns 50B may be formed by the same manufacturing process. For example, trenches may be formed in the dielectric layer 40 and conductive material 50 is formed to fill the trenches, and then a planarization manufacturing process (such as a chemical mechanical polishing manufacturing process or other suitable planarization methods) is performed on the conductive material 50 to remove the conductive material 50 outside the trenches to form the critical dimension monitoring patterns 50A and the resistance monitoring patterns 50B.

[0070] The following will describe different embodiments of the present invention. For the sake of simplicity, the following description mainly details the differences between the embodiments, and will not repeat the same parts. In addition, the same elements in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0071] Please refer to Figure 3 。 Figure 3 which is a schematic diagram of the monitoring structure 102 according to the second embodiment of the present invention. As Figure 3 shown, in some embodiments, another part of the isolation structure 12 can be disposed in the first region R1 of the substrate 10, and the first dummy gate structure 20A can be disposed on the isolation structure 12 in the vertical direction Z, so that the topography and / or structure composition below the critical dimension monitoring pattern 50A can be more consistent with the topography and / or structure composition below the resistance monitoring pattern 50B.

[0072] Please refer to Figure 4 。 Figure 4 which is a schematic diagram of the monitoring structure 103 according to the third embodiment of the present invention. As Figure 4 shown, in some embodiments, the above-mentioned isolation structure 12 may not be disposed in both the first region R1 and the second region R2 of the substrate 10. Therefore, the first dummy gate structure 20A and the second dummy gate structure 20B can be directly disposed on the substrate 10, so that the topography and / or structure composition below the critical dimension monitoring pattern 50A can be more consistent with the topography and / or structure composition below the resistance monitoring pattern 50B.

[0073] Please refer to Figure 5 。 Figure 5 which is a schematic diagram of the monitoring structure 104 according to the fourth embodiment of the present invention. As Figure 5 shown, in some embodiments, the monitoring structure 104 may further include a dielectric layer 32 and a plurality of dummy metal patterns 34 disposed on the substrate 10. The dielectric layer 32 can be disposed between the dielectric layer 30 and the dielectric layer 40, and the dielectric layer 32 can include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride, fluorosilicate glass, low-k dielectric materials or other suitable dielectric materials. The dummy metal patterns 34 can be disposed in the dielectric layer 32. A part of the dummy metal pattern 34 (such as the first dummy metal pattern 34A) can be disposed between the first dummy gate structure 20A and the critical dimension monitoring pattern 50A in the vertical direction Z, and another part of the dummy metal pattern 34 (such as the second dummy metal pattern 34B) can be disposed between the second dummy gate structure 20B and the resistance monitoring pattern 50B in the vertical direction Z. In addition, the dummy metal patterns 34 can be electrically separated from the critical dimension monitoring pattern 50A, the resistance monitoring pattern 50B, the first dummy gate structure 20A, and the second dummy gate structure 20B.

[0074] In the manufacturing method of the monitoring structure 104, a plurality of dummy metal patterns 34 can be formed on the substrate 10. The dummy metal patterns 34 can be formed of the same material and by the same manufacturing process as the metal wires in the integrated circuit structure (e.g., the metal wires corresponding to the transistor structures in the third region R3), but the dummy metal patterns 34 can be electrically separated from these metal wires and have the property of electrical floating, but not limited thereto. In addition, in some embodiments, a part of the dielectric layer 40 can be located between the critical dimension monitoring pattern 50A and the first dummy metal pattern 34A in the vertical direction Z, and another part of the dielectric layer 40 can be located between the resistance monitoring pattern 50B and the second dummy metal pattern 34B in the vertical direction Z. The components formed of the conductive material 50 in the integrated circuit structure and formed by the same manufacturing process as the critical dimension monitoring pattern 50A and the resistance monitoring pattern 50B can include a part of the dual damascene conductive structure, but not limited thereto.

[0075] In summary, in the monitoring structure of the present invention and its manufacturing method, a dummy gate structure can be disposed below the critical dimension monitoring pattern and the resistance monitoring pattern, thereby reducing the topographical differences in the regions corresponding to the critical dimension monitoring pattern and the resistance monitoring pattern respectively, and further improving the correlation between the measurement results of the critical dimension monitoring and the resistance monitoring, which is helpful for the relevant manufacturing process control and / or manufacturing process adjustment.

[0076] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A monitoring structure, comprising: A substrate having a first region and a second region; A plurality of critical dimension monitoring patterns disposed on the first region of the substrate; A plurality of resistance monitoring patterns disposed on the second region of the substrate; A first dummy gate structure disposed on the first region of the substrate and located between the substrate and the plurality of critical dimension monitoring patterns in a vertical direction; A second dummy gate structure disposed on the second region of the substrate and located between the substrate and the plurality of resistance monitoring patterns in the vertical direction; And A plurality of dummy metal patterns disposed on the substrate, wherein a part of the plurality of dummy metal patterns is disposed between the first dummy gate structure and the plurality of critical dimension monitoring patterns in the vertical direction, and another part of the plurality of dummy metal patterns is disposed between the second dummy gate structure and the plurality of resistance monitoring patterns in the vertical direction.

2. The monitoring structure according to claim 1, further comprising: An isolation structure disposed in the substrate, wherein at least a part of the isolation structure is disposed in the second region of the substrate, and the second dummy gate structure is disposed on the isolation structure in the vertical direction.

3. The monitoring structure according to claim 2, wherein the first dummy gate structure is directly disposed on the substrate.

4. The monitoring structure according to claim 2, wherein another part of the isolation structure is disposed in the first region of the substrate, and the first dummy gate structure is disposed on the isolation structure in the vertical direction.

5. The monitoring structure according to claim 1, wherein the bottom surface of one of the plurality of critical dimension monitoring patterns is coplanar with the bottom surface of one of the plurality of resistance monitoring patterns.

6. The monitoring structure according to claim 1, wherein the top surface of one of the plurality of critical dimension monitoring patterns is coplanar with the top surface of one of the plurality of resistance monitoring patterns.

7. The monitoring structure according to claim 1, wherein the length of one of the plurality of critical dimension monitoring patterns in the vertical direction is substantially equal to the length of one of the plurality of resistance monitoring patterns in the vertical direction under a tolerance of ±5%.

8. The monitoring structure according to claim 1, wherein the distance between the bottom surface of one of the plurality of critical dimension monitoring patterns and the top surface of the substrate in the vertical direction is substantially equal to the distance between the bottom surface of one of the plurality of resistance monitoring patterns and the top surface of the substrate in the vertical direction under a tolerance of ±5%.

9. The monitoring structure according to claim 1, wherein the distance between two adjacent ones of the plurality of critical dimension monitoring patterns is different from the distance between two adjacent ones of the plurality of resistance monitoring patterns.

10. The monitoring structure according to claim 1, wherein the material composition of each of the critical dimension monitoring patterns is the same as the material composition of each of the resistance monitoring patterns.

11. The monitoring structure according to claim 1, wherein the material composition of the first dummy gate structure is the same as the material composition of the second dummy gate structure.

12. The monitoring structure as claimed in claim 1, wherein the plurality of dummy metal patterns are electrically separated from the plurality of critical dimension monitoring patterns, the plurality of resistance monitoring patterns, the first dummy gate structure, and the second dummy gate structure.

13. A method of manufacturing a monitoring structure, comprising: forming a first dummy gate structure and a second dummy gate structure on a substrate, wherein the first dummy gate structure is formed on a first region of the substrate, and the second dummy gate structure is formed on a second region of the substrate; forming a plurality of critical dimension monitoring patterns on the first region of the substrate, wherein the first dummy gate structure is located between the substrate and the plurality of critical dimension monitoring patterns in a vertical direction; forming a plurality of resistance monitoring patterns on the second region of the substrate, wherein the second dummy gate structure is located between the substrate and the plurality of resistance monitoring patterns in the vertical direction; and forming a plurality of dummy metal patterns on the substrate, wherein a part of the plurality of dummy metal patterns is located between the first dummy gate structure and the plurality of critical dimension monitoring patterns in the vertical direction, and another part of the plurality of dummy metal patterns is located between the second dummy gate structure and the plurality of resistance monitoring patterns in the vertical direction.

14. The method of manufacturing a monitoring structure as claimed in claim 13, further comprising: forming a gate structure on a third region of the substrate, wherein the gate structure, the first dummy gate structure, and the second dummy gate structure are formed together by the same manufacturing process.

15. The method of manufacturing a monitoring structure as claimed in claim 13, wherein the plurality of critical dimension monitoring patterns and the plurality of resistance monitoring patterns are formed together by the same manufacturing process.

16. The method of manufacturing a monitoring structure as claimed in claim 13, further comprising: forming an isolation structure in the substrate, wherein at least a part of the isolation structure is located in the second region of the substrate, and the second dummy gate structure is formed on the isolation structure in the vertical direction.

17. The method of manufacturing a monitoring structure as claimed in claim 16, wherein the first dummy gate structure is directly formed on the substrate.

18. The method of manufacturing a monitoring structure as claimed in claim 13, wherein the plurality of dummy metal patterns are electrically separated from the plurality of critical dimension monitoring patterns, the plurality of resistance monitoring patterns, the first dummy gate structure, and the second dummy gate structure.

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