Semiconductor devices

Abstract

A semiconductor device with improved reliability of a gate insulating film of a trench gate is provided. The semiconductor device includes a semiconductor substrate, a gate electrode, and a plurality of trench gates. The semiconductor substrate includes an active region and a wiring region. The trench gate extends from the active region to the wiring region. The trench gate forms a part of a transistor in the active region. The gate electrode is disposed in the wiring region and is electrically connected to the trench gate. An end of the trench gate is located in the wiring region. The gate electrode is disposed in a manner covering a gate contact formed at an end of the trench gate. The gate electrode is electrically connected to the trench gate via the gate contact. The plurality of trench gates extend only in one direction.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] In the fields of general inverters, AC servos, etc., IGBTs (Insulated Gate Bipolar Transistors) and diodes are used as power modules for variable speed control of three-phase motors from the perspective of energy saving. These IGBTs and diodes require low switching losses and low on-voltage characteristics in order to reduce inverter losses.

[0003] A trench gate IGBT is a device having a low on-voltage characteristic. For the trench gate IGBT, the shape of the end or bottom of the trench is a dominant factor in determining the reliability of the gate insulating film. Patent documents 1 and 2 disclose a structure in which a gate contact is formed on a conductor buried in the trench in order to improve the reliability of the gate insulating film at the end of the trench.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2003-309263

[0005] Patent Document 2: Japanese Patent Application Publication No. 2014-72412

[0006] In the case where multiple trench gates are arranged in a manner of crossing each other in the active region of the transistor, the opening at the intersection of the trenches is wider than the opening at the straight line portion between the intersections. Therefore, when the trenches are formed by etching, the depth of the intersection is deeper than the surrounding depth due to the microscopic loading effect. As a result, a step is generated at the bottom of the trench, and the reliability of the gate insulating film is reduced. Summary of the invention

[0007] The present invention provides a semiconductor device having a trench gate with improved reliability of a gate insulating film.

[0008] The semiconductor device to which the present invention relates includes a semiconductor substrate, a gate electrode and a plurality of trench gates. The semiconductor substrate includes an active region in which a plurality of transistors are provided and a wiring region surrounding the active region when viewed from above. The plurality of trench gates extend from the active region on the surface of the semiconductor substrate to the wiring region. The plurality of trench gates form a part of the plurality of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the plurality of trench gates. The ends of the plurality of trench gates are respectively located in the wiring region. The gate electrode is provided in a manner covering the gate contact portions formed at the ends of the plurality of trench gates. The gate electrode is electrically connected to each of the plurality of trench gates via the gate contact portions. The plurality of trench gates extend only in one direction on the surface of the semiconductor substrate.

[0009] Effects of the Invention

[0010] According to the semiconductor device of the present invention, the reliability of the gate insulating film of the trench gate is improved.

[0011] The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a top view showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 2 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0014] Figure 3 Yes means Figure 2 A cross-section of the line segment AA'.

[0015] Figure 4 Yes means Figure 2 A cross-section of the line segment BB'.

[0016] Figure 5 Yes means Figure 2 A cross-section of the line segment C-C'.

[0017] Figure 6 It is a top view showing the structure of a semiconductor device according to the second embodiment.

[0018] Figure 7 It is a top view showing the structure of a semiconductor device according to a third embodiment.

[0019] Figure 8 It is a top view showing the structure of a semiconductor device according to a fourth embodiment.

[0020] Fig. 9 It is a top view showing the structure of a semiconductor device according to a fifth embodiment.

[0021] Fig.10 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 6, Figure 2 A cross-section of the line segment AA'.

[0022] Fig.11 Yes means Figure 2 A cross-section of the line segment BB'.

[0023] Fig.12 Yes means Figure 2 A cross-section of the line segment C-C'.

[0024] Fig.13 It is a top view showing the structure of a semiconductor device according to a seventh embodiment.

[0025] Fig.14 Yes means Fig.13 A cross-section of the line segment D-D'.

[0026] Fig.15 It is a top view showing the structure of a semiconductor device according to an eighth embodiment. DETAILED DESCRIPTION

[0027] <Implementation method 1>

[0028] Figure 1 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0029] The semiconductor device includes a semiconductor substrate 10, a gate electrode 30, a gate pad 31, a finger wiring 32, and a plurality of trench gates 20. Figure 1 Although not shown, the semiconductor device is described later. Figure 2 An emitter electrode 40 is shown included.

[0030] The semiconductor substrate 10 includes an active region 1, a wiring region 2, and a terminal region 3 when viewed from above. The active region 1 is a region where a plurality of transistors are provided. The transistor in the first embodiment is an insulated gate bipolar transistor (IGBT). The wiring region 2 is provided so as to surround the active region 1. The terminal region 3 is provided so as to surround the active region 1 and the wiring region 2. A withstand voltage holding structure of a semiconductor device is provided on the semiconductor substrate 10 in the terminal region 3. The semiconductor substrate 10 is formed of, for example, a semiconductor such as Si, or a so-called wide bandgap semiconductor such as SiC or GaN.

[0031] The plurality of trench gates 20 are arranged parallel to each other. The trench gates 20 extend only along the first direction on the surface of the semiconductor substrate 10. In the following description, the first direction is the left-right direction in the top view, and the second direction is the up-down direction in the top view. Figure 1 As an example, eight trench gates 20 are shown, but the number of trench gates 20 is not limited thereto. The trench gates 20 are provided across the active region 1 and the wiring region 2 on the surface of the semiconductor substrate 10. That is, the trench gates 20 extend from the active region 1 to the wiring region 2, and the ends of the trench gates 20 are located in the wiring region 2. The details will be described later, but the trench gates 20 in the active region 1 form a part of the transistor.

[0032] The gate electrode 30 is provided in the wiring region 2. The gate electrode 30 in the first embodiment is also referred to as a gate wiring, and is provided so as to surround the active region 1. The gate electrode 30 is electrically connected to the end of the trench gate 20.

[0033] The gate pad 31 functions as a terminal for connecting to external wiring and is electrically connected to the gate electrode 30 .

[0034] The finger wiring 32 extends from the gate electrode 30 of the wiring region 2 to the active region 1. The finger wiring 32 is electrically connected to both the gate electrode 30 and the trench gate 20. Here, the finger wiring 32 extends in the second direction. The finger wiring 32 reduces the potential difference between the trench gates 20. The finger wiring 32 is not essential for the semiconductor device in the first embodiment, but it is preferable to provide the finger wiring 32.

[0035] Figure 2 is a top view showing the structure of the semiconductor device in the first embodiment. Figure 1 In the following description, n and p represent the conductivity type of the semiconductor. - Indicates that the impurity concentration is lower than n. + Indicates that the impurity concentration is higher than n. + Indicates that the impurity concentration is higher than p.

[0036] In the active area 1, n + The p-type emitter layer 11 and the p-type base layer 12 are selectively arranged as the surface layer of the semiconductor substrate 10. + The p-type emitter layer 11 and the p-type base layer 12 are alternately arranged along the first direction. In the peripheral portion of the active region 1 in the first embodiment, n-type emitter layers 11 and p-type base layers 12 are arranged in this order from the inside to the outside of the active region 1. + Although not shown in the figure, the p-type base layer 12 may include a p-type emitter layer 11 and a p-type base layer 12 on the surface of the semiconductor substrate 10. + Type contact layer.

[0037] In the wiring region 2 , a p-type well layer 13 is disposed as a surface layer of the semiconductor substrate 10 . Here, the p-type well layer 13 extends from the wiring region 2 to the periphery of the active region 1 so as to be in contact with the p-type base layer 12 at the periphery of the active region 1 .

[0038] As already described, the plurality of trench gates 20 extend from the active region 1 to the wiring region 2. The ends of the trench gates 20 are located in the wiring region 2. The configuration pitch P1 of the plurality of trench gates 20 in the second direction is, for example, greater than or equal to 0.6 μm and less than or equal to 10.0 μm. The trench width W11 at the active region 1 and the trench width W12 at the wiring region 2 are, for example, greater than or equal to 0.5 μm and less than or equal to 1.5 μm. The trench width W11 in embodiment 1 is equal to the trench width W12. The trench gate 20 includes a gate insulating film 21 and a gate conductive portion 22. The gate insulating film 21 is disposed along the inner wall of the trench. The gate conductive portion 22 is disposed inside the trench across the gate insulating film 21.

[0039] A gate contact portion 23 is provided at the end of the trench gate 20 of the wiring region 2. The gate contact portion 23 is formed on the gate conductive portion 22. The periphery of the gate contact portion 23 is surrounded by the gate conductive portion 22 when viewed from above. That is, the gate contact portion 23 is formed on the inner side compared to the edge of the gate conductive portion 22. The gate contact portion 23 is provided in an opening of an interlayer insulating film described later. The width W22 of the gate contact portion 23 is, for example, greater than or equal to 0.1 μm and less than or equal to 1.0 μm.

[0040] The gate electrode 30 is provided in the wiring region 2 in a manner covering the gate contact portion 23 formed at the end of each trench gate 20. The gate electrode 30 is electrically connected to each trench gate 20 via the gate contact portion 23. For example, the gate electrode 30 contacts the gate conductive portion 22 at the gate contact portion 23. The gate pad 31 and the trench gate 20 are electrically connected to each other via the gate electrode 30 and the gate contact portion 23 in the wiring region 2.

[0041] An emitter contact portion 41 is provided in the active region 1. The emitter contact portion 41 is provided at least at n + type emitter layer 11, and n + The emitter contact portion 41 in the first embodiment is provided so that not only the n + The emitter contact portion 41 is provided between two adjacent trench gates 20. The emitter contact portion 41 extends in the first direction similarly to the trench gate 20. The emitter contact portion 41 is formed of, for example, metal. The width W21 of the emitter contact portion 41 is, for example, greater than or equal to 0.1 μm and less than or equal to 1.0 μm.

[0042] The emitter electrode 40 is provided in the active region 1 so as to cover the emitter contact portion 41. The emitter electrode 40 is connected to the n +type emitter layer 11 is electrically connected.

[0043] Figure 3 Yes means Figure 2 A cross-section of the line segment AA' in FIG. Figure 4 Yes means Figure 2 A cross-section of the line segment BB' in FIG. Figure 5 Yes means Figure 2 In each cross-sectional view, the structure of the back side of the semiconductor substrate 10 is omitted.

[0044] like Figure 3 As shown, in the active region 1, n layers are sequentially arranged along the depth direction from the surface of the semiconductor substrate 10. + The p-type emitter layer 11, the p-type base layer 12, the n-type carrier storage layer 14 and the n-type - type drift layer 15. Taking the surface of the semiconductor substrate 10 as a reference, n + The depth of the p-type emitter layer 11 is, for example, greater than or equal to 0.1 μm and less than or equal to 2.0 μm. The depth of the p-type base layer 12 is, for example, greater than or equal to 0.5 μm and less than or equal to 3.0 μm. The depth of the n-type carrier storage layer 14 is, for example, greater than or equal to 1.0 μm and less than or equal to 6.0 μm.

[0045] The trench gate 20 of the active region 1 is n + The bottom of the trench gate 20 is connected to the n-type emitter layer 11, the p-type base layer 12 and the n-type carrier storage layer 14. - The trench gate 20 faces the type drift layer 15. The depth of the trench gate 20 is, for example, about 0.5 μm or more and 10.0 μm or less, based on the surface of the semiconductor substrate 10.

[0046] In the active region 1, the surface of the trench gate 20 is covered by the interlayer insulating film 16, but n + A part of the surface of the emitter layer 11 is not covered by the interlayer insulating film 16. The emitter contact portion 41 is formed in a region where the interlayer insulating film 16 is not provided.

[0047] The emitter electrode 40 is provided, for example, to cover the active region 1. The emitter electrode 40 is connected to the n + type emitter layer 11 is electrically connected.

[0048] like Figure 4 and Figure 5 As shown, in the wiring region 2, a p-type well layer 13 and an n-type well layer 14 are sequentially provided in the depth direction from the surface of the semiconductor substrate 10. - Type drift layer 15. Figure 5As shown, the bottom of the end portion of the trench gate 20 in the wiring region 2 is covered with the well layer 13 .

[0049] In the wiring region 2, the surface of the trench gate 20 except the gate contact 23 is covered by the interlayer insulating film 16. The gate contact 23 is located in the opening provided in the interlayer insulating film 16. The gate electrode 30 is electrically connected to the trench gate 20 via the gate contact 23.

[0050] The transistor in the first embodiment includes at least an active region 1 of n + type emitter layer 11, p-type base layer 12, n-type carrier storage layer 14, n - The type drift layer 15, the trench gate 20, the interlayer insulating film 16 and the emitter electrode 40. Figure 3 As shown, the side wall of the trench gate 20 of the active region 1, namely the gate insulating film 21 and the n + The p-type emitter layer 11, the p-type base layer 12, and the n-type carrier storage layer 14 are in contact with each other. When a voltage is applied to the gate conductive portion 22 via the gate pad 31, the gate electrode 30, and the gate contact portion 23, a channel is formed in the p-type base layer 12 in contact with the gate insulating film 21. The voltage to the gate conductive portion 22 for forming the channel is applied via the gate pad 31, the gate electrode 30, and the gate contact portion 23 of the wiring region 2.

[0051] In summary, the semiconductor device in Embodiment 1 includes a semiconductor substrate 10, a gate electrode 30, and a plurality of trench gates 20. The semiconductor substrate 10 includes an active region 1 in which a plurality of transistors are provided and a wiring region 2 surrounding the active region 1 when viewed from above. The plurality of trench gates 20 extend from the active region 1 on the surface of the semiconductor substrate 10 to the wiring region 2. The plurality of trench gates 20 form a part of the plurality of transistors in the active region 1. The gate electrode 30 is provided in the wiring region 2 and is electrically connected to the plurality of trench gates 20. The ends of the plurality of trench gates 20 are respectively located in the wiring region 2. The gate electrode 30 is provided in a manner covering the gate contact portion 23 formed at the ends of the plurality of trench gates 20. The gate electrode 30 is electrically connected to each of the plurality of trench gates 20 via the gate contact portion 23. The plurality of trench gates 20 extend only in one direction on the surface of the semiconductor substrate 10.

[0052] In such a semiconductor device, the trench gates 20 of the active region 1 do not intersect each other. In addition, the trench width W11 of the active region 1 is equal to the trench width W12 of the wiring region 2. Therefore, there is no portion where the trench widths W11 and W12 change sharply. In the extension direction of the trench gate 20, since the size of the opening of the trench does not change sharply, no microscopic load effect is generated. As a result, in the extension direction of the trench gate 20, no portion where the depth of the trench changes sharply is formed, but a trench with a substantially constant depth is formed. Since no steps are generated at the bottom of the trench, the reliability of the gate insulating film 21 at the bottom of the trench is improved.

[0053] In addition, the semiconductor substrate 10 in the first embodiment includes an emitter layer 11 of the first conductivity type, a base layer 12 of the second conductivity type, and a carrier accumulation layer 14 of the first conductivity type in the active region 1 along the depth direction from the surface of the semiconductor substrate 10. In addition, the semiconductor substrate 10 includes a well layer 13 of the second conductivity type in the wiring region 2. The plurality of trench gates 20 in the active region 1 penetrate the emitter layer 11, the base layer 12, and the carrier accumulation layer 14. The side walls of the plurality of trench gates 20 in the active region 1 are in contact with the emitter layer 11, the base layer 12, and the carrier accumulation layer 14. The bottom of each end of the plurality of trench gates 20 in the wiring region 2 is covered by the well layer 13. In the first embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type is described, but the first conductivity type may be p-type and the second conductivity type may be n-type. In addition, the emitter layer 11 is sometimes referred to as a source layer.

[0054] In such a semiconductor device, the well layer 13 covers the bottom of the end of the trench gate 20. Therefore, the reliability of the gate insulating film 21 at the end of the trench is improved, and the main withstand voltage of the semiconductor device is improved. In addition, the carrier accumulation layer 14 also has the effect of reducing the on-voltage.

[0055] <Implementation method 2>

[0056] A semiconductor device in Embodiment 2 will be described. Embodiment 2 is a subordinate concept of Embodiment 1. In Embodiment 2, the same components as those in Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0057] Figure 6 is a top view showing the structure of a semiconductor device in Embodiment 2. Figure 1 An enlarged view of area P is shown.

[0058] The trench width W12 at the end of the trench gate 20 is wider than the trench width W11 of the active region 1. The trench width W12 of the wiring region 2 is, for example, greater than or equal to 1.1 times and less than or equal to 2.0 times the trench width W11 of the active region 1. The thickness Tox of the gate insulating film 21 of the active region 1 and the wiring region 2 is constant.

[0059] The trench gate 20 includes a transition region where the trench width of the wiring region 2 gradually widens as it approaches the end. The transition region is located in the direction of the active region 1 relative to the end of the trench gate 20 where the gate contact 23 is provided. The expansion angle A1 of the trench width of the transition region is less than 45 degrees relative to the first direction, which is the extension direction of the trench gate 20.

[0060] The effect achieved by the groove width W12 wider than the groove width W11 is described. In order to prevent the gate and the emitter from short-circuiting, the gate contact portion 23 needs to be arranged on the inner side compared to the edge of the gate conductive portion 22. In order to manufacture such a structure, considering the robustness of the dimensional fluctuations of each element, the alignment deviation of each element, etc., it is preferred that the difference between the groove width W12 of the wiring area 2 and the width W22 of the gate contact portion 23 is large. However, the smaller the width W22 of the gate contact portion 23, the greater the contact resistance between the gate conductive portion 22 and the gate electrode 30, and the on-off loss is deteriorated. Therefore, it is preferred that the groove width W12 is large. On the other hand, the larger the groove width W11 of the active area 1, the greater the parasitic capacitance, and the on-off loss is deteriorated.

[0061] The trench width W12 in Embodiment 2 is wider than the trench width W11. With such a structure, an increase in parasitic capacitance is prevented, and robustness against manufacturing fluctuations is improved.

[0062] The effect achieved by the expansion angle A1 less than 45 degrees is described. By making the expansion angle A1 less than 45 degrees, the groove width changes smoothly in the transition region. In other words, there is no portion where the groove width suddenly widens. Therefore, a shape in which the depth of the groove changes sharply due to the microscopic load effect will not be formed. The depth of the groove in embodiment 2 changes smoothly. The formation of steps at the bottom of the groove is prevented. As a result, the reliability of the gate insulating film 21 at the bottom of the groove is improved.

[0063] In Embodiment 2, an example is shown in which the trench width in the transition region changes linearly. However, the state of change in the trench width is not limited to this. The expansion of the trench width in the transition region may also be curved. The planar shape of the trench gate 20 described above is controlled by a mask pattern in the manufacturing process.

[0064] <Implementation method 3>

[0065] A semiconductor device in Embodiment 3 will be described. Embodiment 3 is a subordinate concept of Embodiment 1. In Embodiment 3, the same components as those in Embodiment 1 or 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0066] Figure 7 is a top view showing the structure of a semiconductor device in Embodiment 3, Figure 1 An enlarged view of the region P is shown. As in the second embodiment, the trench width W12 at the end of the trench gate 20 is wider than the trench width W11 in the active region 1 .

[0067] In Embodiment 3, the thickness Tox2 of the gate insulating film 21 in the transition region and the end portion is thicker than the thickness Tox of the gate insulating film 21 in the active region 1. The thickness Tox of the gate insulating film 21 is, for example, greater than or equal to 10 nm and less than or equal to 200 nm. The thickness Tox2 of the gate insulating film 21 is, for example, greater than or equal to 1.1 times and less than or equal to 5.0 times the thickness Tox of the gate insulating film 21.

[0068] With such a structure, the reliability of the gate insulating film 21 at the end of the trench is improved.

[0069] The gate insulating film 21 of the wiring region 2 is formed, for example, by oxidation, nitridation or deposition treatment in a process different from that of the gate insulating film 21 of the active region 1. Alternatively, for example, after a high-concentration first conductivity type layer is disposed at the end of the trench, it is formed by utilizing an oxidation-accelerated diffusion effect achieved by a heat treatment such as oxidation.

[0070] <Implementation method 4>

[0071] A semiconductor device in Embodiment 4 will be described. Embodiment 4 is a subordinate concept of Embodiment 1. In Embodiment 4, the same components as those in any of Embodiments 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0072] Figure 8 is a top view showing the structure of a semiconductor device in Embodiment 4, Figure 1 An enlarged view of the region P is shown. The semiconductor substrate 10 includes a first active region 1A and a second active region 1B.

[0073] In the first active region 1A, n layers are selectively arranged along a first direction as a surface layer of the semiconductor substrate 10. + Although the cross-sectional view is omitted, n-type emitter layer 11 and p-type base layer 12 are provided in order from the surface of the semiconductor substrate 10 in the first active region 1A in the depth direction. +The p-type emitter layer 11, the p-type base layer 12, the n-type carrier storage layer 14 and the n-type - Type drift layer 15.

[0074] In the second active region 1B, no n + The p-type emitter layer 11 is disposed only as the surface layer of the semiconductor substrate 10, and the p-type base layer 12 is disposed only as the surface layer of the semiconductor substrate 10. Although the cross-sectional view is omitted, the p-type base layer 12, the n-type carrier storage layer 14 and the n-type carrier storage layer 15 are disposed in this order from the surface of the semiconductor substrate 10 in the second active region 1B in the depth direction. - Type drift layer 15.

[0075] The trench gate 20 extends from the first active region 1A to the wiring region 2. The trench gate 20 of the first active region 1A is + The p-type emitter layer 11, the p-type base layer 12, and the n-type carrier storage layer 14 are connected. The gate insulating film 21 constituting the side wall of the trench gate 20 is connected to the n-type base layer 14. + The p-type emitter layer 11 is in contact with the p-type base layer 12 and the n-type carrier storage layer 14. When a voltage is applied to the gate conductive portion 22 via the gate pad 31, the gate electrode 30 and the gate contact portion 23, a channel is formed in the p-type base layer 12 in contact with the gate insulating film 21.

[0076] The semiconductor device in the fourth embodiment includes at least one dummy trench gate 20A in addition to the trench gates 20. The dummy trench gate 20A is provided in the second active region 1B and extends in the first direction similarly to the trench gate 20. However, the dummy trench gate 20A does not extend in the wiring region 2, and the end of the dummy trench gate 20A is located in the second active region 1B. For example, the trench width and arrangement pitch of the dummy trench gate 20A are respectively the same as the trench width and arrangement pitch of the trench gate 20. With respect to the dummy trench gate 20A, the trench gate 20 is sometimes referred to as an active trench gate.

[0077] The dummy trench gate 20A includes a gate insulating film 21 and a gate conductive portion 22, similarly to the trench gate 20. The dummy trench gate 20A penetrates the p-type base layer 12 and the n-type carrier storage layer 14. The gate insulating film 21 constituting the side wall of the dummy trench gate 20A does not contact the n-type base layer 12. + The p-type emitter layer 11 is in contact with the p-type base layer 12 and the n-type carrier storage layer 14 .

[0078] A dummy contact portion 23A is provided at the end of the dummy trench gate 20A of the second active region 1B. The dummy contact portion 23A is formed on the gate conductive portion 22 of the dummy trench gate 20A. The periphery of the dummy contact portion 23A is surrounded by the gate conductive portion 22 when viewed from above. That is, the dummy contact portion 23A is formed on the inner side compared to the edge of the gate conductive portion 22.

[0079] The emitter electrode 40 is formed by connecting the dummy contact portion 23A on the dummy trench gate 20A and the n + The emitter electrode 40 is provided so as to cover the emitter contact portion 41 on the type emitter layer 11. The emitter electrode 40 is electrically connected to the dummy trench gate 20A via the dummy contact portion 23A. The emitter electrode 40 is electrically connected to the n type emitter layer 11 via the emitter contact portion 41. + type emitter layer 11 is electrically connected.

[0080] Thus, dummy trench gate 20A is connected to emitter electrode 40. No channel is formed in p-type base layer 12 in contact with gate insulating film 21. By replacing part of trench gate 20 with dummy trench gate 20A, parasitic capacitance of the semiconductor device is reduced.

[0081] <Implementation method 5>

[0082] A semiconductor device in Embodiment 5 will be described. Embodiment 5 is a subordinate concept of Embodiment 1. In Embodiment 5, the same components as those in any of Embodiments 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0083] Fig. 9 is a top view showing the structure of a semiconductor device in Embodiment 5, Figure 1 The semiconductor device of the fifth embodiment is different from the semiconductor device of the fourth embodiment in the connection structure between the dummy trench gate 20A and the emitter electrode 40 .

[0084] The emitter contact portion 41 of the second active region 1B is provided in a manner that straddles the dummy trench gate 20A. That is, the emitter contact portion 41 is provided on the dummy trench gate 20A and on the p-type base layer 12 disposed on both sides of the dummy trench gate 20A. In the fifth embodiment, the emitter contact portion 41 of the second active region 1B extends to the adjacent first active region 1A. In the first active region 1A, the emitter contact portion 41 is provided on the n-type base layer 12. + On the p-type emitter layer 11 and the p-type base layer 12.

[0085] The emitter electrode 40 is disposed in the active region 1 and is connected to the dummy trench gate 20A and the n + The emitter layer 11 is electrically connected.

[0086] With such a structure, the width of the emitter contact portion 41 is widened, so that the embedding property of the emitter electrode 40 in the emitter contact portion 41 is improved.

[0087] <Implementation method 6>

[0088] A semiconductor device in Embodiment 6 will be described. Embodiment 6 is a subordinate concept of Embodiment 1. In Embodiment 6, the same components as those in Embodiments 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0089] The planar structure of the semiconductor device in the sixth embodiment is the same as the planar structure of the semiconductor device in the first embodiment. Figure 2 The structures shown are the same. Fig.10 is a cross-sectional view showing the structure of a semiconductor device in Embodiment 6, and is a view showing Figure 2 A cross-section of the line segment AA' in FIG. Fig.11 Yes means Figure 2 A cross-section of the line segment BB' in FIG. Fig.12 Yes means Figure 2 A cross-section of the line segment CC' in FIG.

[0090] The trench gate 20 in the active region 1 is similar to that in the first embodiment. + The p-type emitter layer 11, the p-type base layer 12 and the n-type carrier storage layer 14 are connected. + The emitter layer 11, the p-type base layer 12, and the n-type carrier storage layer 14 are in contact with each other. - The type drift layer 15 is opposite.

[0091] The gate insulating film 21 of the trench gate 20 divides the gate conductive portion into an upper first gate conductive portion 22A and a lower second gate conductive portion 22B within the trench.

[0092] The bottom of the first gate conductive portion 22A is located below the p-type base layer 12. For example, the bottom of the first gate conductive portion 22A is located below the boundary between the p-type base layer 12 and the n-type carrier accumulation layer 14. Here, the bottom of the first gate conductive portion 22A is located at the n-type carrier accumulation layer 14.

[0093] The bottom of the second gate conductive portion 22B is located below the n-type carrier storage layer 14. - Type drift layer 15.

[0094] With such a structure, the feedback capacitance of the trench gate 20 is reduced.

[0095] <Implementation method 7>

[0096] A semiconductor device in Embodiment 7 will be described. Embodiment 7 is a subordinate concept of Embodiment 1. In Embodiment 7, the same components as those in any of Embodiments 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0097] Fig.13 is a top view showing the structure of a semiconductor device in Embodiment 7. Figure 1 An enlarged view of region Q is shown. Fig.14 Yes means Fig.13 A cross-section of the line segment D-D' in FIG.

[0098] The gate insulating film 21 of the trench gate 20 in the active region 1 divides the gate conductive portion into an upper first gate conductive portion 22A and a lower second gate conductive portion 22B within the trench, similarly to the sixth embodiment.

[0099] A portion of the second gate conductive portion 22B of the active region 1 is exposed on the surface of the semiconductor substrate 10. A shield contact portion 23B is provided on a portion of the second gate conductive portion 22B exposed on the surface. The shield contact portion 23B is surrounded by the second gate conductive portion 22B when viewed from above. That is, the shield contact portion 23B is formed on the inner side compared to the edge of the second gate conductive portion 22B.

[0100] In the active region 1 , the surface of the first gate conductive portion 22A is covered by the interlayer insulating film 16 , but the surface of the shield contact portion 23B is not covered by the interlayer insulating film 16 . In other words, the shield contact portion 23B is formed in the opening of the interlayer insulating film 16 .

[0101] Similar to the first embodiment, the emitter contact portion 41 is provided between two adjacent trench gates 20 and extends in the first direction.

[0102] The emitter electrode 40 is connected to the shield contact portion 23B and the n + The emitter electrode 40 is provided so as to cover the emitter contact portion 41 on the n-type emitter layer 11. The emitter electrode 40 is electrically connected to the second gate conductive portion 22B via the shield contact portion 23B. The emitter electrode 40 is electrically connected to the n-type emitter layer 11 via the emitter contact portion 41. + type emitter layer 11 is electrically connected.

[0103] With such a structure, the potential of the second gate conductive portion 22B is stabilized.

[0104] <Implementation method 8>

[0105] A semiconductor device in Embodiment 8 will be described. Embodiment 8 is a subordinate concept of Embodiment 1. In Embodiment 8, the same reference numerals are given to the same components as those in any of Embodiments 1 to 7, and their detailed descriptions are omitted.

[0106] Fig.15 is a top view showing the structure of a semiconductor device in Embodiment 8, Figure 1 The diagram shows an enlarged view of the region Q. The structure of the trench gate 20 in the eighth embodiment is the same as that of the trench gate 20 in the seventh embodiment. In the eighth embodiment, the connection structure between the emitter electrode 40 and the second gate conductive portion 22B is different from that in the seventh embodiment.

[0107] The emitter contact portion 41 is provided between two adjacent trench gates 20 and extends in the first direction, similarly to the first embodiment. Furthermore, the emitter contact portion 41 is provided so as to straddle the second gate conductive portion 22B exposed on the surface of the semiconductor substrate 10. That is, the emitter contact portion 41 is also provided on the second gate conductive portion 22B exposed on the surface of the semiconductor substrate 10 and also extends in the second direction. Such an emitter contact portion 41 has, for example, a lattice shape.

[0108] The emitter electrode 40 is provided so as to cover the emitter contact portion 41. The emitter electrode 40 is connected to the second gate conductive portion 22B and the emitter contact portion 41 via the emitter contact portion 41. + type emitter layer 11 is electrically connected.

[0109] With such a structure, it is easy to form contact between the emitter electrode 40 and the second gate conductive portion 22B.

[0110] The plurality of trench gates 20 described above are part of the components of the transistor formed in the active region 1. In each embodiment, an IGBT is described as an example of the transistor, but the same effect can be achieved when the transistor is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0111] Even when the structure of the trench gate 20 described in each embodiment is applied only to a part of the semiconductor substrate 10 , the same effect can be obtained.

[0112] In the case where the semiconductor device is an RC-IGBT (Reverse Conducting IGBT), the IGBT element included in the RC-IGBT corresponds to the above-mentioned transistor. That is, the trench gate 20 can also be a structural element of the IGBT element included in the RC-IGBT. The RC-IGBT is a semiconductor device in which an IGBT region including an IGBT element and a diode region including a diode element are selectively formed on a semiconductor substrate 10. In the case where the semiconductor device is an RC-IGBT, the above-mentioned active region 1 is a region including an IGBT region and a diode region. In particular, when the structure of the trench gate 20 shown in each embodiment is applied to the boundary between the IGBT region and the wiring region 2, the same effect as above is obtained.

[0113] The semiconductor substrate 10 may be a FZ substrate, an MCZ substrate, an epitaxial substrate, etc., and the effects of the embodiments are achieved regardless of the type of the substrate. Also, the effects of the embodiments are achieved regardless of the withstand voltage level of the semiconductor substrate 10 or the semiconductor device.

[0114] In addition, the present invention can freely combine the various embodiments, or appropriately modify or omit the various embodiments.

[0115] Although the present invention has been described in detail, the above description is in all aspects illustrative and the present invention is not limited thereto, and numerous modifications not shown are conceivable.

[0116] Description of the label

[0117] 1 active region, 1A first active region, 1B second active region, 2 wiring region, 3 termination region, 10 semiconductor substrate, 11 emitter layer, 12 base layer, 13 well layer, 14 carrier storage layer, 15 drift layer, 16 interlayer insulating film, 20 trench gate, 20A dummy trench gate, 21 gate insulating film, 22 gate conductive portion, 22A first gate conductive portion, 22B second gate conductive portion, 23 gate contact portion, 23A dummy contact portion, 23B shield contact portion, 30 gate electrode, 31 gate pad, 32 finger wiring, 40 emitter electrode, 41 emitter contact portion, A1 expansion angle, Tox thickness, Tox2 thickness, W11 trench width, W12 trench width.

Claims

1. A semiconductor device comprising: A semiconductor substrate including, when viewed from above, an active region in which a plurality of transistors are provided and a wiring region surrounding the active region; a plurality of trench gates extending from the active region of the surface of the semiconductor substrate to the wiring region and forming a part of the plurality of transistors in the active region; as well as a gate electrode disposed in the wiring region and electrically connected to the plurality of trench gates; The ends of each of the plurality of trench gates are located in the wiring region, The gate electrode is provided so as to cover the gate contact portion formed at the end portion of each of the plurality of trench gates, and is electrically connected to each of the plurality of trench gates via the gate contact portion. The plurality of trench gates extend only along one direction of the surface of the semiconductor substrate. The semiconductor device further comprises: at least one dummy trench gate disposed in the active region of the surface of the semiconductor substrate; and an emitter electrode disposed in the active region, The semiconductor substrate comprises, in the active region: a first active region in which a first conductive type emitter layer and a second conductive type base layer are selectively arranged on the surface of the semiconductor substrate along the one direction in which the plurality of trench gates extend; as well as a second active region in which the base layer is arranged on the surface of the semiconductor substrate but the emitter layer is not arranged; The emitter layer and the base layer are provided in a depth direction from the surface of the semiconductor substrate in the first active region. The base layer is provided in the second active region in a depth direction from the surface of the semiconductor substrate without providing the emitter layer. The plurality of trench gates are disposed in the first active region and penetrate the emitter layer and the base layer. The side walls of the plurality of trench gates are in contact with the emitter layer and the base layer. The at least one dummy trench gate is disposed in the second active region and penetrates the base layer. The side wall of the at least one dummy trench gate contacts the base layer but does not contact the emitter layer. The emitter electrode is arranged to cover the emitter contact portion formed on the at least one dummy trench gate, the emitter layer, and the base layer arranged on both sides of the dummy trench gate, and is electrically connected to the at least one dummy trench gate and the emitter layer via the emitter contact portion.

2. A semiconductor device comprising: A semiconductor substrate including, when viewed from above, an active region in which a plurality of transistors are provided and a wiring region surrounding the active region; a plurality of trench gates extending from the active region of the surface of the semiconductor substrate to the wiring region and forming a part of the plurality of transistors in the active region; as well as a gate electrode disposed in the wiring region and electrically connected to the plurality of trench gates; The ends of each of the plurality of trench gates are located in the wiring region, The gate electrode is provided so as to cover the gate contact portion formed at the end portion of each of the plurality of trench gates, and is electrically connected to each of the plurality of trench gates via the gate contact portion. The plurality of trench gates extend only along one direction of the surface of the semiconductor substrate. The semiconductor substrate includes, in the active region, an emitter layer of a first conductivity type, a base layer of a second conductivity type, and a carrier storage layer of the first conductivity type in a depth direction from the surface of the semiconductor substrate. The plurality of trench gates in the active region penetrate the emitter layer, the base layer, and the carrier storage layer. The side walls of the plurality of trench gates in the active region are in contact with the emitter layer, the base layer, and the carrier storage layer. Each of the plurality of trench gates of the active region comprises: a gate insulating film provided along the inner wall of the trench formed in the semiconductor substrate and in contact with the emitter layer, the base layer, and the carrier storage layer; as well as a gate conductive portion disposed inside the trench via the gate insulating film, The gate insulating film divides the gate conductive portion into an upper first gate conductive portion and a lower second gate conductive portion in the interior of the trench. The bottom of the first gate conductive portion is located below the base layer. The bottom of the second gate conductive portion is located below the carrier storage layer. The semiconductor device further includes an emitter electrode provided in the active region. A portion of the second gate conductive portion of the active region is exposed on the surface of the semiconductor substrate. The emitter electrode is provided so as to cover an emitter contact portion in which a contact portion formed on the part of the second gate conductive portion and a contact portion formed on the emitter layer communicate with each other, and is electrically connected to the second gate conductive portion and the emitter layer via the emitter contact portion.

3. The semiconductor device according to claim 1 or 2, wherein: The trench width at the end of each of the plurality of trench gates is wider than the trench width of the active region, Each of the plurality of trench gates includes a transition region in which the trench width of the wiring region gradually widens as it approaches the end portion. An expansion angle of the trench width of the transition region is smaller than 45 degrees relative to the one direction in which the plurality of trench gates extend.

4. The semiconductor device according to claim 3, wherein: Each of the plurality of trench gates comprises: a gate insulating film provided along an inner wall of a trench formed in the semiconductor substrate; as well as a gate conductive portion disposed inside the trench via the gate insulating film, The gate contact portion is formed on the gate conductive portion, The thickness of the gate insulating film in the transition region and the end portion is thicker than the thickness of the gate insulating film in the active region.

5. The semiconductor device according to claim 1 or 2, wherein: the semiconductor substrate, The active region includes an emitter layer of the first conductivity type, a base layer of the second conductivity type, and a carrier storage layer of the first conductivity type in a depth direction from the surface of the semiconductor substrate. The wiring region includes a well layer of the second conductivity type, The plurality of trench gates in the active region penetrate the emitter layer, the base layer, and the carrier storage layer. The side walls of the plurality of trench gates in the active region are in contact with the emitter layer, the base layer, and the carrier storage layer. The bottom of each of the end portions of the plurality of trench gates in the wiring region is covered by the well layer.

6. The semiconductor device according to claim 1 or 2, wherein: The plurality of transistors include a plurality of insulated gate bipolar transistors.

7. The semiconductor device according to claim 1 or 2, In the wiring region, surfaces of the plurality of trench gates except the gate contact portion are covered with an interlayer insulating film, The gate contact portion is located at an opening provided in the interlayer insulating film, The opening has a shape that becomes narrower toward the gate contact portion in cross-sectional view.

8. The semiconductor device according to claim 7, wherein: In the active region and the wiring region, trench widths of the plurality of trench gates are equal to and constant.

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