Hybrid CMOS-compatible electro-optical devices

Abstract

A hybrid photonic chip comprising a plurality of semiconductor materials arranged to define a chip providing functionality, wherein at least a first portion of the chip is formed of a material that can be manufactured using CMOS technology; and at least a second portion of the chip comprises a nonlinear crystal material and is not etched; wherein the second portion of the chip combined with the first portion of the chip is configured as a low-loss single-mode waveguide that supports propagation.

Description

Technical Field

[0001] The present invention relates to an electro-optical device, and in particular but not limited to a hybrid strip-loaded electro-optical modulator. Background Art

[0002] Silicon photonics has significant advantages that make it an ideal choice for optical modulators, especially those used for short distances. These advantages include mature manufacturing processes, the ability to exploit the advantages of CMOS processing, inexpensive low-cost mass manufacturing, and electro-optical tunability achieved through carrier injection / depletion effects. Silicon photonic waveguides are sub-micron-scale and have high refractive index contrast, which allows sharp bends and compact structures with a small footprint. However, for modulation, silicon photonics also has some disadvantages, such as slow speed (due to the speed of PN junctions / carrier depletion) and some electrical nonlinearities (which reduce the spurious-free dynamic range, among other disadvantages).

[0003] Some materials are better than others for different applications.

[0004] For example, nonlinear crystalline materials such as lithium niobate (LiNbO3) (sometimes referred to as χ 2 Materials) are of great interest in designing modulators, especially for long-distance optical communications. They have the advantages of low insertion loss, low propagation loss and high-speed modulation. However, the traditional methods of defining waveguides are titanium diffusion and proton exchange, and these methods result in low refractive index changes. As a result, single-mode waveguides are on the order of 5 microns and the bending losses are extremely high. This means that the footprint of a device such as lithium niobate is large. Moreover, the placement of the electrodes must be well separated because the tails of the modes are long, resulting in reduced modulation efficiency. These factors impose "practical" limits on the modulation speed that are far lower than the "theoretical" limits.

[0005] There are several problems with using lithium niobate in CMOS manufacturing processes.

[0006] In general, lithium niobate is not compatible with standard CMOS manufacturing. One problem is contamination due to etching byproducts of lithium niobate. In addition, lithium niobate is difficult to etch anisotropically and produces rough sidewalls, which leads to higher propagation losses. Lithium niobate has been used to form ridge waveguides, however etching of the smooth sidewalls of lithium niobate is a continuing problem. State-of-the-art etching techniques produce highly sloped sidewalls (~45 degrees), and this can negatively affect the mode distribution. Some proposals have been made to overcome some of the problems of using lithium niobate, but none of them have produced an optimal or practical solution.

[0007] The known prior art has many problems, including:

[0008] Problems associated with etching of non-CMOS compatible materials,

[0009] ·With the main presence in χ 2 Problems associated with the propagation patterns of light outside the material, and / or

[0010] • Problems associated with appropriate methods for modulating the device.

[0011] As a result, existing technologies are either not implementable in standard silicon photonics manufacturing processes or are 2 The high optical power outside the area cannot obtain sufficient efficiency.

[0012] The present invention seeks to address at least some or all of these problems.

[0013] One possible improvement for designing and manufacturing modulators is to combine silicon photonics with lithium niobate structures. As is clear from the above, this is not straightforward. The present invention seeks to find solutions to at least some of these problems.

[0014] It is an object of the present invention to combine silicon and lithium niobate to form photonic devices.

[0015] Another goal is to improve the process of bonding silicon and lithium niobate.

[0016] A further object is to produce an improved modulator.

[0017] The embodiments described below are not limited to implementations that solve any or all disadvantages of the prior art. Summary of the invention

[0018] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0019] According to one aspect of the present invention, a hybrid photonic chip is provided, which includes a plurality of semiconductor materials arranged to define a chip that provides functions, wherein at least a first portion of the chip is formed of a material that can be manufactured using CMOS technology; and at least a second portion of the chip is not easily manufactured during CMOS technology; wherein the second portion of the chip combined with the first portion is configured as a low-loss single-mode waveguide that supports propagation.

[0020] Preferably, at least the second portion of the chip comprises a nonlinear crystalline material (χ 2 material or any other electro-optical material).

[0021] Preferably, the nonlinear crystal material may be χ2 material or any other electro-optical material, such as lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium niobate (KNbO3), barium titanate (BaTiO3), potassium titanyl phosphate (KTiOPO4), barium borate (BaB2O4).

[0022] Preferably, the first portion of the chip comprises one or more silicon strips on a silicon-on-insulator SOI platform that do not alone support single mode propagation.

[0023] Preferably, the second portion of the chip and the one or more silicon strips together support single mode propagation.

[0024] Preferably, the hybrid chip is a modulator.

[0025] Preferably, the second portion of the chip is a waveguide configured to substantially support said single mode propagation predominantly in the nonlinear crystalline material.

[0026] Preferably, the modulator is a Mach Zehnder modulator.

[0027] Preferably, the first portion of the chip comprises electrodes.

[0028] Preferably, the electrodes are located in gaps in the buried oxide of the first portion of the chip to accommodate bonding sites from the second portion of the chip.

[0029] Preferably, the second part of the chip is applied to the first part of the chip by means of a flip chip bonding technique.

[0030] Preferably, the electrode is connected to the second part of the chip during a flip chip bonding technique.

[0031] Preferably, a hybrid photonic chip is provided, comprising at least a first portion of a chip and at least a second portion of a chip, wherein the at least first portion comprises silicon and an electrode, and the at least second portion comprises a nonlinear crystal material, wherein the second portion of the chip is not subjected to etching, and wherein the second portion of the chip combined with the first portion of the chip is configured to support single-mode propagation.

[0032] According to a second aspect of the present invention, a method for manufacturing a hybrid photonic chip is provided, which excludes the etching of nonlinear crystal materials, and the method comprises: forming a first part of the chip from semiconductor material on a silicon-on-insulator (SOI) platform using a CMOS manufacturing process; applying a second part of the chip that has not undergone a CMOS processing step to the first part of the chip; the second part of the chip is made of a material configured to substantially support a single propagation mode of the chip.

[0033] Preferably, one or more silicon strips that do not alone support single mode propagation are formed on the SOI platform.

[0034] Preferably, a hybrid chip is formed as a modulator.

[0035] Preferably, the second portion of the chip is formed as a waveguide configured to support substantially single mode propagation.

[0036] Preferably, the modulator is formed as a Mach Zehnder modulator.

[0037] Preferably, the electrode is formed as part of the first part of the chip.

[0038] Preferably, gaps are etched into a buried oxide layer of the SOI platform; and electrodes are formed in the gaps in the buried oxide of a first portion of the chip to accommodate bonding sites from a second portion of the chip.

[0039] Preferably, the second part of the chip is applied to the first part of the chip in a flip chip bonding technique.

[0040] Preferably, the electrode is connected to the second part of the chip during a flip chip bonding technique.

[0041] Preferably, a method for manufacturing a hybrid photonic chip is provided, the method not including etching of nonlinear crystal material, the method comprising: forming a first portion of a chip from silicon using a CMOS manufacturing process; forming an electrode as part of the first portion of the chip; and applying a second portion of the chip including nonlinear crystal material to the first portion of the chip without undergoing a CMOS processing step, wherein the second portion of the chip combined with the first portion of the chip substantially supports single-mode propagation.

[0042] According to a third aspect of the present invention, there is provided a process design kit for forming a photonic integrated chip, which, when processed in a chip manufacturing system, enables the chip manufacturing system to form the photonic integrated chip of another aspect.

[0043] Preferably, a process design kit for forming a hybrid photonic chip disclosed herein is provided, comprising: parameters for forming a first portion of a chip comprising silicon and electrodes using a CMOS manufacturing process; parameters for forming a second portion of the chip comprising a nonlinear crystal material; and parameters for integrating the first portion and the second portion of the chip without performing a CMOS processing step, wherein the process design kit is configured to integrate the first portion of the chip with the second portion of the chip to support single-mode propagation.

[0044] Preferably, the kit includes optimizing the geometry of the hybrid photonic chip.

[0045] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium having stored thereon a computer-readable description of a chip, which, when processed in a chip manufacturing system, enables the chip manufacturing system to manufacture a photonic integrated chip of another embodiment.

[0046] Preferably, there is provided a computer-readable storage medium having stored thereon a computer-readable description of a hybrid photonic chip, which, when the chip is processed in a chip manufacturing system, causes the chip manufacturing system to perform the methods disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Embodiments of the present invention will be described by way of example with reference to the following drawings, in which:

[0048] Figure 1a and Figure 1b Shown is a representation of the electric field strength in two different material combinations according to an embodiment of the present invention.

[0049] Figure 2a and Figure 2b Schematic cross-sectional views of two possible modulators according to embodiments of the present invention are shown.

[0050] Figure 3 A schematic diagram of a device showing a full modulator according to an embodiment of the present invention is shown.

[0051] Figure 4 1 is a diagram showing another device according to an embodiment of the present invention. In this diagram, the electrodes are 2 Below the material.

[0052] Figure 5 a to Figure 5 f is a diagram showing a manufacturing process of a device according to an embodiment of the present invention.

[0053] Figure 6 a to Figure 6 e shows the Figure 4 Device fabrication steps.

[0054] Figure 7 a to Figure 7 d is a set of graphs showing some of the performance parameters of devices according to embodiments of the present invention.

[0055] Figure 8 This is the optical mode distribution of the double nanoribbon loaded lithium niobate waveguide as shown in the previous figure.

[0056] Common reference numerals are used throughout the drawings to indicate similar features. DETAILED DESCRIPTION

[0057] Embodiments of the present invention are described below by way of example only. These embodiments represent the best way currently known to the applicant to put the present invention into practice, although they are not the only way to achieve this goal. This description sets forth the functions of the examples and the order of steps for constructing and operating the examples. However, the same or equivalent functions and orders may be implemented by different examples.

[0058] The present invention relates to combining a silicon photonics platform with lithium niobate by optimizing the strength of each platform and mitigating the weaknesses of both. To achieve this, the present invention relates to a process such as flip-chip bonding, for example, to bond lithium niobate to an insulator of a CMOS fabricated device such as a waveguide. As will be appreciated by those skilled in the art, CMOS devices can be made of materials including silicon, silicon nitride, and many others. The process requires careful engineering that allows the waveguide mode to reside primarily in the lithium niobate region (or x-ray diffraction patterns). 2 material region) rather than in the waveguide region (or silicon region) of CMOS fabrication. This is important because 2 The material is electro-optically active, while silicon is not. Any overlap of the waveguide mode into the non-electro-optically active region will reduce the efficiency of the modulator. This is illustrated in Figure 1, where by careful design a high proportion of the power resides in the lithium niobate rather than in the silicon. The lithium niobate layer is Figure 1a and Figure 1b are marked 10 and 12.

[0059] Reference Figure 2a , the device is shown generally at 100. Device 100 is a modulator. The modulator includes a buried oxide layer 102 and a silicon waveguide 104, which in this example is referred to as a rib-type silicon waveguide with two ribs 106 and 108. An additional silicon dioxide layer 110 is located on the waveguide. Lithium niobate 112 is connected to the ribs of the waveguides 106 and 108 and the silicon dioxide layer 110. The silicon dioxide layer 114 is located above the lithium niobate, and electrodes 116 and 118 are located at the top of the device. This device is referred to herein as a hybrid silicon x 2 modulator. Lithium niobate is 2 Material.

[0060] Two silicon ribbons or silicon ribs together with a thin lithium niobate layer can support a single mode of propagation in the optical spectrum. Each element alone cannot support a single mode of propagation. In the present invention, the power of the optical mode resides primarily in the electro-optically active region, not in the silicon ribbons or silicon ribs. The present invention describes the careful engineering required so that most of the optical mode is contained within the lithium niobate region. Importantly, no single element alone can support a single mode on its own. Otherwise, a large number of unsuitable modes will exist in the silicon ribbons, such as in other designs.

[0061] χ2 The material is x 2 Materials that are nonlinear. This means that these materials have a nonlinear polarization density response to an electric field. As a result, these materials exhibit an electro-optic effect, where the refractive index changes due to the presence of an applied electric field. These materials are sometimes referred to as nonlinear crystalline materials, and include, for example: lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium niobate (KNbO3), barium titanate (BaTiO3), potassium titanyl phosphate (KtiOPO4), barium borate (BaB2O4), etc.

[0062] An example of an electro-optic effect is the Pockels effect, where the refractive index varies linearly with an applied electric field.

[0063] As discussed, lithium niobate is a difficult material to process (especially etch) and is not compatible with standard CMOS manufacturing. Therefore, the present invention does not include any processing of the lithium niobate layer, as will be described in more detail below. As a result, this allows integration with standard CMOS manufacturing and provides one of the advantages of the present invention.

[0064] Now back to Figure 2b , which shows a second type of modulator 120, sometimes referred to as a ridge modulator. This device includes a buried oxide layer 122 in which waveguides 124 and 126 are formed. Lithium niobate 128 is positioned and in contact with the waveguides. A silicon dioxide layer 130 is located above the lithium niobate, and electrodes 132 and 134 are located at the top of the device. This device is another hybrid silicon x 2 Modulator.

[0065] Figure 2a and Figure 2b These are presented only as examples, and other similar devices can be envisioned. Other types of hybrid silicon χ 2 Devices can be designed and manufactured as described herein. In addition, the process can be used for any hybrid chip made of materials in which at least one material is compatible with CMOS and at least one material is incompatible with CMOS. Thus, the resulting device can include CMOS compatible elements or layers and CMOS incompatible elements or layers.

[0066] Figure 3 Another device 200 having similar advantages is shown. The device 200 is a Mach-Zehnder push-pull configuration modulator with two phase shifters. The device includes a buried oxide layer 202 with a waveguide 204 located above the buried oxide layer 202. The waveguide includes an input 206 and an output 208 and two parallel arms or paths 210, 212 connected between the input and output. Lithium niobate 214 is located above the waveguide and the buried oxide layer. A silicon dioxide layer 216 and an electrode 218 are then applied.

[0067] Figure 4 is yet another device 300 in which electrodes are incorporated into the device and applied by different mechanisms, as will be described below. Figure 6 As described in Figure 4 In the embodiment of the present invention, the waveguide is positioned below the lithium niobate layer. The device 300 includes a substrate layer 302, which may be silicon dioxide or silicon, on which a further buried oxide 304 is patterned to leave a space 306 which may then accommodate an electrode 308. The structure may then include any suitable device, such as Figure 2a , Figure 2b and Figure 3 As shown. Figure 4 In this device, the Figure 2b , and includes a buried oxide layer 304 in which waveguides 124 and 126 are formed. Lithium niobate 128 is positioned in contact with the waveguides. An additional silicon dioxide layer 310 is located above the lithium niobate.

[0068] Now refer to Figure 5 Description for manufacturing Figure 2b In the first step, as Figure 5 As shown in FIG. 1 , a silicon on insulator (SOI) wafer is obtained. The SOI wafer 400 includes a silicon layer 402, a buried oxide layer 404, and a thinner silicon layer 406. Figure 5 In b, silicon waveguide 408 is photolithographically defined and additional silicon dioxide 410 is deposited. Figure 5 In c, the deposited silicon dioxide is subsequently planarized. Figure 5 d, the lithium niobate on insulator chip 412 is a wafer or flip chip bonded to a substrate. The chip includes a lithium niobate layer 414, a silicon dioxide layer 416 and a substrate 418. Figure 5 As shown in FIG. 4 , the lithium niobate chip 412 is ground down as close to the top silicon dioxide layer as possible. Any remaining silicon can be etched down until the top of the silicon dioxide layer is exposed. Figure 5 In f, electrode 420 is deposited and patterned.

[0069] As reference Figure 6 As mentioned, the bonding process may also include electrodes, wherein the electrodes are positioned at locations suitable for wire bonding.

[0070] In the first step, if Figure 6 As shown in FIG. 1 , a silicon on insulator (SOI) wafer is obtained. The SOI wafer 500 includes a silicon layer 502, a buried oxide layer 504, and a thinner silicon layer 506. Figure 6In b, silicon waveguide 508 is photolithographically defined and silicon dioxide 510 is deposited. Figure 6 In c, the deposited silicon dioxide is subsequently planarized. Figure 6 In d, two gaps 512 are etched into the silicon dioxide. A mask is used to deposit electrodes 514 within the resulting gaps. Figure 6 In FIG. 5 , the lithium niobate on insulator chip 516 is a flip chip bonded to a substrate. The chip includes a lithium niobate layer 518, a buried oxide layer 520, and a silicon substrate 522. In addition, the chip includes bonding points 524, which are intended to allow under-bump metallization to connect the chip to the electrode 514. Figure 6 f shows the final position of the lithium niobate chip connected to the electrode 514. Further processing may then be performed, such as grinding and etching to remove silicon if required, or any other suitable processing for the desired device.

[0071] These devices offer many advantages. As examples, these advantages include: higher modulation speeds than silicon photonics platforms can be achieved; modes are confined to x 2 region, thereby allowing for higher modulation efficiency; there is no processing (etching) of lithium niobate; and the process is CMOS compatible. The process can be applied to other hybrid chips, where one part of the hybrid chip is made by a CMOS manufacturing process and another part is flip-chipped onto the CMOS part. A hybrid chip is a hybrid chip that has CMOS compatible components and CMOS incompatible components. As an example, CMOS incompatible materials include x 2 Material.

[0072] In silicon photonics, the coplanar waveguide (CPW) is loaded with a PN junction. This can significantly reduce the -3dB bandwidth (and therefore the modulation speed). The traveling wave CPW on lithium niobate will be significantly faster than the traveling wave CPW of silicon photonics because it is just CPW without a loaded PN junction. The Pockels effect or linear electro-optic effect present in lithium niobate is also a field effect, and therefore significantly faster than the carrier depletion effect of silicon photonics. Using the above structure, Figure 7 The graph of FIG. 1 shows some finite element method (FEM) based simulations showing an S21 -3dB point above 60GHz. In general, the electro-optical -3dB response is close to the electrical -6dB point, which exceeds 100GHz, as shown in FIG. Figure 7 As shown in b. Figure 7 a shows that the S11 reflection can be well controlled and is less than -20dB. Figure 7 c shows that the effective refractive index of the microwave mode can be matched with that of the hybrid waveguide. Figure 7d shows that the port impedance can also be matched to 50 ohms at the same time.

[0073] As mentioned above, this model is restricted to the nonlinear χ 2 region. By designing the silicon waveguide, we can distribute most of the modes into the lithium niobate. This is important because a typical loaded waveguide has most of its modes only in the additional loading section. The design was aided by optimizing the number, geometry, and spacing of the silicon nanoribbons. Figure 2b In this configuration with two silicon strips 124 and 126, each individual cannot support a single mode. However, because they are placed in an optimized geometry, they can support a non-radiative single mode that is primarily in the nonlinear region (i.e., lithium niobate) in contrast to silicon. As a result, the optical mode resides in the lithium niobate layer 804 instead of in the silicon strips 800, 802. This is Figure 8 is shown graphically in .

[0074] Since there is no need to etch the nonlinear χ 2 material, thus achieving additional advantages. Etching lithium niobate is a difficult step in any case, even more so if it is added to standard CMOS processing because etching byproducts may contaminate the chamber. This is particularly problematic for the Inductively Coupled Plasma Reactive-ion etching (ICP / RIE) process. Since there are no processing steps involving lithium niobate, the CMOS processing lines are not exposed to any additional contaminants. In addition, lithium niobate is a difficult material to etch and typically produces a lot of sidewall roughness as well as shallow sidewall angles. Avoiding any processing of lithium niobate helps reduce any roughness-induced propagation losses.

[0075] The device produces high electric field strength (compared to conventional diffused lithium niobate modulators). Due to the favorable geometry of the structure and the smaller size of the optical mode, the electrodes can be placed closer together. For example, the electrode spacing can be as low as 5 μm without causing significant metal absorption losses. For example, electric field simulations show that for an application of 1 W on the port, for a gap of 11 μm, the normalized electric field on the active area is averaged to, for example, 598,800 V / m. For each volt of voltage applied, the normalized electric field is 85,542 V / m. The coplanar waveguide design can be modified to accommodate closer electrode spacing. This gives the additional advantage of a smaller device footprint.

[0076] Devices according to the present invention require relatively lower drive voltages compared to conventional lithium niobate designs.

[0077] The above embodiments and advantages are exemplary. There are many variations that can be implemented and still form part of the scope of the present invention. The following modifications are some examples in this regard.

[0078] The SOI substrate can be replaced by any type of substrate in which a waveguide can be defined, such as SiN, SiO2 on polymer, etc. The nonlinear optical material can be any nonlinear material, such as lithium niobate, electro-optic polymer, lithium tantalate, other x-ray diffraction patterns, etc. 2 Materials and other electro-optical materials. The method of strip-loading nonlinear thin films can be replaced by any other waveguide manufacturing technology. The traveling wave electrode can be defined before or after the flip chip bonding process, and the silicon waveguide can be part of the electrode design. The electrode can also be recessed into the top silicon by etching. By placing the electrode closer to the waveguide, the required drive voltage can be reduced.

[0079] The present invention may include various variations and alternatives of the above examples, which are intended to be included within the scope of the present invention.

[0080] Example embodiments include the following.

[0081] A hybrid photonic chip includes multiple semiconductor materials arranged to define a chip that provides functionality, wherein at least a first portion of the chip is formed of a material that can be manufactured using CMOS technology; and at least a second portion of the chip is not easily manufactured during CMOS technology; wherein the second portion of the chip combined with the first portion is configured as a low-loss single-mode waveguide that supports propagation.

[0082] Preferably, at least the second portion of the chip comprises a nonlinear crystalline material (χ 2 material or any other electro-optical material).

[0083] Preferably, the nonlinear crystal material (χ 2 Materials and any other electro-optical materials) include at least one of the following materials: lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium niobate (KNbO3), barium titanate (BaTiO3), potassium titanyl phosphate (KTiOPO4), barium borate (BaB2O4).

[0084] Preferably, the first portion of the chip comprises one or more silicon strips on a silicon-on-insulator SOI platform that do not alone support single mode propagation.

[0085] Preferably, the second portion of the chip and the one or more silicon strips together support single mode propagation.

[0086] Preferably, the hybrid chip is a modulator.

[0087] Preferably, the second portion of the chip is a waveguide configured to substantially support an optical mode predominantly in the nonlinear crystalline material.

[0088] Preferably, the modulator is a Mach-Zehnder modulator.

[0089] Preferably, the first portion of the chip comprises electrodes.

[0090] Preferably, the electrodes are located in gaps in the buried oxide of the first portion of the chip to accommodate bonding sites from the second portion of the chip.

[0091] Preferably, the second part of the chip is applied to the first part of the chip by means of a flip chip bonding technique.

[0092] Preferably, the electrode is connected to the second part of the chip during a flip chip bonding technique.

[0093] A hybrid photonic chip comprises at least a first portion of the chip and at least a second portion of the chip, the at least first portion comprising silicon and an electrode, the at least second portion comprising a nonlinear crystalline material, wherein the second portion of the chip is not subjected to etching, wherein the second portion of the chip combined with the first portion of the chip is configured to support single-mode propagation.

[0094] A method for manufacturing a hybrid photonic chip, the method not including etching of nonlinear crystalline material, the method comprising: forming a first portion of the chip from semiconductor material on a silicon-on-insulator (SOI) platform using a CMOS manufacturing process; applying a second portion of the chip that has not undergone a CMOS processing step to the first portion of the chip; the second portion of the chip being made of a material configured to substantially support single-mode propagation of the chip.

[0095] Preferably, one or more silicon strips that do not alone support single mode propagation are formed on the SOI platform.

[0096] Preferably, a hybrid chip is formed as a modulator.

[0097] Preferably, the second portion of the chip is formed as a waveguide configured to support substantially single mode propagation.

[0098] Preferably, the modulator is formed as a Mach-Zehnder modulator.

[0099] Preferably, the electrode is formed as part of the first part of the chip.

[0100] Preferably, gaps are etched into a buried oxide layer of the SOI platform; and electrodes are formed in the gaps in the buried oxide of a first portion of the chip to accommodate bonding sites from a second portion of the chip.

[0101] Preferably, the second part of the chip is applied to the first part of the chip in a flip chip bonding technique.

[0102] Preferably, the electrode is connected to the second part of the chip during a flip chip bonding technique.

[0103] A method for manufacturing a hybrid photonic chip, the method not including etching of nonlinear crystalline material, the method comprising: forming a first portion of a chip from silicon using a CMOS manufacturing process; forming an electrode as part of the first portion of the chip; and applying a second portion of the chip including nonlinear crystalline material to the first portion of the chip without undergoing a CMOS processing step, wherein the second portion of the chip combined with the first portion of the chip substantially supports single-mode propagation.

[0104] A process design kit for forming a photonic integrated chip. When the chip is processed in a chip manufacturing system, the process design kit enables the chip manufacturing system to form the photonic integrated chip in any embodiment.

[0105] A process design kit for forming a hybrid photonic chip disclosed herein comprises: parameters for forming a first portion of a chip including silicon and electrodes using a CMOS manufacturing process; parameters for forming a second portion of the chip including a nonlinear crystalline material; and parameters for integrating the first portion and the second portion of the chip without performing a CMOS processing step, wherein the process design kit is configured to integrate the first portion of the chip with the second portion of the chip to support single-mode propagation.

[0106] Preferably, the kit includes optimizing the geometry of the hybrid photonic chip.

[0107] A process design kit for forming a hybrid photonic chip disclosed herein, comprising: parameters for forming a first portion of the chip including silicon and electrodes using a CMOS manufacturing process; parameters for forming a second portion of the chip including a nonlinear crystal material; and parameters for integrating the first portion and the second portion of the chip without performing a CMOS processing step; wherein the process design kit is configured to integrate the first portion of the chip with the second portion of the chip to support single-mode propagation.

[0108] A computer-readable storage medium having stored thereon a computer-readable description of a hybrid photonic chip, which, when the chip is processed in the chip manufacturing system, causes the chip manufacturing system to perform the methods disclosed herein.

[0109] It will be apparent to those skilled in the art that any range or device value given herein may be expanded or altered without losing the effect sought.

[0110] It should be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the problems described, or those that have any or all of the benefits and advantages described.

[0111] Any reference to "an" item refers to one or more of those items. The term "comprising" is used herein to mean including the identified method blocks or elements, but these blocks or elements do not comprise an exclusive list and the method or apparatus may contain additional blocks or elements.

[0112] As used herein, the terms computer program code and computer readable instructions refer to any kind of executable code for a processor, including code expressed in a machine language, an interpreted language, or a scripting language. Executable code includes binary code, machine code, byte code, code defining an integrated circuit (such as a hardware description language or a netlist), and code expressed in a programming language code (such as C, Java, or OpenCL). For example, executable code can be any kind of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, executed at a virtual machine or other software environment, causes a processor of a computer system supporting the executable code to perform the tasks specified by the code.

[0113] It is also intended to encompass software that defines the configuration of hardware as described herein, such as HDL (hardware description language) software for designing integrated circuits or for configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided having encoded thereon computer-readable program code in the form of an integrated circuit defining data set that, when processed in a process design kit, configures a system to manufacture some or all of the devices herein.

[0114] The steps of the methods described herein may be performed in any suitable order, or may be performed simultaneously where appropriate. In addition, individual blocks may be deleted from any method without departing from the spirit and scope of the subject matter described herein. Aspects of any of the above examples may be combined with aspects of any of the other examples described to form additional examples without losing the effects sought.

[0115] A method of manufacturing at a process design kit as described herein may be provided. In addition, a process design kit data set may be provided which, when processed in a chip manufacturing system, leads to a method of manufacturing a PIC and / or an asymmetric alignment arrangement as described herein.

[0116] It should be understood that the above description of the preferred embodiments is given as an example only and various modifications may be made by those skilled in the art. Although various embodiments have been described above with a certain degree of particularity or with reference to one or more separate embodiments, those skilled in the art may make various changes to the disclosed embodiments without departing from the spirit or scope of the invention.

Claims

1. A hybrid photonic chip, comprising: at least a first portion of the chip, the first portion comprising silicon and an electrode; and at least a second portion of the chip, the second portion comprising a nonlinear crystalline material, wherein the second portion of the chip is not subjected to etching; wherein said at least first portion and said at least second portion have been applied to each other by a flip chip bonding technique, wherein the second portion of the chip combined with the first portion of the chip is configured to support single-mode propagation, Therein, the first portion of the chip includes one or more silicon strips on a silicon-on-insulator (SOI) platform that do not solely support the single-mode propagation.

2. The hybrid photonic chip according to claim 1, wherein: The nonlinear crystal material includes at least one of the following materials: lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium niobate (KNbO3), barium titanate (BaTiO3), potassium titanyl phosphate (KTiOPO4), and barium borate (BaB2O4).

3. The hybrid photonic chip according to claim 1, wherein: The second portion of the chip and the one or more silicon ribbons together support the single mode propagation.

4. The hybrid photonic chip according to claim 1, wherein: The hybrid photonic chip is a modulator.

5. The hybrid photonic chip according to claim 4, wherein: A second portion of the chip is a waveguide configured to substantially support single mode propagation predominantly in the nonlinear crystal material.

6. The hybrid photonic chip according to claim 4, wherein: The modulator is a Mach-Zehnder modulator.

7. The hybrid photonic chip according to claim 1, wherein: The electrode is located in a gap in the buried oxide of the first portion of the chip to accommodate a bond site from the second portion of the chip.

8. The hybrid photonic chip according to claim 1, wherein: During the flip chip bonding technique, the electrode is connected to a second portion of the chip.

9. A method of manufacturing a hybrid photonic chip, the method not including etching of nonlinear crystal material, the method comprising: forming a first portion of a chip from silicon using a CMOS manufacturing process, wherein the first portion of the chip comprises a silicon-on-insulator (SOI) platform; forming an electrode as part of a first portion of the chip; and forming one or more silicon strips on the silicon-on-insulator platform that do not solely support single-mode propagation; and applying a second portion of the chip comprising a nonlinear crystal material onto the first portion of the chip by means of a flip chip bonding technique, wherein the nonlinear crystal material has not been subjected to etching; Wherein the second portion of the chip combined with the first portion of the chip substantially supports the single mode propagation.

10. The method according to claim 9, wherein: The nonlinear crystal material (χ 2 The material) includes at least one of the following materials: lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium niobate (KNbO3), barium titanate (BaTiO3), potassium titanyl phosphate (KTiOPO4), and barium borate (BaB2O4).

11. The method of claim 9, further comprising forming a hybrid photonic chip as a modulator.

12. The method of claim 11, further comprising forming a second portion of the chip as a waveguide configured to substantially support the single mode propagation.

13. The method of claim 12, further comprising forming the modulator as a Mach-Zehnder modulator.

14. The method according to claim 9 also includes etching a gap into a buried oxide layer of a silicon-on-insulator platform in a first portion of the chip; and forming an electrode located in the gap in the buried oxide of the first portion of the chip to receive a bonding point from a second portion of the chip.

15. The method according to claim 9, wherein: During the flip chip bonding technique, the electrode is connected to a second portion of the chip.

16. A process design kit for forming the hybrid photonic chip according to claim 1, comprising: parameters for forming a first portion of the chip including silicon and electrodes using a CMOS manufacturing process; parameters for forming a second portion of the chip comprising a nonlinear crystalline material; and parameters for integrating the first and second portions of the chip without requiring a CMOS processing step; The process design kit is configured to integrate the first portion of the chip with the second portion of the chip to support single-mode propagation.

17. A computer-readable storage medium having stored thereon a computer-readable description of a hybrid photonic chip, the computer-readable description causing the chip manufacturing system to perform the method according to claim 9 when the hybrid photonic chip is processed in the chip manufacturing system.

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