Electronic device and method of manufacturing the same

Abstract

The present invention provides a method for manufacturing an electronic device having a solar cell structure and a drive circuit. The method comprises the following steps: preparing a first wafer having the solar cell structure on an initial substrate and a second wafer having the drive circuit formed thereon, wherein each of the first and second wafers includes a plurality of independent diode circuits and a capacitor functional layered portion; bonding the solar cell structure, the diode circuits, the capacitor functional layered portion, and the drive circuit to form a bonded wafer; performing wiring; and dicing the bonded wafer. This method provides an electronic device that includes a drive circuit, a solar cell structure, and a capacitor functional portion on a single chip while reducing manufacturing costs, and such an electronic device.

Description

Technical Field

[0001] The present invention relates to an electronic device and a method for manufacturing the same. Background Art

[0002] Electronic devices such as sensors for the IoT (Internet of Things) require small, low-power chips that are also inexpensive. For stable operation in such electronic devices, it is ideal to install an external power supply and use this external power supply to drive various sensors. However, the wiring required is expensive, making it difficult to install inexpensive sensors. Therefore, for IoT sensors, it is necessary to implement a device that does not require wires as a driving power source.

[0003] Furthermore, electronic devices must be compact to achieve cost-effectiveness. To achieve this, the driver circuit and the power receiving element must be implemented on a single chip. While microwaves or optical fiber are both viable wireless power sources, microwaves exhibit significant output attenuation over distance, making them unsuitable for powering distributed IoT sensors.

[0004] Therefore, optical wireless power supply is suitable for IoT sensor applications.

[0005] The power receiving element for optical wireless power supply is a solar cell, but it is difficult to integrate the drive circuit and the power receiving element into a single chip. Instead, the drive circuit area can be pre-configured, and the power receiving (light receiving) solar cell element can be formed in a separate area.

[0006] However, Si (silicon) solar cells equipped with driver circuits have low power reception efficiency and require a large area. Furthermore, in addition to the driver circuit, a capacitor function for temporarily charging the charge is essential for stable operation, requiring an even larger area for the components.

[0007] As a result, it is difficult to manufacture an inexpensive element. In order to improve the efficiency of the power receiving element, a solar cell composed of a compound semiconductor may be epitaxially grown in the solar cell portion.

[0008] However, epitaxial growth of compound semiconductor solar cells on Si substrates creates a significant lattice mismatch with the Si substrate. Consequently, improving crystal quality and creating highly efficient power-receiving solar cells requires careful attention to the buffer layer used for epitaxial growth, which increases epitaxial growth costs.

[0009] Furthermore, since the epitaxial growth temperature is high and, for Si, the epitaxial growth is performed in an impurity atmosphere, the difficulty of process design due to substrate contamination increases.

[0010] As a result, component manufacturing costs remain expensive.

[0011] Prior art literature

[0012] Patent Literature

[0013] Patent Document 1: Japanese Patent Application Publication No. 2018-148074

[0014] Patent Document 2: Japanese Patent Application Laid-Open No. 2013-4632

[0015] Patent Document 3: Japanese Patent Application Laid-Open No. 2008-210886 Summary of the Invention

[0016] (1) Technical issues to be resolved

[0017] As a technology for providing additional components in electronic devices, there is a technology for bonding a functional layer to a substrate. Patent documents 1 to 3 are listed as technologies related to bonding a functional layer to a substrate. Patent document 1 describes a technology for bonding a functional layer to a substrate using BCB (benzocyclobutene). Patent document 2 discloses a technology for etching a sacrificial layer. Patent document 3 discloses a technology for flip-chip bonding (Japanese: フリップ bonding) on ​​a drive circuit substrate. However, Patent documents 1 to 3 do not disclose a technology related to a method for manufacturing an electronic device having a drive circuit, a solar cell structure, and a capacitor functional unit in one chip.

[0018] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing an electronic device and such an electronic device, which includes a driving circuit, a solar cell structure, and a capacitor function unit on a single chip while reducing manufacturing costs.

[0019] (2) Technical solution

[0020] In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing an electronic device, which manufactures an electronic device having a solar cell structure and a driving circuit, and the manufacturing method is characterized in that it includes the following steps: preparing a first wafer having a plurality of independent solar cell structures composed of compound semiconductors formed by epitaxial growth on an initial substrate and a second wafer having a plurality of independent driving circuits formed thereon, wherein a plurality of independent diode circuits and capacitor functional layered parts are provided on either the first wafer or the second wafer; joining the first wafer and the second wafer in a manner such that the plurality of solar cell structures overlap with the plurality of diode circuits, the plurality of capacitor functional layered parts, and the plurality of driving circuits respectively to form a joined wafer; performing wiring so that power can be supplied from the plurality of solar cell structures to the plurality of diode circuits, the plurality of capacitor functional layered parts, and the plurality of driving circuits respectively in the joined wafer; and cutting the joined wafer to manufacture an electronic device having the solar cell structure and a driving circuit.

[0021] By preparing a first wafer having multiple independent solar cell structures and a second wafer having multiple independent drive circuits formed thereon, wherein multiple independent diode circuits and capacitor function stacked portions are formed on either the first wafer or the second wafer, and the multiple solar cell structures are bonded together so that the multiple diode circuits, the multiple capacitor function stacked portions, and the multiple drive circuits overlap, the electronic device can have a very small surface area. Consequently, the manufacturing cost of the electronic device having both a solar cell structure and a drive circuit can be reduced.

[0022] Furthermore, it is preferable to use a thermosetting adhesive for the bonding.

[0023] By using a thermosetting adhesive for bonding, bonding can be performed at low temperatures. Furthermore, the physical properties of the solar cell structure and the driver circuit portion do not change during the heat treatment required for bonding, so the bonding process can be performed after the solar cell structure, diode circuit, capacitor functional layered portion, and driver circuit are formed.

[0024] Furthermore, it is preferable that the initial substrate be separated from the bonded wafer after the bonding is performed.

[0025] By separating the initial substrate from the bonded wafer in this manner, the initial substrate can be reused, thereby reducing costs.

[0026] In addition, in the manufacturing method of the electronic device of the present invention, the wiring is performed through the following steps: setting a pad electrode so that power can be supplied to the driving circuit in the second wafer before the bonding is performed; forming an electrode for the solar cell structure so that power can be taken out from the solar cell structure of the first wafer in at least any one case before and after the bonding is performed; and electrically connecting the pad electrode to the electrode for the solar cell structure after the bonding.

[0027] In the method for manufacturing an electronic device of the present invention, wiring can be performed specifically in this manner.

[0028] In addition, the present invention provides an electronic device having a solar cell structure on a substrate provided with a driving circuit, characterized in that a diode circuit and a capacitor functional stacking portion are arranged between the solar cell structure and the driving circuit, and are electrically connected by wiring so that power can be supplied from the solar cell structure to the diode circuit, the capacitor functional stacking portion and the driving circuit, and the solar cell structure and the diode circuit, the capacitor functional stacking portion or the driving circuit are electrically separated by a thermosetting adhesive except for the wiring.

[0029] Such an electronic device can have a very small device area and can suppress manufacturing costs.

[0030] (3) Beneficial effects

[0031] The electronic device manufacturing method and electronic device of the present invention have a solar cell structure, a diode circuit, and capacitor functions, and can reduce the area of ​​the electronic device including the driving circuit, thereby reducing the manufacturing cost of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 1 is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer on which a solar cell structure and a diode portion are formed.

[0033] Figure 2 1 is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer on which contact portions are further formed.

[0034] Figure 3 1 is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer on which a capacitor functional layered portion is further formed.

[0035] Figure 4It is a schematic diagram showing a mid-step of the process of manufacturing the electronic device of the present invention, and is a schematic diagram showing a first wafer on which contact electrodes are further formed.

[0036] Figure 5 It is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer on which an adhesive layer is further formed.

[0037] Figure 6 This is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer that has been etched for element separation.

[0038] Figure 7 This is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a first wafer that has been further etched for element separation.

[0039] Figure 8 This is a schematic diagram showing a mid-step of the process of manufacturing the electronic device of the present invention, and is a schematic diagram showing the bonding of the first wafer and the second wafer.

[0040] Figure 9 This is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing separation of the initial substrate from the bonded wafer.

[0041] Figure 10 This is a schematic diagram showing a mid-step of the process of producing the electronic device of the present invention, and is a schematic diagram showing a portion of the processing of the bonded wafer.

[0042] Figure 11 It is a schematic diagram showing a mid-step of the process of the electronic device of the present invention, and is a schematic diagram showing SiO2 coating of the bonded wafer.

[0043] Figure 12 It is a schematic diagram showing a mid-step of the process of manufacturing the electronic device of the present invention, and is a schematic diagram showing the formation of electrodes for bonding wafers.

[0044] Figure 13 It is a schematic diagram showing a mid-step of the process of manufacturing the electronic device of the present invention, and is a schematic diagram showing metal wiring in a bonded wafer. DETAILED DESCRIPTION

[0045] As mentioned above, IoT sensors and other electronic devices require compact, low-power chips that are also inexpensive. While it would be ideal to install an external power supply and use this power to drive various sensors, the high wiring costs make it difficult to install inexpensive sensors. Therefore, IoT sensors require a device that can operate without wires.

[0046] The inventors of the present invention have repeatedly conducted research and found that an electronic device having a solar cell structure and a driving circuit manufactured in the following manner can make the area of ​​the electronic device extremely small and can suppress the manufacturing cost, thereby completing the present invention. The above-mentioned method is: preparing a first wafer having a plurality of independent solar cell structures composed of compound semiconductors formed by epitaxial growth on an initial substrate and a second wafer having a plurality of independent driving circuits formed thereon, wherein a plurality of independent diode circuits and capacitor functional layered parts are provided on either the first wafer or the second wafer, and joining these wafers in a manner in which a plurality of solar cell structures and a plurality of diode circuits, a plurality of capacitor functional layered parts, and a plurality of driving circuits are respectively overlapped, and after wiring is performed so that power can be supplied from the plurality of solar cell structures to the plurality of diode circuits, the plurality of capacitor functional layered parts, and the plurality of driving circuits, cutting is performed.

[0047] The present invention is a method for manufacturing an electronic device having a solar cell structure and a drive circuit, comprising the following steps: (a) preparing a first wafer having a plurality of independent solar cell structures composed of a compound semiconductor formed by epitaxial growth on an initial substrate, and a second wafer having a plurality of independent drive circuits formed thereon, wherein each of the first wafer and the second wafer has a plurality of independent diode circuits and a capacitor function layered portion; (b) bonding the first wafer and the second wafer such that the plurality of solar cell structures overlap with the plurality of diode circuits, the plurality of capacitor function layered portions, and the plurality of drive circuits, thereby forming a bonded wafer; (c) wiring the bonded wafer so that power can be supplied from the plurality of solar cell structures to the plurality of diode circuits, the plurality of capacitor function layered portions, and the plurality of drive circuits; and (d) dicing the bonded wafer to thereby manufacture the electronic device having the solar cell structure and the drive circuit.

[0048] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0049] (Implementation Method)

[0050] First, a first wafer is prepared, which has multiple independent solar cell structures composed of compound semiconductors formed by epitaxial growth on an initial substrate. As mentioned above, it is sufficient to have multiple independent diode circuits and capacitor functional layered portions on either the first wafer or the second wafer. Here, the example of having these components on the first wafer is used.

[0051] Figure 1FIG. 1 shows an outline of a first wafer 100. In the first wafer 100, a plurality of solar cell structures are formed on an initial substrate 10 by epitaxial growth.

[0052] More specifically, a solar cell structure can be formed as follows. However, the solar cell structure can adopt various structures composed of compound semiconductors. First, a first wafer 100 is prepared. On the first wafer 100, a p-GaAs buffer layer (not shown) having a thickness of, for example, 0.5 μm, a p-AlAs sacrificial layer 11 having a thickness of, for example, 0.3 μm, a p-GaAs contact layer 12 serving as a first p-GaAs layer having a thickness of, for example, 0.3 μm, and a p-Indium layer having a thickness of, for example, 0.2 μm are formed. 0.5 Ga 0.5 The p-window layer 13, the p-GaAs emitter layer 14 as the second p-GaAs layer with a thickness of, for example, 0.5 μm, the n-GaAs base layer 15 as the first n-GaAs layer with a thickness of, for example, 3.5 μm, and the n-In layer 15 with a thickness of, for example, 0.05 μm. 0.5 Ga 0.5 The BSF (Back Surface Field) layer 16 composed of P has a solar cell structure. Figure 1 In the stage of solar cell, the components are not separated yet, so the solar cell structure is not independent. The structure, composition, thickness, etc. of each layer of the solar cell structure can be appropriately designed. For example, in this case, 0.5 Ga 0.5 P is not limited to the exemplified compositions as long as it is stacked under pseudo-lattice matching conditions and the film thickness is equal to or less than the critical film thickness.

[0053] exist Figure 1 On the BSF layer 16, an n-GaAs contact layer 31 having a thickness of 0.3 μm as a second n-GaAs layer and an n-GaAs contact layer having a thickness of 0.01 μm as a third n-GaAs layer are further formed. + A p-GaAs tunnel junction layer 32, a p-GaAs layer (p-type layer for diode) 33 having a thickness of, for example, 0.3 μm, serving as a third p-GaAs layer, and an n-GaAs layer (n-type layer for diode) 34 having a thickness of, for example, 0.3 μm, serving as a fourth n-GaAs layer. Thus, a first wafer 100 can be obtained in which a diode portion (diode circuit) 30 composed of these layers is formed on a solar cell structure. Thus, a PV-EPW (photovoltaic-electromotive force-epitaxial wafer) with a diode can be prepared. This diode portion (diode circuit) 30 prevents reverse current flow after the electronic device is manufactured.

[0054] Then, if Figure 2 As shown, it is possible to Figure 1Contact portion 40 is formed on first wafer 100, which has a diode portion (diode circuit) 30 formed on the solar cell structure shown. Contact portion 40 can be formed by forming, for example, a 0.1 μm thick AuSi layer 41, a 0.1 μm thick first Ti layer 42, and a 0.5 μm thick Al layer 43, thereby obtaining a contact portion composed of these layers.

[0055] In addition, if Figure 3 As shown, in the formation of such a contact portion Figure 2 A capacitor functional laminate 50 can be formed on the first wafer 100. The capacitor functional laminate 50 can be formed by forming a first Pt layer 51 having a thickness of, for example, 0.5 μm, a Ta layer 52 having a thickness of, for example, 0.5 μm, a TiBaO3 layer 53 having a thickness of, for example, 0.1 μm, a second Ti layer 54 having a thickness of, for example, 0.5 μm, and a second Pt layer 55 having a thickness of, for example, 0.5 μm, thereby obtaining a capacitor layer composed of these layers.

[0056] Then, if Figure 4 As shown, after the capacitor function stacking portion 50 is formed, Figure 3 On the first wafer 100, a first SiO2 film 61 can be formed. The first SiO2 film 61 can be formed into a thickness of, for example, 0.1 μm by P-CVD (Plasma Chemical Vapor Deposition). Figure 4 As shown, a portion of the first SiO2 film 61 can be opened to form a first contact electrode 62 made of Au. In addition, the first SiO2 film 61 is an adhesion-enhancing layer of the BCB film, and the first SiO2 film 61 is not necessarily required.

[0057] Then, if Figure 5 As shown, a BCB (benzocyclobutene) film 63 having a thickness of, for example, 0.2 μm is formed as a thermosetting adhesive on the first SiO2 film 61 by spin coating. As a thermosetting adhesive that can be used in the present invention, BCB (benzocyclobutene) resin is preferably used, but is not limited to this. After applying the BCB film 63, the solvent is preferably dispersed in advance by heat treatment at about 100°C. The thickness of the BCB film 63 is preferably not less than 0.05 μm, more preferably not less than 0.1 μm. A BCB film 63 of this thickness can achieve better wafer bonding. The thickness of the BCB film 63 is preferably not more than 2.0 μm, more preferably not more than 1.0 μm. If the thickness of the BCB film 63 is such, the increase in cost can be suppressed. In addition, if it is such a thickness, the deformation caused by the bonding pressure can be reduced, the amount of attachment of the separation pattern to the side will not increase, and the subsequent sacrificial layer etching and patterning (Japanese: パターンし) process can be easily performed.

[0058] Next, a resist pattern is formed on the BCB film 63 by a photoresist process. The resist pattern has an opening in the portion where the element separation for making the contact electrode 62 and the solar cell structure independent is to be performed (the element separation planned portion). An ICP (inductively coupled plasma) treatment is performed in a mixed plasma atmosphere of a fluorine-containing gas (NF3 or SF6, etc.) and an Ar gas to pattern the BCB film 63 and the SiO2 film 61 as well as the capacitor portion 50 and a portion of the contact portion 40 (the Al layer 43 and the first Ti layer 42) (refer to FIG. Figure 5 Here, as conditions for the ICP treatment, the atmosphere pressure can be 1.0 Pa and the total flow rate of NF3 and Ar gas can be 50 sccm. However, as long as the BCB film 63 and the SiO2 film 61 as well as a portion of the capacitor portion 50 and the contact portion 40 can be patterned, the conditions are not limited thereto.

[0059] Next, the AuSi layer 41 of the contact portion 40 can be opened by removing the AuSi layer 41 through wet treatment using a solution containing KI (see FIG. Figure 6 ).

[0060] After the AuSi layer 41 is opened, Figure 7 As shown, an ICP process is performed in an Ar gas mixed plasma atmosphere to form a bonding substrate (first wafer 100) in which the diode portion 30 and the solar cell structure (PV portion) are separated. Here, the ICP process can be performed under an atmosphere pressure of 1.0 Pa and a total flow rate of 50 sccm of Cl2 and Ar gas. However, the ICP process is not limited to these conditions as long as the diode portion 30 and the solar cell structure (PV portion) can be separated and patterned.

[0061] After the element separation patterning is performed in this way, the resist pattern is removed. The resist can be removed by ashing, but is not limited thereto. It can also be removed by organic cleaning or other degreasing treatment. In addition, the element separation is performed by ICP treatment, but is not limited to the ICP treatment method. A well-known method can be used. For example, the GaAs layer can be etched with a tartaric acid-hydrogen peroxide mixed solution, and the InGaP layer can be etched with a hydrochloric acid-phosphoric acid mixed solution to perform element separation. Figure 7 As shown, through the above steps, the first wafer 100 having a plurality of independent solar cell structures made of compound semiconductors and having a plurality of independent diode portions (diode circuits) 30 and capacitor function stacked portions 50 can be prepared.

[0062] Next, a driving circuit substrate 20 (see FIG. 1 ) having a driving circuit and a power receiving pad portion (a first pad electrode 22 and a second pad electrode 23) for input is prepared on a Si substrate. Figure 8 ) as the second wafer 200. Then, as Figure 8 As shown, a second SiO2 film 21 having a thickness of, for example, 0.1 μm is formed on the surface of the driving circuit substrate 20. The second SiO2 film 21 is an adhesion-enhancing layer for the BCB film and is not necessarily required.

[0063] Next, the driving circuit substrate 20 and the bonding substrate are aligned so that the first pad electrode 22 and the first contact electrode 62 are approximately at the same position, and the driving circuit substrate 20 and the bonding substrate are placed face to face and overlapped. A force of 250 N / cm is applied at a temperature of 300°C, for example. 2 The wafers 300 are bonded while maintaining a pressure of about 100 nm.

[0064] Here, the heat treatment condition of 300°C is shown as an example. However, the temperature condition required for BCB to solidify in a short time is only 300°C. Even if a low temperature condition is selected, solidification can be achieved by extending the holding time. Therefore, it is not limited to this temperature condition. In addition, although 250N / cm 2 The pressure is about , but it is just an example of the pressure that can reliably bond. If the bonding time is extended, bonding can be performed at a pressure lower than this pressure, so it is not limited to this pressure value.

[0065] After joining, Figure 9 As shown, the sacrificial layer 11 is etched. The sacrificial layer 11 is etched using a fluorine-containing solution. Figure 8 and Figure 9 As shown, since the element separation planned portion is opened, the fluorine-containing liquid quickly reaches the AlAs sacrificial layer 11 and etches the sacrificial layer 11 .

[0066] Because the fluorine-containing liquid has etching selectivity for layers other than sacrificial layer 11, only the AlAs sacrificial layer 11 is selectively removed. As sacrificial layer 11 disappears, the solar cell structure, diode portion (diode circuit) 30, and capacitor functional layered portion 50 remain on the driver circuit substrate side (second wafer 200 side), and the initial substrate 10 portion is separated from the bonded wafer 300.

[0067] The separated initial substrate 10 can be reused as an epitaxial growth substrate. The initial substrate 10 can also be used after its surface is polished again as needed.

[0068] Next, a pattern with a partial opening is formed on the bonded wafer 300 by photolithography, and the p-GaAs contact layer (first p-GaAs layer) 12 to the AuSi layer 41 are etched by the same ICP process as above. Next, the AuSi layer 41 in the non-etching portion is removed by KI solution (refer to FIG. Figure 10). After patterning is formed on the AuSi layer 41, the resist is removed.

[0069] Next, a pattern with a partially opened portion is formed by photolithography, and the capacitor function stack portion 50 in the non-resist-covered portion is removed by ICP processing to form a pattern in which the second Ti layer 54 portion remains (refer to FIG. Figure 10 After patterning is formed on the capacitor function stacked portion 50, the resist is removed.

[0070] Next, a pattern with a partially opened portion is formed by photolithography, and the second Ti layer 54 to the BCB film 63 in the non-etching portion are removed by ICP processing to form a pattern that partially exposes the second SiO2 layer 21 (see FIG. Figure 10 After forming a pattern in which a portion of the second SiO2 layer 21 is exposed on the second wafer 200 (driving substrate), the resist is removed. In addition, although the case of forming a pattern in which a portion of the second SiO2 layer 21 is exposed is illustrated, the portion of the second SiO2 layer 21 does not necessarily need to remain, and a pattern in which it is removed may also be used.

[0071] Next, the entire wafer is covered with a third SiO2 film 72 having a thickness of, for example, 0.1 μm (refer to Figure 11 ). Then, if Figure 11 As shown, a pattern is formed by photolithography to partially open the third SiO2 film 72, forming a pattern with openings on a portion of the contact layer (first p-GaAs layer) 12, a portion of the first Ti layer 42, a portion of the first Pt layer 51, a portion of the second Ti layer 54, and the second pad electrode 23. Then, etching is performed using a fluorine-containing solution to partially open the third SiO2 film 72. After partially opening the third SiO2 film 72, the resist is removed.

[0072] Then, if Figure 12 As shown, a second contact electrode 73 is formed in the SiO 2 opening to be in contact with the contact layer (first p-GaAs layer) 12 .

[0073] Here, the second contact electrode 73 is formed of, for example, 0.5 μm thick, Au containing Be, in contact with the contact layer (first p-GaAs layer) 12. Furthermore, any material can be selected without being limited to the above materials as long as it forms an ohmic contact.

[0074] Then, if Figure 13As shown, the second pad electrode 23, the opening in the first Pt layer 51, and the second contact electrode 73 are connected to form a metal wiring 77. An opening pattern is formed using photolithography, an Al layer is vapor-deposited to a thickness of, for example, 0.5 μm, and a wiring pattern is formed using lift-off. Furthermore, the opening in the second Ti layer 54 and the opening in the first Ti layer 42 are connected to form a metal wiring 78. An opening pattern is formed using photolithography, a 0.5 μm Al layer is vapor-deposited, and a wiring pattern is formed using lift-off.

[0075] In this way, a bonded wafer 300 is produced. A plurality of electronic device structures are formed on the bonded wafer 300. By dicing the bonded wafer 300, the electronic device structures can be separated, and electronic devices having a solar cell structure and a drive circuit can be manufactured.

[0076] Cutting Figure 13 The electronic device manufactured by bonding the wafer 300 shown can adopt the following structure. The electronic device is an electronic device having a solar cell structure on a substrate (driving circuit substrate 20) provided with a driving circuit, and a diode part (diode circuit) 30 and a capacitor function stacking part 50 are arranged between the solar cell structure and the driving circuit. In addition, electrical connection is made through wiring 77 and 78 so that power can be supplied from the solar cell structure to the diode circuit 30, the capacitor function stacking part 50 and the driving circuit. In addition, the solar cell structure and the diode circuit 30, the capacitor function stacking part 50 or the driving circuit are electrically separated by a thermosetting adhesive (BCB film 63) except for wiring 77 and 78. In the case of the above example, the solar cell structure and the driving circuit (driving circuit substrate 20), the capacitor function stacking part 50 and the driving circuit are bonded by a thermosetting adhesive (BCB film 63).

[0077] In a solar cell (PV), the power receiving power increases as the area increases, so a larger area is advantageous for driving power. In addition, as for the capacitance of a capacitor, the larger the area, the more charge that can be accumulated, so a larger area is advantageous. In the existing example, the solar cell structure, the capacitor function, and the drive circuit are arranged on the same surface, and the area of ​​the element is increased in order to increase the power receiving power. However, in the present invention, since the power receiving part and the capacitor function are arranged on the drive circuit part, the element surface can be minimized.

[0078] In addition, in particular, by using a thermosetting adhesive during bonding, the bonding temperature can be set to a relatively low temperature of 300°C. Therefore, the physical properties of the driver circuit portion will not change due to the heat treatment required for bonding, and the bonding process can be performed after the driver circuit is formed. Since the bonding temperature is a relatively low temperature of 300°C, the physical properties of the solar cell structure portion and the capacitor functional portion will not change due to the heat treatment required for bonding, and the bonding process can be performed after the electrodes of the solar cell structure portion are formed. Therefore, a functional substrate having the functions of the solar cell structure portion, the capacitor functional portion, and the driver circuit can be realized without compromising the properties of each material.

[0079] Furthermore, in the present invention, since the driving circuit substrate and the solar cell structure portion (and the capacitor functional portion) can be formed separately, optimal conditions can be selected when forming each functional portion, thereby contributing to an improvement in yield.

[0080] Furthermore, in the present invention, since the output electrodes of the solar cell structure and the input electrodes of the drive circuit are aligned and then bonded, it is possible to improve the accuracy of wiring formation and the yield associated with wiring formation.

[0081] Furthermore, in the present invention, the formation of the solar cell structure and the formation of the driving circuit are performed in separate steps, thereby preventing a decrease in yield due to defects occurring after lamination.

[0082] In addition, when an epitaxial layer of a solar cell structure is formed on a driving circuit portion, the material cost of forming a buffer layer accounts for a large proportion. However, by separating the substrate / process for forming the solar cell structure and the substrate / process for forming the driving circuit, each can be formed at the lowest cost and with the best design, thereby reducing the total cost.

[0083] Furthermore, the cost of the epitaxial layers in solar cell structures is relatively high, with the initial substrate cost accounting for a significant portion. Since the solar cell structure is bonded after the components are separated, epitaxial lift-off can be applied, allowing the reuse of the initial substrate after lift-off, thus reducing epitaxial costs.

[0084] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely illustrative, and any solution having substantially the same structure and producing the same effects as the technical concept described in the claims of the present invention is included within the technical scope of the present invention.

Claims

1. A method for manufacturing an electronic device comprising: manufacturing an electronic device having a solar cell structure and a drive circuit, characterized in that: Including the following processes: Preparing a first wafer having a plurality of independent solar cell structures composed of compound semiconductors formed by epitaxial growth on an initial substrate and a second wafer having a plurality of independent driving circuits formed thereon, wherein either the first wafer or the second wafer has a plurality of independent diode circuits and capacitor function stacked portions; Bonding the first wafer and the second wafer so that the plurality of solar cell structures overlap with the plurality of diode circuits, the plurality of capacitor function stacked portions, and the plurality of drive circuits to form a bonded wafer; performing wiring so that power can be supplied from the plurality of solar cell structures to the plurality of diode circuits, the plurality of capacitor function stacked portions, and the plurality of drive circuits in the bonded wafer; and The bonded wafer is cut to produce an electronic device having the solar cell structure and a driving circuit.

2. The method for manufacturing an electronic device according to claim 1, wherein: The bonding is performed using a thermosetting adhesive.

3. The method for manufacturing an electronic device according to claim 1, wherein: After the bonding is performed, the initial substrate is separated from the bonded wafer.

4. The method for manufacturing an electronic device according to claim 2, wherein: After the bonding is performed, the initial substrate is separated from the bonded wafer.

5. The method for manufacturing an electronic device according to any one of claims 1 to 4, characterized in that: Perform the wiring as follows: providing a pad electrode so that power can be supplied to the driving circuit in the second wafer before the bonding; forming an electrode for a solar cell structure so that power can be extracted from the solar cell structure of the first wafer at least in any one of before and after the bonding; and After the bonding, the pad electrode is electrically connected to the solar cell structure electrode.

6. An electronic device having a solar cell structure on a substrate provided with a driving circuit, characterized in that: A diode circuit and a capacitor function stacked portion are arranged between the solar cell structure and the drive circuit. The capacitor function stacked portion, the diode circuit, and the solar cell structure are stacked on the drive circuit in the vertical direction. The solar cell structure is electrically connected to the diode circuit, the capacitor function stacked portion, and the drive circuit via wiring so that power can be supplied thereto. The solar cell structure is electrically isolated from the diode circuit, the capacitor function layered portion, or the drive circuit by a thermosetting adhesive, excluding the wiring.

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