Multi-core system, multi-core system control method, multi-core device and storage medium

Abstract

The present application relates to a multi-core system, a control method for a multi-core system, a multi-core device and a storage medium. An embodiment of the present application includes: a main system unit controls a subsystem control unit to perform a power-on operation on the subsystem unit, controls the subsystem unit to perform a boot operation, and controls the subsystem unit to perform a locking operation on the subsystem control unit; the main system unit controls the subsystem unit to perform an unlocking operation on the subsystem control unit, controls the subsystem unit to perform a shutdown operation, and controls the subsystem control unit to perform a power-off operation on the subsystem unit. An embodiment of the present application can enable the subsystem control unit to continue to supply power to the subsystem unit after the main system is restarted or a power failure occurs, thereby avoiding abnormal power loss of the subsystem unit, and can also enable the subsystem unit to stop working when the subsystem unit is not needed to perform a function, thereby reducing the power consumption of the system.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the technical field of multi-core systems, and in particular to a multi-core system, a control method for a multi-core system, a multi-core device, and a storage medium. Background Art

[0002] With advancements in integrated circuit design and manufacturing processes, chip performance and integration are increasing, significantly increasing chip power consumption. To reduce chip power consumption, most current chips utilize a multi-core system architecture. Because each core in a multi-core system has distinct functions, the main system controls the operating status of subsystems, effectively reducing power consumption by halting non-functional subsystems during the execution of certain functions.

[0003] In current multi-core system design architectures, the main system usually powers the subsystems. If the main system restarts or fails, causing a power supply abnormality, the subsystem will stop working due to power loss, which will affect the chip's functional execution and may even cause the subsystem's business data to be lost. Summary of the Invention

[0004] The embodiments of the present application provide a multi-core system, a control method for a multi-core system, a multi-core device, and a storage medium, which can solve the problem of abnormal power loss of a subsystem caused by a main system restart or a power supply failure, and can effectively reduce the power consumption of the system while meeting performance requirements.

[0005] In a first aspect, an embodiment of the present application provides a multi-core system, including a main system unit, a subsystem unit, and a subsystem control unit; wherein,

[0006] The main system unit is used to generate control instructions, including power-on and power-off instructions, locking and unlocking instructions, and power-on and power-off instructions;

[0007] The subsystem unit is connected to the main system unit and the subsystem control unit and is used to:

[0008] In response to a power-on instruction, the power-on operation is performed; or, in response to a power-off instruction, the power-off operation is performed; or, in response to a locking instruction, the power-off operation is performed on the subsystem control unit; or, in response to an unlocking instruction, the power-off operation is performed on the subsystem control unit;

[0009] The subsystem control unit is connected to the main system unit and the subsystem unit respectively and is used to:

[0010] In response to the power-on instruction, a power-on operation is performed on the subsystem unit; or, in response to the power-off instruction, a power-off operation is performed on the subsystem unit.

[0011] In the second aspect, an embodiment of the present application provides a control method for a multi-core system, wherein the multi-core system includes a main system unit, a subsystem unit and a subsystem control unit. The main system unit is connected to the subsystem unit and the subsystem control unit respectively, and the subsystem unit is also connected to the subsystem control unit. The method includes a power-on step and a power-off step.

[0012] In a third aspect, an embodiment of the present application provides a multi-core device, which includes the multi-core system of some embodiments of the first aspect of the present application; or, the multi-core device includes a memory, a processor, and a program stored in the memory and runnable on the processor, and when the program is executed by the processor, it implements the control method of the multi-core system of some embodiments of the second aspect of the present application.

[0013] In a fourth aspect, an embodiment of the present application provides a readable storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement a control method for a multi-core system that executes some embodiments of the second aspect of the present application.

[0014] The embodiments of the present application include: the main system unit controls the subsystem control unit to perform a power-on operation on the subsystem unit, controls the subsystem unit to perform a boot operation, and controls the subsystem unit to perform a lock operation on the subsystem control unit; the main system unit controls the subsystem unit to perform an unlock operation on the subsystem control unit, controls the subsystem unit to perform a shutdown operation, and controls the subsystem control unit to perform a power-off operation on the subsystem unit. The embodiments of the present application enable the subsystem control unit to continue to supply power to the subsystem unit after the main system is restarted or a power supply failure occurs, thereby avoiding abnormal power loss of the subsystem unit. In addition, the subsystem unit can be stopped when the subsystem unit is no longer needed to perform its function, thereby reducing system power consumption.

[0015] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a structural block diagram of a multi-core system provided by an embodiment of the present application;

[0017] Figure 2 yes Figure 1 A structural block diagram of an embodiment of a neutron system control unit;

[0018] Figure 3 yes Figure 2 A structural block diagram of the first switch control module;

[0019] Figure 4 yes Figure 1 A structural block diagram of another embodiment of a neutron system control unit;

[0020] Figure 5 yes Figure 1 A structural block diagram of another embodiment of a neutron system control unit;

[0021] Figure 6 yes Figure 4 A structural block diagram of the second switch control module;

[0022] Figure 7 This is a flow chart of a method for controlling a multi-core system provided by an embodiment of the present application;

[0023] Figure 8 yes Figure 7 Flowchart of power-on steps;

[0024] Figure 9 yes Figure 7 A schematic diagram of a flow chart of an embodiment of power-on and power-off steps;

[0025] Figure 10 yes Figure 7 Flowchart of the steps for opening a business channel;

[0026] Figure 11 yes Figure 7 Flow chart of the business channel closing steps;

[0027] Figure 12 yes Figure 7 A flowchart of another embodiment of the power-on and power-off steps.

[0028] Reference numerals:

[0029] Multi-core system 100; main system unit 110; subsystem unit 120; subsystem control unit 130; power supply module 210; first switch control module 220; first logic OR gate circuit 310; first switch circuit 320; service module 410; second switch control module 420; second logic OR gate circuit 610; second switch circuit 620; step S0710; steps S0810-S0830; steps S0910-S0930; steps S1010-S1030; steps S1110-S1130; steps S1210-S1240. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. In the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other in any manner.

[0031] It should be noted that although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. The terms "first," "second," and the like in the specification, claims, and drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] The multi-core system of the embodiment of the present application includes a main system and multiple subsystems, and the main system connects multiple subsystems through an inter-core serial / parallel data communication bus (such as UART, SPI, I-wire, USB, SD IO, etc.) to provide a business main control logic. The subsystem performs business functions according to the control instructions of the main system. The subsystem and the main system are both integrated with a processor with programmable capabilities. The multi-core processor designed based on the multi-core system architecture can support multiple processors on the inter-core serial / parallel data communication bus, and multiple processors process different tasks in parallel. The current multi-core system design architecture is usually powered by the main system to the subsystem. If a power failure occurs in the main system, the subsystem will stop working due to power failure.

[0033] For example, wireless positioning terminal devices with high battery life requirements (such as positioning trackers for children, pets, assets, and other application scenarios that support NB-IoT / eMTC wireless cellular networks) and battery-powered IoT smart terminal devices (such as water / electricity / gas meters that support LPWA low-power wireless wide area network transmission, and smart door magnets, smart infrared sensors, smart smoke sensors, and other sensors that support wireless short-range communication such as Zigbee / Zwave / BLE for home use) generally consist of a communication module and a main processor. When the device is in a non-operating state (such as a static state), the communication module needs to be powered off to extend battery life. However, when the main processor's GPIO pin is used to control the communication module to power off, if the main processor abnormally resets and causes the GPIO pin level to flip, the communication module will be abnormally powered off.

[0034] Based on this, the embodiments of the present application provide a multi-core system, a control method for a multi-core system, a multi-core device and a storage medium, which can solve the problem of abnormal power loss of the subsystem caused by the restart of the main system or a power supply failure, and can effectively reduce the power consumption of the system while meeting performance requirements.

[0035] In the first aspect, the embodiment of the present application provides a multi-core system 100, referring to Figure 1 The multi-core system 100 includes a main system unit 110, a subsystem unit 120 and a subsystem control unit 130; wherein the main system unit 110 is used to generate control instructions, and the control instructions include power-on instructions and power-off instructions, locking instructions and unlocking instructions, power-on instructions and power-off instructions; the subsystem unit 120 is respectively connected to the main system unit 110 and the subsystem control unit 130, and is used to: respond to the power-on instruction to perform a power-on operation; or, respond to the power-off instruction to perform a shutdown operation; or, respond to the locking instruction to perform a locking operation on the subsystem control unit; or, respond to the unlocking instruction to perform an unlocking operation on the subsystem control unit; the subsystem control unit 130 is respectively connected to the main system unit and the subsystem unit, and is used to: respond to the power-on instruction to perform a power-on operation on the subsystem unit; or, respond to the power-off instruction to perform a power-off operation on the subsystem unit.

[0036] In some embodiments, the main system unit triggers a power-on or power-off operation by setting the power-on control pin of the subsystem unit. For example, the main system unit generates a power-on command, which is used to set the power-on control pin of the subsystem unit to a high level. The subsystem unit responds to the power-on command and performs a power-on operation; the main system unit generates a power-off command, which is used to set the power-on control pin of the subsystem unit to a low level. The subsystem unit responds to the power-off command and performs a power-off operation. In digital logic circuits, the high and low voltages are represented by logic levels. Logic levels include high and low levels. A high level refers to a high voltage relative to a low level. A low level represents 0, and a high level represents 1. For example, in a TTL gate circuit, a voltage greater than 3.5V is defined as a logic high level, represented by the number 1; a voltage less than 0.3V is defined as a logic low level, represented by the number 0. Generally, a low level is defined as 0 to 0.25V, and a high level is defined as 3.5 to 5V. The embodiment of the present application stipulates that the value of the high level is the power supply voltage of the main system unit to the subsystem unit, or close to the power supply voltage, and the value of the low level is 0V, or close to 0V. The value ranges of the high level and the low level can be customized according to the actual scenario.

[0037] In some embodiments, the main system unit triggers a power-on or power-off operation by setting a power control pin of a subsystem control unit. For example, the main system unit generates a power-on instruction, which is used to set the power control pin of the subsystem control unit to a high level. The subsystem control unit responds to the power-on instruction and performs a power-on operation on the subsystem unit; the main system unit generates a power-off instruction, which is used to set the power control pin of the subsystem control unit to a low level. The subsystem control unit responds to the power-off instruction and performs a power-off operation on the subsystem unit.

[0038] In some embodiments, the subsystem unit triggers a locking operation or an unlocking operation by setting a power-supply self-locking pin of the subsystem control unit. For example, the main system unit generates a locking instruction, which is used to control the subsystem unit to set the power-supply self-locking pin of the subsystem control unit to a high level. The subsystem unit responds to the locking instruction and performs a locking operation on the subsystem control unit; the main system unit generates an unlocking instruction, which is used to control the subsystem unit to set the power-supply self-locking pin of the subsystem control unit to a low level. The subsystem unit responds to the unlocking instruction and performs an unlocking operation on the subsystem control unit.

[0039] The main system unit of the embodiment of the present application may not supply power to the subsystem unit, but the subsystem control unit supplies power to the subsystem unit. The input end of the subsystem control unit includes a power supply control pin and a power supply self-locking pin. If the power supply control pin and / or the power supply self-locking pin are set to a high level, the subsystem control unit can continue to supply power to the subsystem unit. Through the locking operation of the subsystem unit on the subsystem control unit, the power supply self-locking pin is set to a high level. At this time, the subsystem control unit can supply power to the subsystem unit. Even if the level of the power supply control pin connected to the main system unit is abnormally flipped, it will not affect the power supply circuit of the subsystem, thereby avoiding the situation of abnormal power loss of the subsystem and improving the stability and reliability of the subsystem operation. Moreover, through the unlocking operation of the subsystem unit on the subsystem control unit, the power supply self-locking pin is set to a low level, and through the power-off operation of the subsystem unit by the subsystem control unit, the power supply control pin is also set to a low level. At this time, the subsystem control unit stops supplying power to the subsystem unit, thereby reducing the power consumption of the subsystem unit by actively stopping the operation of the subsystem unit on the basis of meeting performance requirements.

[0040] In other embodiments, the control instructions generated by the main system unit also include business channel opening instructions and business channel closing instructions, and the subsystem control unit is further used to: respond to the business channel opening instruction and execute the business channel opening operation on the subsystem unit; or respond to the business channel closing instruction and execute the business channel closing operation on the subsystem unit.

[0041] In some embodiments, the main system unit triggers a service channel opening operation or a service channel closing operation by setting a service channel control pin of the subsystem control unit. For example, the main system unit generates a service channel opening instruction, which is used to set the service channel control pin of the subsystem control unit to a high level. The subsystem control unit responds to the service channel opening instruction and performs a service channel opening operation on the subsystem unit; the main system unit generates a service channel closing instruction, which is used to set the service channel control pin of the subsystem control unit to a low level. The subsystem control unit responds to the service channel closing instruction and performs a service channel closing operation on the subsystem unit.

[0042] In the embodiment of the present application, the main system unit may not transmit business data to the subsystem unit, but the subsystem control unit may transmit business data to the subsystem unit. The input end of the subsystem control unit includes a business channel control pin and a business data transmission self-locking pin. If the business channel control pin and / or the business data transmission self-locking pin are set to a high level, the subsystem control unit can continue to transmit business data for the subsystem unit. Through the locking operation of the subsystem unit on the subsystem control unit, the business data transmission self-locking pin is set to a high level. At this time, the subsystem control unit can transmit business data for the subsystem unit. Even if the level of the business channel control pin connected to the main system unit is abnormally flipped, it will not affect the business data transmission circuit of the subsystem, thereby avoiding the occurrence of abnormal business data transmission of the subsystem, improving the stability and reliability of the subsystem operation. Moreover, through the unlocking operation of the subsystem unit on the subsystem control unit, the business data transmission self-locking pin is set to a low level, and through the subsystem control unit closing the business channel of the subsystem unit, the business channel control pin is also set to a low level. At this time, the subsystem control unit stops transmitting business data for the subsystem unit, thereby being able to reduce the power consumption of the multi-core system by actively stopping the business data transmission of the subsystem unit on the basis of meeting performance requirements.

[0043] In other embodiments, referring to Figure 2 The subsystem control unit 130 includes: a power supply module 210, which is used to supply power to the subsystem unit; a first switch control module 220, which is respectively connected to the power supply module 210, the main system unit 110 and the subsystem unit 120, and is used to control the connection between the power supply module and the subsystem unit according to the first signal and the second signal output by the main system unit and the third signal output by the subsystem unit.

[0044] In some embodiments, the power supply module may be a DC voltage source that provides a DC voltage with a stable output. The power supply module may be built into the subsystem control unit or may be external to the subsystem control unit. If the power supply module is built into the subsystem control unit, it may be connected to the first switch control module to form a switching power supply. The power supply module may also be a multi-channel DC voltage source that provides a multi-channel DC voltage with a stable output, which can meet a wider range of practical application scenarios, thereby improving the applicability and scalability of the multi-core system. The main system unit has a separate power supply built in. If the power supply module is external to the subsystem control unit, it may be connected to the main system unit to power the main system unit.

[0045] In some embodiments, the input end of the first switch control module includes a power supply control pin and a power supply self-locking pin, the power supply control pin receives a first signal output by the main system unit, and the power supply self-locking pin receives a second signal output by the subsystem unit. The power supply control pin is set to a high level or a low level by the first signal, and the power supply self-locking pin is set to a high level or a low level by the second signal. If the power supply control pin and / or the power supply self-locking pin are set to a high level, the first switch control module can control the power supply module to establish a connection with the subsystem unit, so that the power supply module supplies power to the subsystem unit. If both the power supply control pin and the power supply self-locking pin are set to a low level, the first switch control module can control the power supply module to disconnect from the subsystem unit, so that the power supply module stops supplying power to the subsystem unit. In other embodiments, the input end of the first switch control module includes a first power supply control pin, a second power supply control pin, and a power supply self-locking pin. The first power supply control pin receives a first signal output by the main system unit, the second power supply control pin receives a second signal output by the main system unit, and the power supply self-locking pin receives a third signal output by the subsystem unit. The first power supply control pin is set to a high level or a low level by the first signal, the second power supply control pin is set to a high level or a low level by the second signal, and the power supply self-locking pin is set to a high level or a low level by the third signal. If the first power supply control pin and / or the second power supply control and / or power supply self-locking pin are set to a high level, the first switch control module can control the power supply module to establish a connection with the subsystem unit, so that the power supply module supplies power to the subsystem unit. If the first power supply control pin, the second power supply control pin, and the power supply self-locking pin are all set to a low level, the first switch control module can control the power supply module to disconnect from the subsystem unit, so that the power supply module stops supplying power to the subsystem unit. In some embodiments, the first signal and the second signal are set according to a preset coding rule. For example, the first signal and the second signal are binary-encoded, and the binary-encoded signals are 01 and 10. During the power-on process of the subsystem unit, the power supply self-locking pin is initially set to a low level. If the first signal is set to 0 and the second signal is set to 1, at least one of the first power supply control pin and the second power supply control pin is set to a high level, the first switch control module outputs a high-level signal, the power supply module establishes a connection with the subsystem unit, and the power supply module supplies power to the subsystem unit. During the power-off process of the subsystem unit, the power supply self-locking pin is set to a low level. If the first signal is set to 1 and the second signal is set to 0, both the first power supply control pin and the second power supply control pin are set to a low level, the first switch control module outputs a low level, the connection between the power supply module and the subsystem unit is disconnected, and the power supply module stops supplying power to the subsystem unit.

[0046] In other embodiments, referring to Figure 3The first switch control module 220 includes: a first logic OR gate circuit 310 and a first switch circuit 320; wherein the first logic OR gate circuit 310 includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal and the second input terminal are respectively connected to the main system unit 110, the third input terminal is connected to the subsystem unit 120, and the output terminal is connected to the first switch circuit 320, and is used to output a fourth signal according to the first signal, the second signal and the third signal; the first switch circuit 320 is respectively connected to the power module 210, the output terminal of the first logic OR gate circuit 310 and the subsystem unit 120, and is used to control the connection between the power module 210 and the subsystem unit 120 according to the third signal.

[0047] In some embodiments, the first input of the first logic OR gate circuit is a power supply control pin, the second input of the first logic OR gate circuit is a power supply self-locking pin, the first input receives a first signal output by the main system unit, the second input receives a second signal output by the subsystem unit, and outputs a third signal according to a logic OR operation. For example, if the first signal and / or the second signal are high-level signals, the third signal output according to the logic OR operation is also a high-level signal; if the first signal and the second signal are both low-level signals, the third signal output according to the logic OR operation is also a low-level signal. In some embodiments, the first input of the first logic OR gate circuit is a first power supply control pin, the second input of the first logic OR gate circuit is a second power supply control pin, the third input of the first logic OR gate circuit is a power supply self-locking pin, the first input receives the first signal output by the main system unit, the second input receives the second signal output by the main system unit, the third input receives the third signal output by the subsystem unit, and outputs a fourth signal according to a logic OR operation. For example, if the first signal and / or the second signal and / or the third signal are high-level signals, the fourth signal output according to the logical OR operation is also a high-level signal; if the first signal, the second signal, and the third signal are all low-level signals, the fourth signal output according to the logical OR operation is also a low-level signal. In some embodiments, the first signal and the second signal are set according to a preset coding rule. For example, the first signal and the second signal are binary-coded, and the binary-coded signals are 11 and 00. If the power self-locking pin is set to a low level (the third signal is a low-level signal), the first signal is set to 1, and the second signal is set to 1, then at least one of the first power supply control pin and the second power supply control pin is set to a high level, and the fourth signal output according to the logical OR operation is a high-level signal. If the power self-locking pin is set to a low level (the third signal is a low-level signal), the first signal is set to 0, and the second signal is set to 0, then both the first power supply control pin and the second power supply control pin are set to a low level, and the fourth signal output according to the logical OR operation is a low-level signal.

[0048] In some embodiments, the on / off of the first switch circuit is controlled by a fourth signal. If the fourth signal is a high-level signal, the first switch circuit is connected, and the power module supplies power to the subsystem unit; if the fourth signal is a low-level signal, the first switch circuit is disconnected, and the power module stops supplying power to the subsystem unit. The first switch circuit can be a field-effect transistor (FET) or a bipolar junction transistor (BJT). If the first switch circuit is a field-effect transistor, it includes a source, a gate, and a drain. The source is connected to the power module, the gate is connected to the output end of the first logic OR gate circuit, and the drain is connected to the subsystem unit, and is used to control the connection between the power module and the subsystem unit according to the fourth signal. The gate is equivalent to the control end of the field-effect transistor. By applying a voltage to the gate, the connection between the source and the base can be controlled. Field-effect transistors include junction field-effect transistors (JFETs) and metal-oxide semiconductor field-effect transistors (MOSFETs). MOSFETs include N-channel transistors (NMOS) and P-channel transistors (PMOS). For example, if the first switching circuit is an NMOS, when a positive voltage is applied to the gate, negatively charged electrons are attracted to the surface, forming a channel that allows electrons, the majority carriers of the N-type semiconductor, to flow from the source to the drain, turning the NMOS on. If this voltage is removed, or a negative voltage is applied, the channel is not formed, and carriers cannot flow between the source and drain, turning the NMOS off. If the first switching circuit is a transistor, it includes an emitter, a base, and a collector. The emitter is connected to the power module, the base is connected to the output of the first logic OR gate circuit, and the collector is connected to the subsystem unit, which is used to control the connection between the power module and the subsystem unit based on the fourth signal. The base acts as the control terminal of the transistor; applying a voltage to the base can control the connection between the emitter and collector. Field effect transistors are voltage-controlled current devices, and transistors are current-controlled current devices. Depending on the actual application scenario, field effect transistors or transistors can be selected as the first switching circuit.

[0049] In other embodiments, referring to Figure 4 The subsystem control unit 130 also includes: a business module 410, which is used for transmitting business data of the subsystem unit; a second switch control module 420, which is respectively connected to the business module 410, the main system unit 110 and the subsystem unit 120, and is used to control the connection between the business module 410 and the subsystem unit 120 according to the fifth signal and the sixth signal output by the main system unit 110 and the seventh signal output by the subsystem unit 120.

[0050] In some embodiments, the service module can be a memory for storing service data transmitted by the subsystem unit; the service module can also be a communication module for transmitting communication data between the subsystem unit. The service module can be built into the subsystem control unit or external to the subsystem control unit. The main system unit has a separate built-in service module. If the service module is external to the subsystem control unit, it can be connected to the main system unit to transmit service data to the main system unit.

[0051] In some embodiments, the input end of the second switch control module includes a service channel control pin and a service data transmission self-locking pin. The service channel control pin receives a fourth signal output by the main system unit, and the service data transmission self-locking pin receives a fifth signal output by the subsystem unit. The service channel control pin is set to a high level or a low level by the fourth signal, and the service data transmission self-locking pin is set to a high level or a low level by the fifth signal. If the service channel control pin and / or the service data transmission self-locking pin are set to a high level, the second switch control module can control the service module to establish a connection with the subsystem unit, so that the service module transmits service data to the subsystem unit. If the service channel control pin and the service data transmission self-locking pin are both set to a low level, the second switch control module can control the service module to disconnect from the subsystem unit, so that the service module stops transmitting service data to the subsystem unit. In other embodiments, the input end of the second switch control module includes a first service channel control pin, a second service channel control pin, and a service data transmission self-locking pin. The first service channel control pin receives a fifth signal output by the main system unit, the second service channel control pin receives a sixth signal output by the main system unit, and the service data transmission self-locking pin receives a seventh signal output by the subsystem unit. The first service channel control pin is set to a high level or a low level according to the fifth signal, the second service channel control pin is set to a high level or a low level according to the sixth signal, and the service data transmission self-locking pin is set to a high level or a low level according to the seventh signal. If the first service channel control pin and / or the second service channel control pin and / or the service data transmission self-locking pin are set to a high level, the second switch control module can control the service module to establish a connection with the subsystem unit, so that the service module transmits service data to the subsystem unit. If the first service channel control pin, the second service channel control pin, and the service data transmission self-locking pin are all set to a low level, the second switch control module can control the service module to disconnect from the subsystem unit, so that the service module stops transmitting service data to the subsystem unit.

[0052] In other embodiments, referring to Figure 5 The second switch control module 420 is also connected to the first switch control module 220 . If the power module 210 is disconnected from the subsystem unit 120 , the service module 410 is disconnected from the subsystem unit 120 .

[0053] In some embodiments, the subsystem control unit includes a power module, a service module, a first switch control module, and a second switch control module. The first switch control module is connected to the power module, the main system unit, and the subsystem unit, respectively, and is configured to output a third signal to control the connection between the power module and the subsystem unit based on a first signal output by the main system unit and a second signal output by the subsystem unit. The second switch control module is connected to the service module, the main system unit, the subsystem unit, and the first switch control module, respectively, and is configured to output a sixth signal to control the connection between the service module and the subsystem unit based on a fourth signal output by the main system unit, a fifth signal output by the subsystem unit, and the third signal output by the first switch control module. If the third signal is a low-level signal, the sixth signal is also a low-level signal, and the connection between the service module and the subsystem unit is disconnected. Even if the fourth signal and / or the fifth signal are high-level signals, the low-level state of the sixth signal will not be changed. In other embodiments, the subsystem control unit includes a power module, a service module, a first switch control module, and a second switch control module. The first switch control module is respectively connected to the power module, the main system unit, and the subsystem unit, and is configured to output a fourth signal to control the connection between the power module and the subsystem unit based on the first and second signals output by the main system unit and the third signal output by the subsystem unit. The second switch control module is respectively connected to the service module, the main system unit, the subsystem unit, and the first switch control module, and is configured to output an eighth signal to control the connection between the service module and the subsystem unit based on the fifth and sixth signals output by the main system unit, the seventh signal output by the subsystem unit, and the fourth signal output by the first switch control module. If the fourth signal is a low-level signal, the eighth signal is also a low-level signal, and the connection between the service module and the subsystem unit is disconnected. Even if the fifth signal, the sixth signal, and / or the seventh signal are high-level signals, the low-level state of the eighth signal will not be changed.

[0054] In other embodiments, referring to Figure 6 The second switch control module 420 includes: a second logic OR gate circuit 610 and a second switch circuit 620; wherein the second logic OR gate circuit 610 includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal and the second input terminal are respectively connected to the main system unit 110, the third input terminal is connected to the subsystem unit 120, and the output terminal is connected to the second switch circuit 620, and is used to output the eighth signal according to the fifth signal, the sixth signal and the seventh signal; the second switch circuit 620 is respectively connected to the service module 410, the output terminal of the second logic OR gate circuit 610 and the subsystem unit 120, and is used to control the connection between the service module 410 and the subsystem unit 120 according to the eighth signal.

[0055] In some embodiments, the first input of the second logic OR gate circuit is a service channel control pin, the second input of the second logic OR gate circuit is a service data transmission self-locking pin, the first input receives the fourth signal output by the main system unit, the second input receives the fifth signal output by the subsystem unit, and outputs a sixth signal according to a logic OR operation. For example, if the fourth signal and / or the fifth signal are high-level signals, the sixth signal output according to the logic OR operation is also a high-level signal; if the fourth signal and the fifth signal are both low-level signals, the sixth signal output according to the logic OR operation is also a low-level signal. In other embodiments, the first input of the second logic OR gate circuit is a first service channel control pin, the second input of the second logic OR gate circuit is a second service channel control pin, the third input of the second logic OR gate circuit is a service data transmission self-locking pin, the first input receives the fifth signal output by the main system unit, the second input receives the sixth signal output by the main system unit, the third input receives the seventh signal output by the subsystem unit, and outputs an eighth signal according to a logic OR operation. For example, if the fifth signal and / or the sixth signal and / or the seventh signal are high-level signals, the eighth signal output according to the logical OR operation is also a high-level signal; if the fifth signal, the sixth signal and the seventh signal are all low-level signals, the eighth signal output according to the logical OR operation is also a low-level signal.

[0056] In some embodiments, the on / off of the second switch circuit is controlled by an eighth signal. If the eighth signal is a high-level signal, the second switch circuit is connected, and the business module transmits business data to the subsystem unit; if the eighth signal is a low-level signal, the second switch circuit is disconnected, and the business module stops transmitting business data to the subsystem unit. The second switch circuit can be a field-effect transistor or a triode. If the second switch circuit is a field-effect transistor, it includes a source, a gate, and a drain. The source is connected to the business module, the gate is connected to the output end of the second logic OR gate circuit, and the drain is connected to the subsystem unit, and is used to control the on / off connection between the business module and the subsystem unit according to the eighth signal. If the second switch circuit is a triode, it includes an emitter, a base, and a collector. The emitter is connected to the business module, the base is connected to the output end of the second logic OR gate circuit, and the collector is connected to the subsystem unit, and is used to control the on / off connection between the business module and the subsystem unit according to the eighth signal.

[0057] In the second aspect, the embodiment of the present application provides a control method for a multi-core system, wherein the multi-core system includes a main system unit, a subsystem unit and a subsystem control unit, the main system unit is connected to the subsystem unit and the subsystem control unit respectively, and the subsystem unit is also connected to the subsystem control unit, Figure 7 , the control methods of multi-core systems include:

[0058] S0710, the main system unit controls the subsystem control unit and the subsystem unit respectively to execute: a power-on step and a power-off step.

[0059] In some embodiments, reference Figure 8 , the power-on steps include:

[0060] S0810, generating a power-on instruction to control the subsystem control unit to perform a power-on operation on the subsystem unit;

[0061] S0820, generating a power-on instruction to control the power-on operation of the subsystem unit;

[0062] S0830: Generate a locking instruction and control the subsystem unit to execute a locking operation on the subsystem control unit.

[0063] In some embodiments, in step S0810, the main system unit triggers a power-on operation by setting the power supply control pin of the subsystem control unit. For example, the main system unit generates a power-on instruction, and the power-on instruction is used to set the power supply control pin of the subsystem control unit to a high level. The subsystem control unit responds to the power-on instruction and performs a power-on operation on the subsystem unit. In step S0820, the main system unit triggers a power-on operation by setting the power-on control pin of the subsystem unit. For example, the main system unit generates a power-on instruction, and the power-on instruction is used to set the power-on control pin of the subsystem unit to a high level. The subsystem unit responds to the power-on instruction and performs a power-on operation. In step S0830, the subsystem unit triggers a locking operation by setting the power self-locking pin of the subsystem control unit. For example, the main system unit generates a locking instruction, and the locking instruction is used to control the subsystem unit to set the power self-locking pin of the subsystem control unit to a high level. The subsystem unit responds to the locking instruction and performs a locking operation on the subsystem control unit. By executing the power-on step, the power supply self-locking pin is set to a high level. At this time, the subsystem control unit can power the subsystem unit. Even if the level of the power supply control pin connected to the main system unit is abnormally flipped, it will not affect the power supply circuit of the subsystem, thereby avoiding the situation of abnormal power loss of the subsystem and improving the stability and reliability of the subsystem operation. In other embodiments, after step S0830, the subsystem unit feedbacks the execution status of the locking operation to the main system unit via the inter-core serial / parallel data communication bus. After the main system unit knows that the subsystem unit has completed the locking operation, it can actively set the level of the power supply control pin to a low level, thereby reducing the power consumption of the main system unit while meeting performance requirements.

[0064] In some embodiments, reference Figure 9 The power-off steps include:

[0065] S0910, generating an unlocking instruction, and controlling the subsystem unit to execute an unlocking operation on the subsystem control unit;

[0066] S0920, generating a shutdown instruction to control the shutdown operation of the subsystem unit;

[0067] S0930: Generate a power-off instruction to control the subsystem control unit to execute a power-off operation on the subsystem unit.

[0068] In some embodiments, in step S0910, the subsystem unit triggers an unlocking operation by setting the power self-locking pin of the subsystem control unit. For example, the main system unit generates an unlocking instruction, and the unlocking instruction is used to control the subsystem unit to set the power self-locking pin of the subsystem control unit to a low level. The subsystem unit responds to the unlocking instruction and performs an unlocking operation on the subsystem control unit. In step S0920, the main system unit triggers a shutdown operation by setting the power on / off control pin of the subsystem unit. For example, the main system unit generates a shutdown instruction, and the shutdown instruction is used to set the power on / off control pin of the subsystem unit to a low level. The subsystem unit responds to the shutdown instruction and performs a shutdown operation. In step S0930, the main system unit triggers a power-off operation by setting the power control pin of the subsystem control unit. For example, the main system unit generates a power-off instruction, and the power-off instruction is used to set the power control pin of the subsystem control unit to a low level. The subsystem control unit responds to the power-off instruction and performs a power-off operation on the subsystem unit. By executing the power-off step, the power supply self-locking pin is set to a low level, and the power-off operation of the subsystem unit is performed by the subsystem control unit, and the power supply control pin is also set to a low level. At this time, the subsystem control unit stops supplying power to the subsystem unit, thereby reducing the power consumption of the subsystem unit by actively stopping the operation of the subsystem unit while meeting the performance requirements. In other embodiments, after step S0910, the subsystem unit feeds back the execution status of the unlocking operation to the main system unit via the inter-core serial / parallel data communication bus. After the main system unit learns that the subsystem unit has completed the unlocking operation, it can immediately start executing step S0920 or step S0930, thereby reducing the delay in executing the power-off step and improving the execution efficiency of the power-off step.

[0069] In some embodiments, the power-on instruction of step S0810 and the power-off instruction of step S0930 are both preset coded signals, and the coded signals include a first signal and a second signal. For example, the first signal and the second signal are binary coded, and the binary coded signals are 01 and 10. During the power-on process of the subsystem unit, the power supply self-locking pin is initially set to a low level. If the first signal is set to 1 and the second signal is set to 0, at least one of the first power supply control pin and the second power supply control pin is set to a high level, the first switch control module outputs a high level signal, the power supply module establishes a connection with the subsystem unit, and the power supply module supplies power to the subsystem unit. During the power-off process of the subsystem unit, the power supply self-locking pin is set to a low level. If the first signal is set to 0 and the second signal is set to 1, both the first power supply control pin and the second power supply control pin are set to a low level, the first switch control module outputs a low level, the connection between the power supply module and the subsystem unit is disconnected, and the power supply module stops supplying power to the subsystem unit.

[0070] In some embodiments, the multi-core system includes a main system unit, a subsystem unit and a subsystem control unit. The main system unit is connected to the subsystem unit and the subsystem control unit respectively. The subsystem unit is also connected to the subsystem control unit. The control method of the multi-core system includes a service channel opening step and a service channel closing step.

[0071] In some embodiments, reference Figure 10 , the steps to open a service channel include:

[0072] S1010, generating a service channel opening instruction to control the subsystem control unit to execute a service channel opening operation on the subsystem unit;

[0073] S1020, generating a power-on instruction to control the power-on operation of the subsystem unit;

[0074] S1030: Generate a locking instruction, and control the subsystem unit to execute a locking operation on the subsystem control unit.

[0075] In some embodiments, in step S1010, the main system unit triggers a service channel opening operation by setting the service channel control pin of the subsystem control unit. For example, the main system unit generates a service channel opening instruction, and the service channel opening instruction is used to set the service channel control pin of the subsystem control unit to a high level. The subsystem control unit responds to the service channel opening instruction and performs the service channel opening operation on the subsystem unit. In step S1020, the main system unit triggers a power-on operation by setting the power-on and power-off control pin of the subsystem unit. For example, the main system unit generates a power-on instruction, and the power-on instruction is used to set the power-on and power-off control pin of the subsystem unit to a high level. The subsystem unit responds to the power-on instruction and performs the power-on operation. In step S1030, the subsystem unit triggers a locking operation by setting the service data transmission self-locking pin of the subsystem control unit. For example, the main system unit generates a locking instruction, and the locking instruction is used to control the subsystem unit to set the service data transmission self-locking pin of the subsystem control unit to a high level. The subsystem unit responds to the locking instruction and performs the locking operation on the subsystem control unit. By executing the service channel opening step, the service data transmission self-locking pin is set to a high level. At this point, the subsystem control unit can transmit service data for the subsystem unit. Even if the level of the service channel control pin connected to the main system unit is abnormally flipped, it will not affect the subsystem's service data transmission loop, thereby avoiding abnormal subsystem service output transmission and improving the stability and reliability of the subsystem operation. In other embodiments, after step S1030, the subsystem unit feedbacks the execution status of the locking operation to the main system unit via the inter-core serial / parallel data communication bus. After the main system unit learns that the subsystem unit has completed the locking operation, it can actively set the level of the service channel control pin to a low level, thereby reducing the power consumption of the main system unit while meeting performance requirements.

[0076] In some embodiments, reference Figure 11 , the steps for closing the service channel include:

[0077] S1110, generating an unlocking instruction, and controlling the subsystem unit to execute an unlocking operation on the subsystem control unit;

[0078] S1120, generating a shutdown instruction to control the shutdown operation of the subsystem unit;

[0079] S1130: Generate a service channel closing instruction and control the subsystem control unit to execute a service channel closing operation on the subsystem unit.

[0080] In some embodiments, in step S1110, the subsystem unit triggers an unlock operation by setting the service data transmission self-locking pin of the subsystem control unit. For example, the main system unit generates an unlock instruction, and the unlock instruction is used to control the subsystem unit to set the service data transmission self-locking pin of the subsystem control unit to a low level. The subsystem unit responds to the unlock instruction and performs an unlock operation on the subsystem control unit. In step S1120, the main system unit triggers a shutdown operation by setting the power on / off control pin of the subsystem unit. For example, the main system unit generates a shutdown instruction, and the shutdown instruction is used to set the power on / off control pin of the subsystem unit to a low level. The subsystem unit responds to the shutdown instruction and performs a shutdown operation. In step S1130, the main system unit triggers a service channel closing operation by setting the service channel control pin of the subsystem control unit. For example, the main system unit generates a service channel closing instruction, and the service channel closing instruction is used to set the service channel control pin of the subsystem control unit to a low level. The subsystem control unit responds to the service channel closing instruction and performs a service channel closing operation on the subsystem unit. By executing the service channel closing step, the service data transmission self-locking pin is set to a low level, and the service channel of the subsystem unit is closed by the subsystem control unit, and the service channel control pin is also set to a low level. At this time, the subsystem control unit stops transmitting service data to the subsystem unit, thereby actively stopping the operation of the subsystem unit on the basis of meeting performance requirements and reducing the power consumption of the subsystem unit. In other embodiments, after step S1110, the subsystem unit feeds back the execution status of the unlocking operation to the main system unit via the inter-core serial / parallel data communication bus. After the main system unit learns that the subsystem unit has completed the unlocking operation, it can immediately start executing step S1120 or step S1130, thereby reducing the delay in executing the service channel closing step and improving the execution efficiency of the service channel closing step.

[0081] In some embodiments, reference Figure 12 , the power-off steps also include:

[0082] S1210, generating an unlocking instruction, and controlling the subsystem unit to execute an unlocking operation on the subsystem control unit;

[0083] S1220, generating a shutdown instruction to control the shutdown operation of the subsystem unit;

[0084] S1230, generating a power-off instruction to control the subsystem control unit to execute a power-off operation on the subsystem unit;

[0085] S1240: Generate a service channel closing instruction and control the subsystem control unit to execute a service channel closing operation on the subsystem unit.

[0086] In some embodiments, reference Figure 9 and Figure 11 Steps S1210 to S1230 are similar to steps S0910 to S0930, and step S1240 is similar to step S1130. After the power-off operation is performed, the subsystem control unit stops supplying power to the subsystem unit, and the subsystem unit stops working. At this time, the subsystem unit cannot continue to transmit service data. If the service channel is still open, it will cause wasteful power consumption of the subsystem control unit. Therefore, after the power-off operation is performed, the service channel shutdown operation is automatically triggered to avoid wasted power consumption of the subsystem control unit.

[0087] On the third aspect, an embodiment of the present application provides a multi-core device, which includes the multi-core system of some embodiments of the present application; or, the multi-core device includes a memory, a processor, and a program stored in the memory and runnable on the processor. When the program is executed by the processor, the control method of the multi-core system of some embodiments of the present application is implemented.

[0088] In a fourth aspect, an embodiment of the present application provides a readable storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement a control method for a multi-core system that executes some embodiments of the second aspect of the present application.

[0089] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0090] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0091] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the above-mentioned implementation methods. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A multi-core system comprising: A main system unit, a subsystem unit and a subsystem control unit; wherein the main system unit, the subsystem unit and the subsystem control unit are three independent units, The main system unit is used to generate control instructions, including power-on instructions and power-off instructions, locking instructions and unlocking instructions, power-on instructions and power-off instructions; The subsystem units are connected to the main system unit and the subsystem control unit respectively, and are used to: In response to the power-on instruction, a power-on operation is performed; in response to the power-off instruction, a power-off operation is performed; in response to the locking instruction, a locking operation is performed on the subsystem control unit; in response to the unlocking instruction, an unlocking operation is performed on the subsystem control unit; The subsystem control unit includes a power supply module and a first switch control module. The power supply module is used to supply power to the subsystem unit. The first switch control module is connected to the power supply module, the main system unit and the subsystem unit respectively, and is used to control the connection between the power supply module and the subsystem unit according to the signal output by the main system unit and the signal output by the subsystem unit.

2. The multi-core system according to claim 1, wherein: The control instructions also include a service channel opening instruction and a service channel closing instruction, and the subsystem control unit is further configured to: In response to the service channel opening instruction, a service channel opening operation for the subsystem unit is performed; or, in response to the service channel closing instruction, a service channel closing operation for the subsystem unit is performed.

3. The multi-core system according to claim 1 or 2, characterized in that: The controlling the connection between the power module and the subsystem unit according to the signal output by the main system unit and the signal output by the subsystem unit includes: The first switch control module controls the connection between the power module and the subsystem unit according to the first signal and the second signal output by the main system unit and the third signal output by the subsystem unit.

4. The multi-core system according to claim 3, wherein: The first switch control module includes: a first logic OR gate circuit and a first switch circuit; wherein, The first logic OR gate circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal and the second input terminal are respectively connected to the main system unit, the third input terminal is connected to the subsystem unit, and the output terminal is connected to the first switch circuit, and is configured to output a fourth signal according to the first signal, the second signal, and the third signal; The first switch circuit is respectively connected to the power module, the output end of the first logic OR gate circuit and the subsystem unit, and is used to control the connection between the power module and the subsystem unit according to the fourth signal.

5. The multi-core system according to claim 3, wherein: The subsystem control unit further includes: A service module, used for transmitting service data of the subsystem unit; The second switch control module is connected to the business module, the main system unit and the subsystem unit respectively, and is used to control the connection between the business module and the subsystem unit according to the fifth signal and the sixth signal output by the main system unit and the seventh signal output by the subsystem unit.

6. The multi-core system according to claim 5, characterized in that: The second switch control module is also connected to the first switch control module, and if the connection between the power module and the subsystem unit is disconnected, the connection between the service module and the subsystem unit is disconnected.

7. The multi-core system according to claim 6, characterized in that: The second switch control module includes: a second logic OR gate circuit and a second switch circuit; wherein, The second logic OR gate circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal and the second input terminal are respectively connected to the main system unit, the third input terminal is connected to the subsystem unit, and the output terminal is connected to the second switch circuit, and is configured to output an eighth signal according to the fifth signal, the sixth signal, and the seventh signal; The second switch circuit is connected to the service module, the output end of the second logic OR gate circuit and the subsystem unit respectively, and is used to control the connection between the service module and the subsystem unit according to the eighth signal.

8. A control method for a multi-core system, the multi-core system comprising a main system unit, a subsystem unit and a subsystem control unit, wherein: The main system unit, the subsystem unit, and the subsystem control unit are three independent units. The main system unit is connected to the subsystem unit and the subsystem control unit respectively. The subsystem unit is also connected to the subsystem control unit. The subsystem control unit includes a power module. The method includes a power-on step and a power-off step. The power-on step includes: The main system unit generates a power-on instruction to control the subsystem control unit to perform a power-on operation on the subsystem unit, wherein the power-on instruction includes a first signal; The main system unit generates a power-on instruction to control the power-on operation of the subsystem unit; The main system unit generates a locking instruction to control the subsystem unit to perform a locking operation on the subsystem control unit, wherein the locking operation includes generating a third signal; The subsystem control unit controls the communication between the power module and the subsystem unit according to the first signal and the third signal.

9. The multi-core system control method according to claim 8, characterized in that: The method further comprises a service channel opening step and a service channel closing step.

10. The multi-core system control method according to claim 8 or 9, characterized in that: The power-off step includes: generating an unlocking instruction to control the subsystem unit to execute an unlocking operation on the subsystem control unit; Generate a shutdown instruction to control the shutdown operation of the subsystem unit; A power-off instruction is generated to control the subsystem control unit to execute a power-off operation on the subsystem unit.

11. The multi-core system control method according to claim 10, characterized in that: The power-on instruction further includes a second signal, and both the first signal and the second signal are preset coded signals.

12. The multi-core system control method according to claim 9, characterized in that: The service channel opening step includes: Generate a service channel opening instruction to control the subsystem control unit to execute a service channel opening operation on the subsystem unit; Generate a power-on instruction to control the power-on operation of the subsystem unit; A locking instruction is generated to control the subsystem unit to perform a locking operation on the subsystem control unit.

13. The multi-core system control method according to claim 9, characterized in that: The service channel closing step includes: generating an unlocking instruction to control the subsystem unit to execute an unlocking operation on the subsystem control unit; Generate a shutdown instruction to control the shutdown operation of the subsystem unit; Generate a service channel closing instruction and control the subsystem control unit to execute a service channel closing operation on the subsystem unit.

14. The multi-core system control method according to claim 10, characterized in that: The power-off step further includes: After the power-off operation is performed, a service channel closing instruction is generated to control the subsystem control unit to perform a service channel closing operation on the subsystem unit.

15. A multi-core device, comprising the multi-core system according to any one of claims 1 to 7; or, the multi-core device comprising a memory, a processor, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the control method of the multi-core system according to any one of claims 8 to 14 is implemented.

16. A computer-readable storage medium, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the control method of the multi-core system according to any one of claims 8 to 14.

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