A parallel computing optimization method based on single-core DSP

Abstract

A parallel computing optimization method based on a single-core DSP comprises the following steps: dividing a program to be run into a key complex program and a non-key complex program, wherein the key complex program is fixedly run in the internal cache of the DSP, and the non-key complex program is run in an externally configured RAM memory; for loop statements in the running program, the loop counter is decremented, and loop nesting is not performed in the loop body; the hardware resources used by each loop body do not exceed the number of operation units and registers in the processor, so that the statements in each loop body can be executed in parallel in multiple operation units at the same time; and single instruction multiple data instructions are used to assemble the data for the same calculation processing to improve the parallel degree of data processing.

Description

Technical Field

[0001] The invention relates to a parallel computing optimization method based on a single-core DSP, belonging to the technical field of satellite-borne computers. Background Art

[0002] my country's first Mars exploration achieved the goal of "orbiting, landing, and patrolling" Mars through a single flight mission, and the lander and rover "Zhurong" Mars rover broke through key technologies such as safe and autonomous patrolling on the surface of Mars. During the autonomous patrol process, the navigation control unit of the Mars rover's GNC subsystem needs to run key complex algorithms such as navigation image processing, obstacle avoidance image processing, autonomous path planning, visual odometry, and motion control, facing the difficulties of large image data processing volume and long algorithm running time. Therefore, in order to meet the requirements of autonomous, safe, and efficient patrols of the Mars rover, it is necessary to optimize the various complex algorithms on the navigation control unit in parallel, improve the algorithm operation efficiency, and efficiently realize the Mars rover's environmental perception, autonomous planning, posture determination, and motion control functions. Summary of the invention

[0003] The technical problem to be solved by the present invention is: to overcome the shortcomings of the prior art and provide a parallel computing optimization method based on a single-core DSP. The method improves the parallelism of storage access, instruction execution and data processing, uses segmented addressing compilation to fix the key complex algorithm to run in the internal cache of the DSP, improves the loop and branch judgment structure of the algorithm, and uses parallel optimization measures such as processor single instruction multiple data processing instructions to improve the parallel operation efficiency of the key complex algorithm of the Mars rover and ensure the autonomous, safe and efficient patrol of the Mars rover.

[0004] The purpose of the present invention is achieved through the following technical solutions:

[0005] A parallel computing optimization method based on a single-core DSP comprises the following steps:

[0006] The programs to be run are divided into key complex programs and non-key complex programs, wherein the key complex programs are fixedly run in the internal cache of the DSP, and the non-key complex programs are run in the externally configured RAM memory;

[0007] For loop statements in the running program, the loop counter is decremented, and loops are not nested in the loop body; the hardware resources used by each loop body do not exceed the number of computing units and registers in the processor, so that the statements in each loop body can be executed in parallel in multiple computing units at the same time;

[0008] Single instruction multiple data instructions are used to assemble data for the same calculation processing to improve the parallelism of data processing.

[0009] Preferably, fixed-address compilation is adopted for both critical complex programs and non-critical complex programs, and the fixed-address compilation is implemented by defining code segments and specifying the code segment address space in the compiler link file.

[0010] Preferably, no function calls or breaks are performed in the loop body.

[0011] Preferably, the internal cache access bit width of the DSP is much larger than the externally configured RAM access bit width.

[0012] Preferably, all branch judgment statements in the running program are changed into conditional operation statements.

[0013] Preferably, the program to be run is an autonomous planning algorithm or a visual odometry algorithm.

[0014] A single-core DSP, wherein the parallel computing in the single-core DSP is optimized by using the above-mentioned parallel computing optimization method.

[0015] A processor includes the above-mentioned single-core DSP and a RAM configured outside the DSP.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] (1) The present invention improves the parallelism of storage access: segmented addressing compilation is used to fix the key complex algorithm to run in the DSP internal cache with a larger data access bit width;

[0018] (2) The present invention expands and optimizes the loop structure in the algorithm, thereby improving the parallelism of instruction execution;

[0019] (3) The present invention improves the branch judgment structure of the algorithm, replaces the branch judgment statement with a conditional operation statement, fully utilizes the instruction pipeline function of the processor, and provides instruction execution parallelism;

[0020] (4) The present invention improves the parallelism of data processing: the algorithm is implemented using processor single instruction multiple data processing instructions;

[0021] (5) The parallel optimization method of the present invention improves the performance of the Mars rover's autonomous planning and visual odometry algorithms by 2.5 times. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of parallel computing based on single-core DSP. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0024] A parallel computing optimization method based on a single-core DSP first improves the parallelism of storage access to achieve the purpose of fetching multiple program instructions at one time; then, based on the acquisition of multiple instructions, the parallelism of instruction execution is improved so that multiple instructions can be executed in parallel; finally, the parallelism of data processing is improved so that when executing an instruction, the instruction can process multiple data at the same time. The specific implementation process is as follows Figure 1 As shown:

[0025] 1) The first major step: improve the parallelism of storage access. Based on the hierarchical memory structure characteristics of the DSP processor, the cache inside the DSP has a faster access rate and a larger data access bit width than the RAM memory configured outside the processor. For example, the internal cache access bit width of the DSP used in the Mars rover navigation control unit is 256 bits, and the external RAM access bit width is 32 bits. Compared with the externally configured RAM memory, when the DSP accesses the internal cache, more data can be obtained in one memory access operation. Therefore, in order to improve the parallel operation efficiency of the algorithm, this method will address and compile different key complex algorithms so that the key complex algorithm program is fixedly run in the internal cache, and the non-key complex algorithm runs in the externally configured RAM memory.

[0026] 2) Address compilation is achieved by defining code segments and specifying the code segment address space in the compiler link file.

[0027] 3) Define the code segment method:

[0028] #pragma CODE_SECTION(key algorithm function name, "KeyAlgorithmText")

[0029] 4) Specify the code segment address space method in the compiler link file:

[0030] MEMORY

[0031] {

[0032] InternalRAM: origin = internal cache start address, length = internal cache byte length

[0033] ExternalRAM: origin = external memory starting address, length = external memory byte length

[0034] }

[0035] SECTIONS

[0036] {

[0037] .KeyAlgorithmText:>InternalRAM

[0038] .NonKeyAlgorithmText:>ExternalRAM

[0039] }

[0040] 5) The second major step: improve the parallelism of instruction execution. Based on the characteristics of DSP containing multiple computing function units and multiple register groups, a large number of loop statements contained in the algorithm are expanded and optimized so that the statements in the loop body can be executed in parallel in multiple computing units at the same time; at the same time, a large number of branch judgment statements contained in the algorithm are improved into conditional operation statements to reduce program jumps, avoid interruption of the processor instruction pipeline, and give full play to the parallel advantages of the processor's instruction pipeline.

[0041] 6) The expansion optimization method of the loop statement is as follows:

[0042] (1) The loop counter is decremented;

[0043] (2) No function calls or break exits are made within the loop body;

[0044] (3) No loop nesting is performed within the loop body;

[0045] (4) Split complex large loops into simple small loops so that the hardware resources used by each loop do not exceed the number of computing function units and registers in the processor.

[0046] 7) The third step: improve the parallelism of data processing. Image processing algorithms have the characteristics of performing the same operation on a large amount of data, which matches the characteristics of DSP processors using very long instruction word (VLIW) architecture and supporting single instruction multiple data (SIMD) parallel instructions. SIMD instructions are used to assemble the data processing part that affects the efficiency of the algorithm to improve the parallelism of data processing.

[0047] A single-core DSP, wherein the parallel computing in the single-core DSP is optimized by using the above-mentioned parallel computing optimization method.

[0048] A processor includes the above-mentioned single-core DSP and a RAM configured outside the DSP.

[0049] In summary, with the development of autonomous and intelligent operation of spacecraft, the functional algorithms for on-orbit image information processing and autonomous planning of spacecraft are becoming more and more complex. The performance of the algorithms is increasingly restricting the autonomous, safe and efficient operation of spacecraft. It is necessary to optimize the key complex algorithms in parallel to improve the system operation performance. The parallel computing optimization method based on a single-core DSP proposed in this application can effectively improve the parallel processing performance of key complex algorithms by improving the parallelism of storage access, instruction execution and data processing, which can well meet the parallel processing requirements of future spacecraft and has a broad application prospect.

[0050] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0051] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A parallel computing optimization method based on a single-core DSP, characterized in that: The steps include: The programs to be run are divided into key complex programs and non-key complex programs, wherein the key complex programs are fixedly run in the internal cache of the DSP, and the non-key complex programs are run in the externally configured RAM memory; fixed-address compilation is adopted for both key complex programs and non-key complex programs, and fixed-address compilation is realized by defining code segments and specifying the code segment address space in the compiler link file; the branch judgment statements in the programs to be run are all changed into conditional operation statements; For loop statements in the running program, the loop counter is decremented, and loops are not nested in the loop body; the hardware resources used by each loop body do not exceed the number of computing units and registers in the processor, so that the statements in each loop body can be executed in parallel in multiple computing units at the same time; Single instruction multiple data instructions are used to assemble data for the same calculation processing to improve the parallelism of data processing.

2. The parallel computing optimization method according to claim 1, characterized in that: No function calls or breaks are performed in the loop body.

3. The parallel computing optimization method according to claim 1 or 2, characterized in that: The internal cache access bit width of the DSP is much larger than the external RAM access bit width.

4. The parallel computing optimization method according to claim 1 or 2, characterized in that: The running program is treated as an autonomous planning algorithm or a visual odometry algorithm.

5. A single-core DSP, characterized in that: The parallel computing in the single-core DSP is optimized using the parallel computing optimization method described in claim 1 or 2.

6. A processor, characterized in that: It comprises the single-core DSP as claimed in claim 5, and a RAM configured outside the DSP.

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