A Steiner minimum tree construction method for obstacle-avoiding X-structure under time relaxation constraints

Abstract

The present invention relates to a Steiner minimum tree construction method for an X-structure with obstacle bypassing under a timing relaxation constraint. First, a wiring topology initialization strategy is designed. A PD tree is constructed and encoded based on the X-structure using a PD algorithm to obtain a wiring topology that optimizes the line length and radius in a trade-off manner. Secondly, a particle swarm optimization algorithm based on genetic operations is proposed. The traditional genetic algorithm is combined with the particle swarm optimization algorithm to solve the discrete problem of constructing a Steiner minimum tree for an X-structure with obstacle bypassing under a timing relaxation constraint. In addition, a wiring topology normalization strategy is designed. On the one hand, the interconnection line mode is changed or the obstacle endpoint is added as a pseudo Steiner point. On the other hand, the critical path with a negative timing relaxation value is disconnected and rewound. Finally, a wiring topology optimization method is proposed to globally optimize the connection of the interconnection line and select the optimal wiring topology. The method of the present invention can obtain a better wiring topology structure while better satisfying the timing relaxation constraint.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit computer-aided design, and more particularly to a method for constructing an Obstacle-Avoiding X-architecture Steiner Minimal Tree with Slack Constraint (OAXSMT-SC) under a timing slack constraint. Background Art

[0002] As a key stage of VLSI (Very Large Scale Integration, VLSI) physical design, wiring needs to determine the wiring topology of each wire net on the circuit and optimize the circuit performance. The Steiner tree algorithm is the best method to solve the wiring problem. The X-architecture Steiner Minimal Tree (XSMT) makes fuller use of the wiring space resources, shortens the length of the interconnection line, reduces the delay of the interconnection line, reduces the area of ​​the chip, and greatly improves the chip performance. With the emergence of wiring obstacles such as intellectual property protection modules, pre-wired wire nets and macro cells in the chip, it is necessary to consider the influence of obstacles when constructing the Steiner minimum tree. The problem of constructing the Obstacle-Avoiding Steiner Minimal Tree (OASMT) has received widespread attention. At the same time, with the advancement of VLSI process manufacturing technology, the delay caused by the interconnection line has become more and more obvious, which has greatly exceeded the delay of the component itself and has become the main source of chip delay. Therefore, timing analysis is also indispensable when constructing the Steiner minimum tree. Summary of the invention

[0003] The object of the present invention is to provide a Steiner minimum tree construction method for bypassing obstacle X structure under timing relaxation constraints, which can obtain a routing solution that minimizes line length and worst negative slack (WNS).

[0004] To achieve the above object, the technical solution of the present invention is: a method for constructing a Steiner minimum tree of an obstacle-avoiding X structure under a time relaxation constraint, comprising the following steps:

[0005] Step S1, wiring topology initialization stage: construct X-PDT using PD algorithm and encode it to obtain the initial wiring topology; in addition, generate a wiring edge-obstacle association information table to record the position relationship between the wiring edge and the obstacle;

[0006] Step S2, particle swarm optimization search phase based on genetic operation: the encoded X-PDT is used as the initial position of random particles in the population, the crossover and mutation genetic operations in the genetic algorithm are added to the PSO algorithm to propose a particle swarm optimization algorithm based on genetic operation, and then the particle swarm optimization algorithm based on genetic operation is used for iterative search and update until convergence to the global optimal particle, which is used as the X-structure Steiner wiring tree;

[0007] Step S3, wiring topology normalization stage: for the obstacle-piercing wiring edges that do not meet the design constraints in the X-structure Steiner wiring tree obtained in step S2, the obstacles are successfully bypassed by changing their interconnection line mode or adding obstacle endpoints as pseudo Steiner points; for the wiring edges with negative timing slack values ​​that do not meet the timing constraints, the wiring is removed and rewound, thereby optimizing the local delay; finally, a standardized wiring topology that meets the timing constraints and completely bypasses the obstacles is obtained;

[0008] Step S4, wiring topology optimization stage: the current wiring topology is optimized more finely by optimizing the connection of the interconnection lines, and the optimal wiring topology is selected.

[0009] In one embodiment of the present invention, in step S1, an X-PDT is constructed and encoded using the PD algorithm, that is, a PD tree is constructed and encoded using the PD algorithm based on the X structure to obtain an initial wiring topology that optimizes the line length and radius in a balanced manner.

[0010] In one embodiment of the present invention, in step S1, the encoding method of X-PDT is: firstly, unique digital numbers are set for the pins and obstacles in order, and then the digital string (pqc) is used to encode the pins and obstacles. n-1 f encodes each edge in the PD tree separately, where p represents the number of the predecessor node in the PD tree, q represents the number of the successor node in the PD tree, c represents the interconnection line mode of the corresponding edge, n represents the number of pins, and f represents the fitness value of X-PDT.

[0011] In one embodiment of the present invention, in step S1, the wiring edge-obstacle association information table is generated in the following manner: for each pair of pins p in the wire net i and p j , pre-record the wiring edges generated by four interconnection lines ij The set of obstacles to be crossed O ijc , these information constitute the final wiring edge-obstacle association information table.

[0012] In one embodiment of the present invention, in step S2, the fitness function of the particle swarm optimization algorithm based on genetic operation is:

[0013]

[0014] Indicates the i-th particle in the t-th iteration The fitness function of particles WL and maxPL are The function of the line length and radius; α is an adaptive balance factor that increases linearly with the number of iterations, thereby weighing the value of the line length and radius; in the tth round of iteration, α is defined as:

[0015]

[0016] Among them, α s , α e Represent the initial and final α values ​​respectively, and iteration represents the number of iterations;

[0017] When calculating the line length of the X-structure wiring tree, if the wiring edge does not pass through any obstacle, that is, the non-obstruction wiring edge, or the wiring edge passes through the obstacle but can be changed by changing its interconnection line to bypass the obstacle, that is, the simple obstacle wiring edge, then the line length is calculated by the following formula for the interconnection line length of each pair of pins:

[0018]

[0019] Each pin p i Corresponding to a two-dimensional coordinate (x i ,y i ), respectively represent the horizontal and vertical coordinates of the pins, c is the interconnection line mode, including interconnection modes 0-3;

[0020] When calculating the wire length of the X-structure wiring tree, if the wiring edge e mn The complex obstacle-piercing routing edge is a routing edge that passes through an obstacle and cannot be bypassed by changing its interconnection method. The obstacle endpoint needs to be selected as a pseudo-Steiner point to bypass the obstacle. The length of the interconnection line between the pin and the obstacle endpoint needs to be calculated segmentally. In addition, the length of the common edge in the routing tree, WL, needs to be calculated. co , finally, the line length of the particle is:

[0021]

[0022] When calculating the radius of the X-structure wiring tree, we also need to consider three types of obstacle-avoiding wiring edges. First, we find all the leaf nodes of the wiring tree, and then calculate the length of each interconnection line on the path from the source point to each leaf node. The radius of the particle is:

[0023]

[0024] in, Represents particles The set of all leaf nodes of path(p0,p k ) represents the distance from the source point p0 to a sink point p i The collection of interconnect lines passed through.

[0025] In one embodiment of the present invention, in step S2, the i-th particle in the t-th iteration is updated by iterative search using a particle swarm optimization algorithm based on genetic operations. The update formula is defined as:

[0026]

[0027] That is, update according to the following three parts:

[0028] (1) The inertia retention part, that is, the previous velocity of the particle, represents the particle's search ability. The updated particle is defined as:

[0029]

[0030] Among them, M represents the mutation operation, the inertia weight w represents the probability of particle mutation, and r1 is a random number between 0 and 1;

[0031] (2) The self-cognition part, that is, the distance between the current position of the particle and the individual extreme value, represents the particle's own learning. The updated particle is defined as:

[0032]

[0033] Among them, C represents the crossover operation, the learning factor c1 represents the probability of the particle crossing with the individual extreme value, and r2 is a random number between 0 and 1;

[0034] (3) The social experience part, i.e., the distance between the current position of the particle and the global extreme value, represents the collaboration and information sharing between particles. The updated particle is defined as:

[0035]

[0036] Among them, the learning factor c2 represents the probability of the particle crossing the global extreme value, and r3 is a random number between 0 and 1;

[0037] The inertia weight w and the learning factors c1 and x2 have a great influence on the search and update process. A larger w makes particles more likely to mutate, that is, they have better global search capabilities and are not easily trapped in the local optimum. A smaller w makes particles more likely to stay in the current local area for a more refined search, so that the algorithm converges faster. An overly large c1 causes particles to search excessively in the local area, while an overly large c2 causes the algorithm to converge prematurely. Therefore, in order to consider the parameter trade-off and make the search and update process converge to the global optimal solution faster, based on the time-varying acceleration factor strategy and the linear adjustment parameter strategy, w, c1, and c2 are adaptively adjusted according to the number of iterations. The adjustment formula is as follows:

[0038]

[0039]

[0040]

[0041] Among them, w s , w e Represent the initial and final w values, c 1s , c 1e Represent the initial and final c1 values, c 2s , c 2e represent the initial and final c2 values ​​respectively.

[0042] In one embodiment of the present invention, step S3 is specifically implemented as follows:

[0043] Design Standardization:

[0044] Traverse each wiring edge and determine whether it passes through an obstacle through the wiring edge-obstacle association information table; for pin p i , p j The wiring edge between ij If it is a simple obstacle-penetrating routing edge, and the interconnection line mode 0 or 1 can make it bypass the obstacle, then adjust its interconnection line mode; otherwise, delete this routing edge and process it in the same way as the complex obstacle-penetrating routing edge; if it is a complex obstacle-penetrating routing edge, the obstacle set O that it passes through is calculated based on the Manhattan distance from the starting pin to the midpoint of the obstacle. ijc Sort in non-decreasing order; by p i Take f as the starting point, and perform bypass operations on the sorted obstacle set in turn: select the closest straight line fp among the current obstacles jThe endpoint of fs is added as a pseudo Steiner point s, the edge obstacle information of fs is calculated and added to the wiring edge-obstacle association information table. At the same time, fs is connected according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3; s is used as the starting point to continue the detour operation of the next obstacle until all obstacles are detoured; finally, fp is calculated j The edge barrier information is added to the wiring edge-obstacle association information table. At the same time, according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3, fp is connected. j ;

[0045] Timing Normalization:

[0046] There are some sinks in the routing topology with negative timing slack values. These key sinks violate the timing constraints. Similarly, the key paths they are on also violate the timing constraints. For these routing edges, wire removal and rewinding are performed to reduce local delays so that they can meet the timing slack constraints as much as possible. First, find the paths that do not meet the timing constraints in the routing topology and remove the routing edges where the leaf nodes of the paths are located. Then connect the first sink and leaf node on the path, recalculate the delay of the routing edge from the sink to the leaf node, and the timing slack value of each pin on the path. If the delay is optimized, update the routing topology and record the new delay and line length.

[0047] In one embodiment of the present invention, the specific implementation of step S4 is as follows: the wiring after the wiring topology normalization in step S3 is further globally optimized based on the common edge sharing method, so as to obtain an optimal wiring topology for solving the problem model; since the topological structure of the multi-degree (>2) pin can be decomposed into the topological structures of multiple two-degree pins, for a two-degree pin, since each wiring edge has four interconnection line modes, the pin has a total of 4 2 = 16 topological structures; first traverse all routing edges, calculate the degree of each pin, and record all pins connected to the pin. i If the degree is d, then list the pins p i All 4 d The topology structure is selected, and the topology structure with the smallest line length and delay and bypassing obstacles is selected as the optimal topology structure; secondly, the common edge length of each topology structure is calculated, and all pins are sorted in descending order according to the common edge length; finally, the original topology structure of each pin in the sorted pin set is replaced with its optimal topology structure in turn, and the final wiring topology structure is obtained.

[0048] Compared with the prior art, the present invention has the following beneficial effects: the present invention can obtain a wiring solution that minimizes line length and worst negative slack (WNS). BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Interconnect lines model resistor-capacitor circuits.

[0050] Figure 2 Four interconnection line methods.

[0051] Figure 3 Mutation operation.

[0052] Figure 4 Crossover operation. DETAILED DESCRIPTION

[0053] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0054] The present invention provides a Steiner minimum tree construction method for bypassing obstacle X structure under time sequence relaxation constraint, which specifically includes the following steps:

[0055] 1. Routing topology initialization stage: Use the PD algorithm to construct X-PDT and encode it to obtain the initial routing topology. In addition, a routing edge-obstacle association information table is generated to record the positional relationship between the routing edge and the obstacle, providing information for the subsequent stages of the algorithm.

[0056] 2. Particle swarm optimization search phase based on genetic operations: The encoded X-PDT is used as the initial position of random particles in the population, and the crossover and mutation genetic operations in the genetic algorithm are added to the PSO algorithm to propose a particle swarm optimization algorithm based on genetic operations. Then, based on the algorithm, iterative search and update are performed until convergence to the global optimal particle, which is used as the X-structure Steiner wiring tree.

[0057] 3. Routing topology normalization stage: For the obstacle-piercing routing edges that do not meet the design constraints in the X-structure Steiner routing tree obtained in the previous stage, the obstacles are successfully bypassed by changing their interconnection lines or adding obstacle endpoints as pseudo Steiner points. For the routing edges with negative timing slack values ​​that do not meet the timing constraints, the wires are removed and rewound to optimize the local delay. Finally, a standardized routing topology that meets the timing constraints and completely bypasses obstacles is obtained.

[0058] 4. Wiring topology optimization stage: By optimizing the connection of interconnect lines, the current wiring topology is optimized more finely and the optimal wiring topology is selected.

[0059] The following is the specific implementation process of the present invention.

[0060] 1. Latency:

[0061] The present invention uses the Elmore delay model to model the delay of the interconnection line. Figure 1As shown in the Elmore delay model, the interconnection line is regarded as a uniformly distributed resistance and capacitance line, and is modeled as a π-type resistance and capacitance circuit, with half of the capacitance on the line located at the upstream node and the other half of the capacitance on the line located at the downstream node. ij The delay can be expressed as:

[0062]

[0063] Among them, r0 and c0 represent the resistance and capacitance of the unit line respectively, l eij Represents the interconnected line segment e ij The line length, C down (p j ) indicates pin p j The downstream capacitance can be calculated using the following formula:

[0064] Among them, c pj Indicates p j The capacitance at succ(p j ) indicates pin p j The set of successor nodes.

[0065] 2. Timing relaxation:

[0066] The actual arrival time (AAT) is the time at which a given pin p i The latest transition time of the signal at pin p i The AAT can be expressed as

[0067] AAT(p i )=AAT(p j )+delay(e ij )

[0068] Among them, p j For pin p i For predecessor nodes connected by directed edges, the AAT of the source node is 0.

[0069] The required arrival time (RAT) indicates the time required to reach a certain pin p within a certain clock cycle to ensure the normal operation of the circuit. i The latest time at which the signal must transition. i The RAT can be expressed as

[0070]

[0071] Where suc(p i ) for all pins p iA set of successor nodes connected by directed edges. The RAT of a leaf node is specified by the user.

[0072] Then a pin p i The timing relaxation can be defined as

[0073] slack(p i )=RAT(p i )-AAT(p i )

[0074] The maximum path delay requires that the AAT of each pin cannot exceed the RAT, that is, all pins need to meet the AAT (p i )≤RAT(p i ). Relaxation can accurately determine the pin p i Check whether the timing constraints meet the requirements.

[0075] A sink with a negative slack value is called a critical sink (CS), and the path connected by the critical sink is called the critical path. The worst negative slack is the minimum value of the negative slack values ​​of all sinks except the source, which can be defined as

[0076]

[0077] 3.X-PDT structure:

[0078] If only the line length is considered, some paths may be too long, resulting in excessive delay of this path, and then the sink on this path has a negative timing relaxation value, that is, the timing constraint is not satisfied. If only the radius is considered, the line length of the entire wiring topology may be too long, and the delay of the entire wire network will also be aggravated, increasing the probability that the entire wiring topology violates the timing constraint. As a method for effectively constructing a wiring topology that balances the minimum line length and the shortest radius, the PD algorithm has been applied to many electronic design automation tools and advanced semiconductor design methods. Therefore, the present invention uses a PD algorithm that compromises line length and radius to construct an initial PD wiring tree. The PD algorithm optimizes the two conflicting goals of line length and radius in a balanced manner by combining the traditional Prim and Dijkstra spanning tree algorithms, thereby achieving simultaneous optimization of local delay and global delay. In addition, the construction of the PDT in the present invention is based on the X structure, which makes full use of the wiring space resources and further comprehensively optimizes the line length and radius.

[0079] 4.X-PDT encoding:

[0080] Definition 1: Interconnection line mode. Under the X structure, the connection mode c of the interconnection line is divided into the following four types:

[0081] Definition 1.1 Interconnection method 0. First, connect the starting pin and the pseudo-Steiner point through a horizontal or vertical edge, and then connect the pseudo-Steiner point and the ending pin through a 45° or 135° edge.

[0082] Figure 2 In it, p1(x1, y1) and p2(x2, y2) are the starting pin and the ending pin of an edge respectively, where x1 < x2. As Figure 2 (a) shows, the pin p1 is connected to the pseudo-Steiner point s through a horizontal edge, and then the point s is connected to the pin p2 through a 45° edge.

[0083] Definition 1.2 Interconnection method 1. First, connect the starting pin and the pseudo-Steiner point through a 45° or 135° edge, and then connect the pseudo-Steiner point and the ending pin through a horizontal or vertical edge.

[0084] As Figure 2 (b) shows, the pin p1 is connected to the pseudo-Steiner point s through a 45° edge, and then the point s is connected to the pin p2 through a horizontal edge.

[0085] Definition 1.3 Interconnection method 2. First, connect the starting pin and the pseudo-Steiner point through a vertical edge, and then connect the pseudo-Steiner point and the ending pin through a horizontal edge.

[0086] As Figure 2 (c) shows, the pin p1 is connected to the pseudo-Steiner point s through a vertical edge, and then the point s is connected to the pin p2 through a horizontal edge.

[0087] Definition 1.4 Interconnection method 3. First, connect the starting pin and the pseudo-Steiner point through a horizontal edge, and then connect the pseudo-Steiner point and the ending pin through a vertical edge.

[0088] As Figure 2 (d) shows, the pin p1 is connected to the pseudo-Steiner point s through a horizontal edge, and then the point s is connected to the pin p2 through a vertical edge.

[0089] The present invention designs an X-PDT coding scheme. First, set unique digital numbers for pins and obstacles in sequence, and then use the digital string (pqc) n-1 f to encode each edge in the tree respectively. Among them, p represents the number of the predecessor node in the tree, q represents the number of the successor node in the tree, c represents the interconnection method of this edge, n represents the number of pins, and f represents the fitness value of X-PDT.

[0090] 5. Generation of wiring edge-obstacle association information table:

[0091] The present invention needs to use the information about the wiring edge and the obstacle many times, and the repeated calculation of this information greatly increases the amount of calculation of the algorithm. In order to improve the efficiency of the algorithm, the present invention pre-generates a wiring edge-obstacle association information table to record the positional relationship between the wiring edge and the obstacle, thus avoiding a large amount of repeated calculation of such information in the subsequent stages. i and p j , pre-record the wiring edges generated by four interconnection lines ij The set of obstacles to be crossed O ijc , these information constitute the final wiring edge-obstacle association information table.

[0092] 6. Population initialization:

[0093] The PSO algorithm is an algorithm based on population search, and each particle in the population represents a potential solution to the problem. Therefore, the present invention initializes a group of random particles and then iteratively searches for the optimal solution to the problem. The present invention uses the encoded XPDT set as the initial position of all particles in the PSO, and initializes the historical best position of each particle and the current best position of the entire population. At the same time, a series of parameters such as the population size, number of iterations, inertia weight, and learning factor of the PSO algorithm are initialized.

[0094] 7. PSO search based on genetic operation:

[0095] The PSO algorithm searches for the optimal solution to the problem through the simple behavior of the particles themselves and the information interaction of the population. It is an algorithm for solving continuous optimization problems. The genetic algorithm uses the encoding set of parameters as the operation object, and can effectively solve discrete optimization problems through core genetic operations such as mutation and crossover operations. By combining it with the PSO algorithm and introducing the idea of ​​union and search, the present invention proposes a particle swarm optimization algorithm based on genetic operations. The particle swarm optimization algorithm based on genetic operations has a stronger global search capability and can effectively solve the discrete problem of constructing the Steiner minimum tree of the obstacle-avoiding X structure under the time relaxation constraint.

[0096] 8. Mutation operation:

[0097] The principle of mutation operation on wiring tree is as follows Figure 3 As shown in the figure. After randomly selecting an edge in the tree and deleting it, a union-find operation is introduced to divide the tree nodes after deleting the edge into two point sets. Then, a point is randomly selected from each of the two point sets, and the two points are connected to form a new edge, and finally a new wiring tree is constructed. The mutation operation increases the randomness and global search capability of the algorithm by changing the interconnection lines between pins.

[0098] 9. Crossover operation:

[0099] The principle of crossover operation on the wiring tree is as follows Figure 4 As shown. According to the pin numbers in the two wiring trees, the edges in the two trees are compared in turn, and the union-find operation is introduced. The same edges in the two trees are added to one edge set, and the remaining edges are added to another edge set. The edges in the same edge set are directly used as the edges of the new wiring tree. Then, edges are randomly selected from the remaining edge sets and added to the new wiring tree until a new wiring tree is constructed.

[0100] 10. Fitness function design:

[0101] The main optimization goal of the OAXSMT-SC problem is to minimize the wiring line length and the delay of the interconnection line to meet the timing constraints. Since the line length is proportional to the delay, a radius that is too long will cause the delay of the local path to be too large, causing the local wiring topology to obtain a negative timing relaxation value, violating the timing constraints; a line length that is too long will cause the delay of the global wiring topology to be too large, causing the global wiring topology to obtain a negative timing relaxation value, violating the timing constraints. Therefore, the present invention uses line length and radius as optimization goals to reflect global delay and local delay, thereby minimizing line length and delay. In the tth iteration, the i-th particle The fitness function is defined as

[0102]

[0103] Among them, WL and maxPL are the α is a function of the line length and radius. α is an adaptive balance factor that increases linearly with the number of iterations, thereby weighing the value of the line length and radius. In the tth iteration, α is defined as:

[0104]

[0105] Among them, α s , α e Represent the initial and final α values ​​respectively, and iteration represents the number of iterations.

[0106] When calculating the wire length of an X-structured wiring tree, three types of wiring edges need to be considered, defined as follows:

[0107] Definition 2: Obstacle-free wiring edge. A wiring edge that does not pass through any obstacle.

[0108] Definition 3: Simple obstacle-penetrating routing edge. A routing edge that passes through an obstacle but can be made to bypass the obstacle by changing its interconnection pattern.

[0109] Definition 4: Complex obstacle-penetrating routing edge: A routing edge that passes through an obstacle and cannot be bypassed by changing its interconnection pattern.

[0110] For non-barrier routing edges and simple barrier routing edges, the line lengths of the interconnection lines of each pair of pins are calculated using the following formulas.

[0111]

[0112] Where c is the interconnection line mode.

[0113] For complex obstacle-piercing wiring edges, the present invention proposes a design normalization strategy, which selects the obstacle endpoint as a pseudo-Steiner point to bypass the obstacle. Therefore, it is necessary to calculate the length of the interconnection line between the pin and the obstacle endpoint in segments. In addition, it is also necessary to calculate the length of the common edge in the wiring tree WL co Finally, the line length of the particle is

[0114]

[0115] When calculating the radius of the X-structure wiring tree, we also need to consider the three types of obstacle-avoiding wiring edges. First, find all the leaf nodes of the wiring tree, and then calculate the length of each interconnection line on the path from the source point to each leaf node. The radius of the particle is

[0116]

[0117] in, Represents particles The set of all leaf nodes.

[0118] 11. Search for updates:

[0119] Each particle in the population has a speed that determines its search direction and distance, as well as a fitness value determined by the optimization function, and based on this, it iteratively searches for the optimal solution in the solution space. In each round of iterative search, the particle completes its own update by following two extreme values: one is the particle's own historical best position, called the individual extreme value; the other is the current best position of the entire population, called the global extreme value. The update formula is defined as:

[0120]

[0121] That is, update according to the following three parts:

[0122] (1) The inertia retention part, that is, the previous velocity of the particle, represents the particle's search ability. The updated particle is defined as:

[0123]

[0124] Among them, M represents the mutation operation, the inertia weight w represents the probability of particle mutation, and r1 is a random number between 0 and 1.

[0125] (2) The self-cognition part, that is, the distance between the current position of the particle and the individual extreme value, represents the particle's own learning. The updated particle is defined as:

[0126]

[0127] Among them, C represents the crossover operation, the learning factor c1 represents the probability of the particle crossing with the individual extreme value, and r2 is a random number between 0 and 1.

[0128] (3) The social experience part, that is, the distance between the current position of the particle and the global extreme value, represents the collaboration and information sharing between particles. The updated particle is defined as:

[0129]

[0130] Among them, the learning factor c2 represents the probability of the particle crossing the global extreme value, and r3 is a random number between 0 and 1.

[0131] The inertia weight w and the learning factors c1 and c2 have a great influence on the search and update process. A larger w makes particles more likely to mutate, that is, they have better global search capabilities and are not easily trapped in local optimality; while a smaller w makes particles more likely to stay in the current local area for a more refined search, allowing the algorithm to converge faster. An excessively large c1 causes particles to over-search in the local area, while an excessively large c2 causes the algorithm to converge prematurely. Therefore, in order to consider the parameter trade-offs and make the search and update process converge to the global optimal solution faster, the present invention is based on a time-varying acceleration factor strategy and a linear adjustment parameter strategy, and adaptively adjusts w, c1, and c2 according to the number of iterations. The adjustment formula is as follows:

[0132]

[0133]

[0134]

[0135] Among them, w s , w e Represent the initial and final w values, c 1s , c 1e Represent the initial and final c1 values, c 2s , c 2e represent the initial and final c2 values ​​respectively.

[0136] 12. Design standardization:

[0137] After the PSO search is completed, the final population global optimal particle is used as the X-structure Steiner wiring tree. At this time, the wiring topology has three wiring edges defined by Definitions 2-4. For the two obstacle-penetrating wiring edges that do not meet the design constraints, the present invention proposes a design normalization strategy to adjust them so that they can bypass obstacles.

[0138] This strategy traverses each routing edge and determines whether it passes through an obstacle through the routing edge-obstacle association information table. i , p j The wiring edge between ij If it is a simple obstacle-piercing routing edge, and the interconnection mode 0 or 1 can make it bypass the obstacle, then adjust its interconnection mode. Otherwise, delete this routing edge and process it in the same way as the complex obstacle-piercing routing edge. If it is a complex obstacle-piercing routing edge, the obstacle set O that it passes through is calculated based on the Manhattan distance from the starting pin to the midpoint of the obstacle. ijc Sort in non-decreasing order. i Take f as the starting point, and perform bypass operations on the sorted obstacle set in turn: select the closest straight line fp among the current obstacles j The endpoint of fs is added as a pseudo Steiner point s, the edge obstacle information of fs is calculated and added to the routing edge-obstacle association information table. At the same time, fs is connected according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3. s is used as the starting point to continue the detour operation of the next obstacle until all obstacles are detoured. Finally, fp is calculated j The edge barrier information is added to the wiring edge-obstacle association information table. At the same time, according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3, fp is connected. j .

[0139] 13. Timing Normalization:

[0140] There are some sinks in the routing topology that have negative timing slack values, that is, their AAT exceeds RAT. These key sinks violate the timing constraints, and similarly, the critical paths where they are located also violate the timing constraints. For these routing edges, the present invention proposes a timing normalization strategy, which removes and rewinds them to reduce local delays so that they can meet the timing slack constraints as much as possible. First, find the path that does not meet the timing constraints in the routing topology, and remove the routing edges where the leaf nodes of the path are located. Then connect the first sink on the path with the leaf node, and recalculate the delay of the routing edge from the sink to the leaf node, as well as the timing slack value of each pin on the path. If the delay is optimized, update the routing topology and record the new delay and line length. This strategy mainly optimizes the delay of the critical path by reducing the radius, thereby optimizing the timing slack value of the critical sink, so that the critical path meets the timing constraints as much as possible.

[0141] 14. Wiring topology optimization:

[0142] During the wiring topology normalization phase, the wiring topology is optimized locally in many places to satisfy the design constraints and timing constraints under the OAXSMT-SC problem model. However, some wiring edges can still be further optimized, and any wiring edge has at least one optimal topology. At this stage, the present invention designs a method based on common edge sharing to globally optimize the normalized wiring topology, thereby obtaining an optimal wiring topology for solving the problem model. Since the topological structure of multi-degree (>2) pins can be decomposed into the topological structures of multiple two-degree pins, the present invention only discusses two-degree pins. For a two-degree pin, since each wiring edge has four interconnection line modes, the pin has a total of 4 2 = 16 topological structures. This strategy first traverses all routing edges, calculates the degree of each pin, and records all pins connected to the pin. i If the degree is d, then list the pins p i All 4 d The topology with the smallest line length and delay and bypassing obstacles is selected as the optimal topology. Secondly, the common edge length of each topology is calculated, and all pins are sorted in descending order according to the common edge length. Finally, the original topology of each pin in the sorted pin set is replaced with its optimal topology in turn. At this point, the final routing topology that solves the OAXSMT-SC problem is obtained.

[0143] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

Claims

1. A method for constructing Steiner minimum tree of obstacle-avoiding X structure under time relaxation constraint, characterized in that: The steps include: Step S1, wiring topology initialization stage: construct X-PDT using PD algorithm and encode it to obtain the initial wiring topology; in addition, generate a wiring edge-obstacle association information table to record the position relationship between the wiring edge and the obstacle; Step S2, particle swarm optimization search phase based on genetic operation: the encoded X-PDT is used as the initial position of random particles in the population, the crossover and mutation genetic operations in the genetic algorithm are added to the PSO algorithm to propose a particle swarm optimization algorithm based on genetic operation, and then the particle swarm optimization algorithm based on genetic operation is used for iterative search and update until convergence to the global optimal particle, which is used as the X-structure Steiner wiring tree; Step S3, wiring topology normalization stage: for the obstacle-piercing wiring edges that do not meet the design constraints in the X-structure Steiner wiring tree obtained in step S2, the obstacles are successfully bypassed by changing their interconnection line mode or adding obstacle endpoints as pseudo Steiner points; for the wiring edges with negative timing slack values ​​that do not meet the timing constraints, the wiring is removed and rewound, thereby optimizing the local delay; finally, a standardized wiring topology that meets the timing constraints and completely bypasses the obstacles is obtained; Step S4, wiring topology optimization stage: optimizing the current wiring topology more finely by optimizing the connection of the interconnection lines, and selecting the optimal wiring topology; In step S1, the encoding method of X-PDT is: first, unique digital numbers are set for the pins and obstacles in order, and then the digital string (pqc) is used. n-1 f encodes each edge in the PD tree, where p represents the number of the predecessor node in the PD tree, q represents the number of the successor node in the PD tree, c represents the interconnection line mode of the corresponding edge, n represents the number of pins, and f represents the fitness value of X-PDT; In step S2, the fitness function of the particle swarm optimization algorithm based on genetic operation is: Fitness(P i t )=(1-α t )×WL(P i t )+α t ×maxPL(P i t ) Fitness(P i t ) represents the i-th particle in the t-th iteration The fitness function of particles WL and maxPL are The function of the line length and radius; α is an adaptive balance factor that increases linearly with the number of iterations, thereby weighing the value of the line length and radius; in the tth round of iteration, α is defined as: Among them, α s , α e Represent the initial and final α values ​​respectively, and iteration represents the number of iterations; When calculating the line length of the X-structure wiring tree, if the wiring edge does not pass through any obstacle, that is, the non-obstruction wiring edge, or the wiring edge passes through the obstacle but can be changed by changing its interconnection line to bypass the obstacle, that is, the simple obstacle wiring edge, then the line length is calculated by the following formula for the interconnection line length of each pair of pins: Each pin p i Corresponding to a two-dimensional coordinate (x i ,y i ), respectively represent the horizontal and vertical coordinates of the pins, c is the interconnection line mode, including interconnection modes 0-3; When calculating the wire length of the X-structure wiring tree, if the wiring edge e mn The complex obstacle-piercing routing edge is a routing edge that passes through an obstacle and cannot be bypassed by changing its interconnection method. The obstacle endpoint needs to be selected as a pseudo-Steiner point to bypass the obstacle. The length of the interconnection line between the pin and the obstacle endpoint needs to be calculated segmentally. In addition, the length of the common edge in the routing tree, WL, needs to be calculated. co , finally, the line length of the particle is: When calculating the radius of the X-structure wiring tree, we also need to consider three types of obstacle-avoiding wiring edges. First, we find all the leaf nodes of the wiring tree, and then calculate the length of each interconnection line on the path from the source point to each leaf node. The radius of the particle is: in, Represents particles The set of all leaf nodes of path(p0,p k ) represents the distance from the source point p0 to a sink point p i the set of interconnects passed through; In step S2, the particle swarm optimization algorithm based on genetic operation is used to iteratively search and update the i-th particle in the t-th iteration. The update formula is defined as: That is, update according to the following three parts: (1) The inertia retention part, that is, the previous velocity of the particle, represents the particle's search ability. The updated particle is defined as: Among them, M represents the mutation operation, the inertia weight w represents the probability of particle mutation, and r1 is a random number between 0 and 1; (2) The self-cognition part, that is, the distance between the current position of the particle and the individual extreme value, represents the particle's own learning. The updated particle is defined as: Among them, C represents the crossover operation, the learning factor c1 represents the probability of the particle crossing with the individual extreme value, and r2 is a random number between 0 and 1; (3) The social experience part, i.e., the distance between the current position of the particle and the global extreme value, represents the collaboration and information sharing between particles. The updated particle is defined as: Among them, the learning factor c2 represents the probability of the particle crossing the global extreme value, and r3 is a random number between 0 and 1; The inertia weight w and the learning factors c1 and c2 have a great influence on the search and update process. A larger w makes particles more likely to mutate, that is, they have better global search capabilities and are not easy to fall into the local optimum. A smaller w makes particles more likely to stay in the current local area for a more refined search, so that the algorithm converges faster. An overly large c1 causes particles to search excessively in the local area, while an overly large c2 causes the algorithm to converge prematurely. Therefore, in order to consider the parameter trade-off and make the search and update process converge to the global optimal solution faster, based on the time-varying acceleration factor strategy and the linear adjustment parameter strategy, w, c1, and c2 are adaptively adjusted according to the number of iterations. The adjustment formula is as follows: Among them, w s , w e Represent the initial and final w values, c 1s , c 1e Represent the initial and final c1 values, c 2s , c 2e represent the initial and final c2 values ​​respectively; The specific implementation of step S3 is as follows: Design Standardization: Traverse each wiring edge and determine whether it passes through an obstacle through the wiring edge-obstacle association information table; for pin p i , p j The wiring edge between ij If it is a simple obstacle-penetrating routing edge, and the interconnection line mode 0 or 1 can make it bypass the obstacle, then adjust its interconnection line mode; otherwise, delete this routing edge and process it in the same way as the complex obstacle-penetrating routing edge; if it is a complex obstacle-penetrating routing edge, the obstacle set O that it passes through is calculated based on the Manhattan distance from the starting pin to the midpoint of the obstacle. ijc Sort in non-decreasing order; by p i Take f as the starting point, and perform bypass operations on the sorted obstacle set in turn: select the closest straight line fp among the current obstacles j The endpoint of fs is added as a pseudo Steiner point s, the edge obstacle information of fs is calculated and added to the wiring edge-obstacle association information table. At the same time, fs is connected according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3; s is used as the starting point to continue the detour operation of the next obstacle until all obstacles are detoured; finally, fp is calculated j The edge barrier information is added to the wiring edge-obstacle association information table. At the same time, according to the rule that interconnection line mode 0 and 1 take precedence over interconnection line mode 2 and 3, fp is connected. j ; Timing Normalization: There are some sinks in the routing topology with negative timing slack values. These key sinks violate the timing constraints. Similarly, the key paths they are on also violate the timing constraints. For these routing edges, wire removal and rewinding are performed to reduce local delays so that they can meet the timing slack constraints as much as possible. First, find the paths that do not meet the timing constraints in the routing topology and remove the routing edges where the leaf nodes of the paths are located. Then connect the first sink and the leaf node on the path, recalculate the delay of the routing edge from the sink to the leaf node, and the timing slack value of each pin on the path. If the delay is optimized, update the routing topology and record the new delay and line length. The specific implementation method of step S4 is: the wiring after the wiring topology normalization in step S3 is further globally optimized based on the common edge sharing method to obtain an optimal wiring topology; since the topological structure of multi-degree pins can be decomposed into the topological structures of multiple two-degree pins, the multi-degree pins refer to pins greater than two degrees. For a two-degree pin, since each wiring edge has four interconnection line modes, the pin has a total of 4 2 = 16 topological structures; first traverse all routing edges, calculate the degree of each pin, and record all pins connected to the pin. i If the degree is d, then list the pins p i All 4 d The topology structure is selected, and the topology structure with the smallest line length and delay and bypassing obstacles is selected as the optimal topology structure; secondly, the common edge length of each topology structure is calculated, and all pins are sorted in descending order according to the common edge length; finally, the original topology structure of each pin in the sorted pin set is replaced with its optimal topology structure in turn, and the final wiring topology structure is obtained.

2. The Steiner minimum tree construction method for avoiding obstacles with X-structure under timing relaxation constraints according to claim 1 is characterized in that: In the step S1, an X-PDT is constructed and encoded using the PD algorithm, that is, a PD tree is constructed and encoded using the PD algorithm based on the X structure to obtain an initial wiring topology that optimizes the line length and radius in a balanced manner.

3. The Steiner minimum tree construction method for avoiding obstacles with X-structure under timing relaxation constraints according to claim 1, characterized in that: In step S1, the wiring edge-obstacle association information table is generated in the following manner: for each pair of pins p in the wire net i and p j , pre-record the wiring edges generated by four interconnection lines ij The set of obstacles to be crossed O ijc , these information constitute the final wiring edge-obstacle association information table.

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