Method of designing a semiconductor chip and computing device for performing the method

Abstract

A method of designing a semiconductor chip and a computing device for performing the same are provided. The method includes acquiring first data including information about an arrangement of a plurality of cells on a semiconductor chip, acquiring second data including information about wiring between the plurality of cells and power and signal lines, and outputting a verification result by detecting an error in the arrangement of the plurality of cells based on matching of the first data and the second data.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2020-0086439, filed on July 13, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The inventive concept relates to a computing device and / or a semiconductor chip design method of a computing device. For example, at least some example embodiments relate to a method of designing an input / output interface of a semiconductor chip. BACKGROUND

[0003] Various semiconductor chips including an integrated circuit or the like include an input / output interface for communicating between a circuit inside the semiconductor chip and a device outside the semiconductor chip. For example, the input / output interface can exchange a control signal, various types of voltage signals, and various types of data between the semiconductor chip and the device outside the semiconductor chip.

[0004] When designing an input / output interface of a semiconductor chip, a designer can directly design an input / output unit to be disposed on the semiconductor chip, and can directly check and verify whether the designed input / output unit is disposed to properly operate. Accordingly, a great amount of time and expense is spent in the design process, and the reliability of the verification process is low. SUMMARY

[0005] The inventive concept provides a method and / or apparatus for detecting a design error on an input / output interface of a semiconductor chip without direct intervention of a designer for a computing device and a semiconductor chip design method thereof.

[0006] According to an aspect of the inventive concept, there is provided a method of designing a semiconductor chip, the method including: obtaining first data indicating an arrangement of a plurality of units on the semiconductor chip; obtaining second data indicating wiring between the plurality of units and power and signal lines including at least one power line and at least one signal line; and outputting a verification result by detecting at least one error in the arrangement of the plurality of units based on the first data and the second data.

[0007] According to another aspect of the inventive concept, there is provided a method of designing a semiconductor chip, the method including: obtaining first data indicating an arrangement of a plurality of cells on a semiconductor chip; obtaining second data including wiring information indicating wiring between the plurality of cells and a power supply and a plurality of pieces of library information corresponding to the plurality of cells; obtaining merged data by merging the wiring information of corresponding cells among the first data and the second data; detecting at least one error among a short error, a floating error, and a different type library error based on the merged data; and outputting a verification result indicating the at least one error.

[0008] According to another aspect of the inventive concept, there is provided a computing device including: at least one processor; and a memory storing instructions that, when executed by the at least one processor, configure the computing device to: obtain first data indicating an arrangement of a plurality of cells on a semiconductor chip; obtain second data indicating wiring between the plurality of cells and power and signal lines including at least one power line and at least one signal line; and output a verification result by detecting at least one error in the arrangement of the plurality of cells based on the first data and the second data.

[0009] According to another aspect of the inventive concept, there is provided a program stored in a non-transitory computer-readable recording medium, the program performing operations in at least one of a plurality of methods. BRIEF DESCRIPTION OF DRAWINGS

[0010] Example embodiments of the inventive concept will become more fully understood from the detailed description given herein below, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a computing device according to an example embodiment of the inventive concept;

[0012] Figure 2 is a view of a semiconductor chip according to an example embodiment of the inventive concept;

[0013] Figure 3 is a flowchart of a semiconductor chip design method according to an example embodiment of the inventive concept;

[0014] Figure 4 is a flowchart of a semiconductor chip design method according to an example embodiment of the inventive concept;

[0015] Figure 5 is a view of first data according to an example embodiment of the inventive concept;

[0016] Figure 6 is a view of second data according to an example embodiment of the inventive concept;

[0017] Figure 7 is a view of merging data according to example embodiments of the inventive concept;

[0018] Figure 8A is a flowchart of a semiconductor chip design method according to example embodiments of the inventive concept;

[0019] Figure 8B is a view of merging data and short error detection according to example embodiments of the inventive concept;

[0020] Figure 8C is a view of merging data according to example embodiments of the inventive concept;

[0021] Figure 9A is a flowchart of a semiconductor chip design method according to example embodiments of the inventive concept;

[0022] Figure 9B is a view of merging data and floating error detection according to example embodiments of the inventive concept;

[0023] Figure 10A is a flowchart of a semiconductor chip design method according to example embodiments of the inventive concept;

[0024] Figure 10B is a view for describing a problem that can occur when input / output units belonging to different type libraries are connected in a single ring;

[0025] Figure 10C is a view of merging data and different type library error detection according to example embodiments of the inventive concept;

[0026] Figure 11A and Figure 11B is a view of a computing device according to example embodiments of the inventive concept; and

[0027] Figure 12 is a view of an input / output unit including a linker unit according to example embodiments of the inventive concept. DETAILED DESCRIPTION

[0028] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0029] Figure 1is a block diagram of a computing device 10 according to example embodiments of the inventive concept. As a non-limiting example, the computing device 10 can be implemented by a smart phone, a tablet personal computer (PC), a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a mobile medical device, a camera, or a wearable device.

[0030] The computing device 10 can include a memory 100 and a processor 200. According to example embodiments of the inventive concept, the computing device 10 can include a single processor 200 or a plurality of processors.

[0031] According to example embodiments of the inventive concept, the computing device 10 can have programs installed therein and operate based on the installed programs. The programs can be stored in a computer-readable recording medium (e.g., in the memory 100).

[0032] The memory 100 is a storage device that stores data, and can store, for example, various algorithms, various programs, and various data. The memory 100 can include at least one of a volatile memory and a non-volatile memory. The non-volatile memory can include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM or FeRAM), etc. The volatile memory can include a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a PRAM, an MRAM, an RRAM, a FeRAM, etc. In addition, according to example embodiments of the inventive concept, the memory 100 can include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF) card, a secure digital (SD) card, a micro-secure digital (micro-SD) card, a mini-secure digital (mini-SD) card, an extreme digital (xD) card, or a memory stick. The memory 100 can semi-permanently or temporarily store algorithms, programs, and a plurality of instructions to be executed by the computing device 10. According to example embodiments of the inventive concept, the memory 100 can store instructions to be executed by the computing device 10 when performing a semiconductor chip design method. That is, the processor 200 can execute at least one instruction stored in the memory 100 so that the computing device 10 performs operations in the semiconductor chip design method according to example embodiments of the inventive concept.

[0033] The processor 200 can control various operations of the computing device 10, and for example, the processor 200 can include a central processing unit (CPU) or an application processor (AP). The processor 200 can include a single core or multiple cores.

[0034] The processor 200 can be implemented using processing circuitry such as hardware including a logic circuit, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuitry can include, without limitation, a CPU, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, or an application specific integrated circuit (ASIC), etc.

[0035] The processing circuitry can be a dedicated processing circuitry configured to detect an error in an arrangement of input / output (I / O) units on a semiconductor chip, and can correct at least one error detected. Accordingly, the processing circuitry can improve the function of the computing device 10 itself.

[0036] The computing device 10 can acquire first data DATA1 and second data DATA2. Here, the first data DATA1 and the second data DATA2 are associated with a semiconductor chip design, wherein the first data DATA1 can include information about an arrangement of a plurality of input / output units on a semiconductor chip, and the second data DATA2 can include information about wiring between the plurality of input / output units and power and signal lines. Here, the power and signal lines are used as a term indicating at least one power line and at least one signal line. That is, an input / output interface of a semiconductor chip according to an example embodiment of the inventive concept can include at least one power line and at least one signal line, wherein the second data DATA2 can include information about wiring between the plurality of input / output units and the power and signal lines including at least one power line and at least one signal line. According to an example embodiment of the inventive concept, the computing device 10 can receive the first data DATA1 and the second data DATA2 from the outside of the computing device 10. According to an example embodiment of the inventive concept, the first data DATA1 and the second data DATA2 can be input by a semiconductor chip designer (for example, a user of the computing device 10). The computing device 10 can detect an error in an arrangement of input / output units on a semiconductor chip based on the first data DATA1 and the second data DATA2, and output a verification result RST by generating the verification result RST based on the detected error.

[0037] According to example embodiments of the inventive concept, the processor 200 can detect an error of the arrangement of the input / output cells on the semiconductor chip based on matching of the first data DATA1 and the second data DATA2. According to example embodiments of the inventive concept, the processor 200 can acquire merged data by merging the wiring information of the corresponding input / output cell among the second data DATA2 for each of the plurality of input / output cells included in the first data DATA1. The processor 200 can detect an error based on the information included in the merged data, the error including at least one of a short error, a floating error, and a different type library error. The processor 200 can generate a verification result RST including information about the detected at least one error, and output the verification result RST to the outside of the computing device 10.

[0038] In addition, according to example embodiments of the inventive concept, the processor 200 can modify the first data DATA1 and / or the second data DATA2 based on the verification result RST. For example, the processor 200 can correct the detected at least one error by modifying the data that needs to be modified in the first data DATA1 and / or the second data DATA2 based on the type and details of the detected at least one error included in the verification result RST.

[0039] In addition, according to example embodiments of the inventive concept, the processor 200 can output error-corrected design data based on the first data DATA1, the second data DATA2, and the verification result RST, wherein the design data can indicate design information to be directly used to manufacture a semiconductor chip according to a user's design. For example, the design data can include specific design data (e.g., chip layout design information) for arranging the input / output cells on the semiconductor chip. In some example embodiments, the processor 200 can control a manufacturing device to manufacture a semiconductor chip based on the error-corrected design data.

[0040] In addition, according to example embodiments of the inventive concept, the processor 200 can generate correction information including information about an error correction method for the first data DATA1 and / or the second data DATA2 based on the type and details of the detected error included in the verification result RST, and output the correction information to the outside of the computing device 10. According to example embodiments of the inventive concept, the processor 200 can display the correction information on a display device (such as a display included in the computing device 10) to a semiconductor chip designer (e.g., a user of the computing device 10). The semiconductor chip designer can correct the arrangement error of the input / output cells based on the correction information, and manufacture a semiconductor chip based on the result of the correction.

[0041] In addition, according to example embodiments of the inventive concept, the computing device 10 can merge the first data DATA1 including information about the arrangement of the plurality of input / output cells on the semiconductor chip and the second data DATA2 including information about the wiring between the plurality of input / output cells and the power and signal lines. Based on the merged data, the computing device 10 can detect at least one error among a short error, a floating error, and a different type library error related to the input / output cell arrangement.

[0042] In addition, the computing device 10 according to example embodiments of the inventive concept can help a user of the computing device 10 to be aware of an error in the semiconductor chip design by outputting the verification result RST including information about the error. Accordingly, even without direct intervention of a designer, a semiconductor chip designer can detect a design error in an input / output interface of a semiconductor chip. As a result, time and expense that would be spent to find a design error in the input / output interface can be saved, and the error can be found more accurately.

[0043] Further, the computing device 10 according to example embodiments of the inventive concept can help a user who is a designer to accurately correct an error by providing an error correction method for the first data DATA1 and / or the second data DATA2 to the user of the computing device 10 based on the verification result RST.

[0044] In addition, the computing device 10 according to example embodiments of the inventive concept can directly correct a design error without intervention of a designer by modifying the first data DATA1 and / or the second data DATA2 based on the verification result RST.

[0045] Figure 2 is a view of a semiconductor chip 1000 according to example embodiments of the inventive concept. Figure 2 A semiconductor chip 1000 manufactured according to a semiconductor chip design method according to example embodiments of the inventive concept can be specifically illustrated. The specific shape, number, etc. of the semiconductor chip 1000 or the input / output interface 1100 are for convenience of description only and are not limited thereto.

[0046] Referring to Figure 2, the semiconductor chip 1000 can include an input / output interface 1100 for receiving power from the outside, for example, receiving data and / or a control signal from the outside, and outputting data to the outside. In addition, according to an example embodiment of the inventive concept, the input / output interface 1100 can generate an operating voltage required for an internal circuit of the semiconductor chip 1000 based on a voltage input from the outside, and supply the operating voltage to the internal circuit of the semiconductor chip 1000. According to an example embodiment of the inventive concept, the input / output interface 1100 can be implemented on the semiconductor chip 1000 in a shape that surrounds the semiconductor chip 1000 to provide an interface between the internal circuit and the outside of the semiconductor chip 1000. In addition, according to an example embodiment of the inventive concept, the input / output interface 1100 can include a plurality of input / output units. The plurality of input / output units can receive a voltage or power through at least one power line and receive a control signal through at least one signal line. Accordingly, a power source should be connected to each of the at least one power line and should supply a control signal to the at least one signal line. The at least one power line and the at least one signal line along the shape in which the input / output units are connected can have a similar shape to the shape in which the input / output units are arranged, and thus have a ring shape that can be referred to as a power line ring and / or a signal line ring.

[0047] For example, the plurality of input / output units included in the input / output interface 1100 can include an input / output unit 1120. The input / output unit 1120 can be connected to the at least one power line through at least one pin of the input / output unit 1120 and to the at least one signal line through the at least one pin. For example, the input / output unit 1120 can be connected to a first signal line SL1, a first power line PL1, and a second power line PL2. The number of power lines and the number of signal lines are merely illustrative and are not limited thereto. The power lines can be lines for delivering various types of driving voltages VDD and VSS or power, and the signal lines can be lines for delivering a control signal. In addition, as described above, the at least one power line and the at least one signal line can be referred to together as power and signal lines. In other words, the power and signal lines can include the at least one power line and the at least one signal line.

[0048] The input / output unit 1120 can provide or receive a control signal to or from another input / output unit through the first signal line SL1. In addition, the input / output unit 1120 can provide or receive a voltage or power to or from another input / output unit through the first power line PL1 and the second power line PL2.

[0049] For example, the first signal line SL1 can be connected to a plurality of input / output units according to the arrangement of the input / output units of the designer, and the units of these connected first signal lines SL1 can be referred to as a signal line ring. Also, the first power line PL1 can be connected to a plurality of input / output units according to the arrangement of the input / output units of the designer, and the units of these connected first power lines PL1 can be referred to as a power line ring.

[0050] A single power line ring defined as described above should include one type of power source for providing a voltage or power. Thus, designing the arrangement of input / output units such that two types of power sources are connected to a single power line ring can cause a short circuit on the power line, resulting in a power line failure. For example, when a power source for providing a voltage VDD and a power source for providing a voltage VSS are connected to a single power line ring, a failure can occur on the corresponding power line due to a short circuit. Likewise, there should be one type of control signal provider for providing a control signal on a signal line ring defined as described above. Thus, designing the arrangement of input / output units such that two types of control signal providers are connected to a single signal line ring can cause a short circuit on the signal line, resulting in a signal line failure. These two cases are referred to as short circuit error related to the arrangement of input / output units.

[0051] Also, likewise, not connecting a power source to a single power line ring can cause the power line to float, hindering the normal operation of the input / output units. This case is referred to as floating error related to the arrangement of input / output units.

[0052] Also, according to example embodiments of the inventive concept, as referred to above Figure 10B More specifically, when input / output units belonging to different banks (or categories) are connected to a single power line ring or a single signal line ring, the wiring of the input / output units can not be performed completely due to a mismatch between the pins of adjacent input / output units. Thus, connecting two input / output units belonging to different banks to a single power line ring or a single signal line ring is referred to as a different type bank error (or, alternatively, a mismatch error).

[0053] According to example embodiments, in the operation of designing the arrangement of input / output units on a semiconductor chip 1000, short circuit error, floating error, and different type bank error are detectable.

[0054] Figure 3 is a flowchart of a semiconductor chip design method according to example embodiments of the inventive concept. Reference will be made together to Figure 1 Described Figure 3 .

[0055] Reference Figure 1 and Figure 3In operation S120, the computing device 10 can acquire first data DATA1 including information about arrangement of a plurality of input / output cells on a chip. According to an example embodiment of the inventive concept, the first data DATA1 can include information about a plurality of input / output cells corresponding to a plurality of pin names on a semiconductor chip. Here, according to an example embodiment of the inventive concept, the pin name can indicate information about a location where the input / output cell is located on the semiconductor chip. According to an example embodiment of the inventive concept, the first data DATA1 can be referred to as a pin file and set or provided by a designer. Reference can be made to Figure 5 Example embodiments of the first data DATA1 are described in more detail.

[0056] In operation S140, the computing device 10 can acquire second data DATA2 including information about wiring between the plurality of input / output cells and power and signal lines. According to an example embodiment of the inventive concept, the second data DATA2 can include a matrix including a plurality of rows corresponding to a plurality of input / output cells and a plurality of columns corresponding to a plurality of power and signal lines, and each element of the matrix can include data indicating whether an input / output cell corresponding to a row is connected to a power line or a signal line corresponding to a column, or indicating a type of a power source or a control signal supplied to the corresponding input / output cell or the corresponding power line or signal line. According to an example embodiment of the inventive concept, the second data DATA2 can be provided by a designer. Reference can be made to Figure 6 and Figure 11A Example embodiments of the second data DATA2 are described in more detail.

[0057] In operation S160, the computing device 10 can output a verification result RST by detecting an error of the input / output cell arrangement based on the first data DATA1 and the second data DATA2 (e.g., by matching of the first data DATA1 and the second data DATA2). For example, the computing device 10 can generate merged data by matching (or merging) the first data DATA1 and the second data DATA2, and detect at least one error among a short error, a floating error, and a different type library error based on the merged data. The computing device 10 can generate the verification result RST including information about the detected at least one error, and output the verification result RST. Reference can be made to Figure 4 Operation S160 is described in more detail.

[0058] According to example embodiments of the inventive concept, the computing device 10 can merge first data DATA1 including information about an arrangement of a plurality of input / output cells on a semiconductor chip and second data DATA2 including information about wiring between the plurality of input / output cells and power and signal lines, and detect at least one error among a short error, a floating error, and a different type library error related to the input / output cell arrangement based on the merged data.

[0059] In addition, the computing device 10 according to example embodiments of the inventive concept can help a user of the computing device 10 to be aware of an error in a semiconductor chip design by outputting a verification result RST including information about the error. Thus, a semiconductor chip designer can detect a design error in an input / output interface of a semiconductor chip even without direct intervention of the designer. Accordingly, time and expense that would be spent to find a design error in the input / output interface can be saved, and the error can be found more accurately.

[0060] Further, the computing device 10 according to example embodiments of the inventive concept can help a user who is a designer to accurately correct an error by providing the user with an error correction method for the first data DATA1 and / or the second data DATA2 based on the verification result RST.

[0061] In addition, the computing device 10 according to example embodiments of the inventive concept can directly correct a design error without intervention of a designer by modifying the first data DATA1 and / or the second data DATA2 based on the verification result RST.

[0062] Accordingly, the processor 200 can be a dedicated processor that improves a function of the computing device 10 itself by automatically correcting a design error in a semiconductor chip design.

[0063] Figure 4 is a flowchart of a semiconductor chip design method according to example embodiments of the inventive concept. Specifically, Figure 4 A detailed flowchart of operation S160 of Figure 3 may be shown. Reference will be made to Figure 1 descriptions Figure 4 .

[0064] Reference will be made to Figure 1 and Figure 4In operation S162, the computing device 10 can acquire merged data by merging the wiring information of the corresponding input / output unit among the second data DATA2 for each of the plurality of input / output units included in the first data DATA1. For example, the computing device 10 can acquire the merged data by merging the rows corresponding to the input / output units included in the matrix in the second data DATA2 for each of the plurality of input / output units included in the first data DATA1.

[0065] In operation S164, the computing device 10 can detect at least one error among a short-circuit error, a floating error, and a different type library error based on the merged data. The method of detecting the short-circuit error will be described in greater detail below with reference to Figure 8A to Figure 8C The method of detecting the short-circuit error will be described in greater detail below with reference to Figure 9A and Figure 9B The method of detecting the floating error will be described in greater detail below with reference to Figure 10A to Figure 10C The method of detecting the different type library error will be described in greater detail below.

[0066] In operation S166, the computing device 10 can output a verification result RST including information about the detected at least one error. For example, the verification result RST can include the type and details of the at least one error detected in operation S164, and the details of the at least one error can include information about a power line loop or a signal line loop and / or the name of the input / output unit on which the at least one error occurred.

[0067] According to example embodiments of the inventive concept, the computing device 10 can correct at least one data among the first data DATA1 and the second data DATA2 that needs to be corrected based on the type and details of the at least one error included in the verification result RST. In addition, according to example embodiments of the inventive concept, the computing device 10 can provide the user of the computing device 10 with an error correction method based on the type and details of the at least one error included in the verification result RST. In other words, according to example embodiments of the inventive concept, the computing device 10 can guide the method of correcting the error that occurred based on the verification result RST.

[0068] Figure 5 is a view of the first data DATA1 according to example embodiments of the inventive concept. For ease of description, Figure 5 The specific details of the first data DATA1 shown in

[0069] Referring to Figure 5 , the first data DATA1 can include information about the arrangement of the plurality of input / output units on the chip. For example, the first data DATA1 can include information about the plurality of input / output units corresponding to the pin names on the semiconductor chip.

[0070] For example, according to induction, the first data DATA1 can include information about the first input / output unit CELL_1 being arranged to correspond to the first pin PIN_1, the second input / output unit CELL_2 being arranged to correspond to the second pin PIN_2, and likewise, the k-th input / output unit CELL_k being arranged to correspond to the k-th pin PIN_k (k is a natural number greater than or equal to 2).

[0071] According to an example embodiment of the inventive concept, the first data DATA1 can include information about a plurality of input / output units corresponding to a plurality of pin names in a matrix form.

[0072] Figure 6 is a view of second data DATA2 according to an example embodiment of the inventive concept. For ease of description, Figure 6 The specific details of the second data DATA2 shown in

[0073] Referring to Figure 6 , the second data DATA2 can include information about wiring between a plurality of input / output units and a plurality of power and signal lines. For example, the second data DATA2 can include a matrix including a plurality of rows corresponding to a plurality of input / output units (e.g., the first input / output unit CELL_1 to the k-th input / output unit CELL_k) and a plurality of columns corresponding to a plurality of power and signal lines (e.g., the first power and signal line PSL1 to the m-th power and signal line PSLm) (k and m are each a natural number greater than or equal to 2, and are independent of each other). Here, the power and signal lines PSL1, …, PSLm can include at least one power line and at least one signal line. Here, each element of the matrix can include data indicating whether an input / output unit corresponding to a row is connected to or disconnected from a power line or a signal line corresponding to a column, whether the corresponding power line or signal line is not present, or a type of power or control signal supplied to the corresponding input / output unit.

[0074] Referring to Figure 6The first input / output unit CELL_1, the second input / output unit CELL_2, and the k-th input / output unit CELL_k can be connected to the first power and signal line PSL1. The first input / output unit CELL_1 and the k-th input / output unit CELL_k can be disconnected from the second power and signal line PSL2, and the second input / output unit CELL_2 can supply the power VDD to the second power and signal line PSL2. In addition, there can be no pin corresponding to the m-th power and signal line PSLm for the first input / output unit CELL_1, and the second input / output unit CELL_2 and the k-th input / output unit CELL_k can be connected to the m-th power and signal line PSLm. Figure 7 is a view of merged data DATA_M according to an example embodiment of the inventive concept. For ease of description, Figure 7 particular details of the merged data DATA_M shown in Figure 7 may show merged data DATA_M generated by merging Figure 5 the first data DATA1 and Figure 6 the second data DATA2.

[0075] Although Figure 5 and Figure 6 show a plurality of input / output units arranged in the same order in each of the first data DATA1 and the second data DATA2, and this is only for ease of description, in an actual situation, the order of the plurality of input / output units included in the column of the second data DATA2 can be different from the order of the plurality of input / output units included in the column of the first data DATA1. Therefore, the process that can include matching the input / output units included in the first data DATA1 and the second data DATA2 performed by the computing device 10 will be described together with Figure 1 , Figure 5 and Figure 6 .

[0076] Referring to Figure 1 , Figure 5 and Figure 6 , the computing device 10 can acquire merged data DATA_M by merging the first data DATA1 with a row corresponding to a corresponding input / output unit in the second data DATA2 for each of the plurality of input / output units included in the first data DATA1.

[0077] The computing device 10 can detect at least one error among a short circuit error, a floating error, and a different type library error by using the merged data DATA_M generated by the above-described process, and the error detection method will be described in more detail with reference to the following drawings.

[0078] Figure 8A is a flowchart of a semiconductor chip design method according to an example embodiment of the inventive concept. Figure 8A may specifically be a method of detecting a short-circuit error that has occurred in a semiconductor chip design during operation S164 of Figure 4 will be described with reference to Figure 1 together. Figure 8A .

[0079] In operation S220, the computing device 10 can scan a plurality of columns respectively corresponding to a plurality of power and signal lines by using the merged data. For example, referring to Figure 7 together, the computing device 10 can scan all columns corresponding to the first to mth power and signal lines PSL1 to PSLm in the merged data DATA_M.

[0080] In operation S240, the computing device 10 can determine whether two or more different power sources are supplied to each ring included in the corresponding column. Here, the rings included in the column can indicate a path from a first cell to which no power and signal line is connected to a second cell to which no power and signal line is connected. Each power and signal line can include only one ring or a plurality of rings.

[0081] In operation S260, the computing device 10 can determine that a short-circuit error has occurred in the semiconductor chip design in response to the fact that at least two types of power sources or control signals are supplied to a single ring included in the corresponding column, and output a verification result RST including information about the short-circuit error. For example, the verification result RST can include at least one of data indicating that there is a short-circuit error, information about a power and signal line on which the short-circuit error has occurred, and information about an input / output cell on which the short-circuit error has occurred.

[0082] The operation of detecting a short-circuit error performed by the computing device 10 will be described below with reference to Figure 8B together.

[0083] Figure 8B is a view of merged data DATA_M and short-circuit error detection according to an example embodiment of the inventive concept. For ease of description, Figure 8B particular details of the merged data DATA_M shown in Figure 1 together. Figure 8A . Figure 8B ​

[0084] The computing device 10 can scan the columns in the merged data DATA M corresponding to the first to fourth power lines PL1 to PL4 and the first signal line SL1. Here, VDD, VSS, VSS0, DVSS, BIAS, and VDDP can denote different types of power.

[0085] The first power line PL1 includes one power line ring, and the power VDD is supplied to the first power line PL1 by the third input / output unit CELL_3, and thus, no short-circuit error occurs. Likewise, no short-circuit error occurs on the second power line PL2 and the fourth power line PL4. The power VDDP can be supplied to the fourth power line PL4 by the sixth input / output unit CELL_6. Also, the power BIAS is supplied to the first signal line SL1 by the second input / output unit CELL_2, and thus, no short-circuit error occurs.

[0086] However, the third power line PL3 includes a single power line ring, but the power VSS0 is provided to the power line ring included in the third power line PL3 by the fourth input / output unit CELL_4, and the power DVSS is also supplied to the power line ring included in the third power line PL3 by the seventh input / output unit CELL_7. Thus, in operation S240, the computing device 10 can determine that a short-circuit error has occurred on the third power line PL3. Thus, in operation S260, the computing device 10 can output the verification result RST including information indicating that a short-circuit error has occurred, information about the third power line PL3, and information about the fourth input / output unit CELL_4 and the seventh input / output unit CELL_7.

[0087] Figure 8C is a view of the merged data DATA M according to an example embodiment of the inventive concept. As Figure 8B compared to Figure 8C a case where no short-circuit error occurs is shown. Reference will be made to Figure 1 together describe Figure 8C .

[0088] differences from Figure 8C will mainly be described. Figure 8B .

[0089] The third power line PL3 can include two power line rings. For example, the third power line PL3 can include a first ring connected with the second to fourth input / output units CELL_2 to CELL_4 and a second ring connected with the sixth to eighth input / output units CELL_6 to CELL_8.

[0090] Reference will be made to Figure 8CAlthough both the power VSS0 and the power DVSS are supplied to the third power line PL3, the power VSS0 is supplied only to the first ring, and the power DVSS is supplied only to the second ring, thus, a short-circuit error does not occur. That is, even in a single power line, it should be determined for each power line ring whether a short-circuit error has occurred.

[0091] Figure 9A is a flowchart of a semiconductor chip design method according to an example embodiment of the inventive concept. Figure 9A may specifically be a method of detecting a floating error that has occurred in a semiconductor chip design during operation S164 of Figure 4 will be described with reference to Figure 1 together. Figure 9A .

[0092] In operation S320, the computing device 10 can scan a plurality of columns respectively corresponding to a plurality of power and signal lines by using the merged data. For example, referring to Figure 7 together, the computing device 10 can scan all columns corresponding to the first power and signal line PSL1 to the m-th power and signal line PSLm in the merged data DATA_M.

[0093] In operation S340, the computing device 10 can determine whether there is a power source connected to each ring included in the corresponding column. Here, the ring included in the column can indicate a path from a first cell to which no power and signal line is connected to a second cell to which no power and signal line is connected. Each power and signal line can include only one ring or a plurality of rings.

[0094] In operation S360, the computing device 10 can determine that a floating error has occurred in the semiconductor chip design in response to the fact that there is no power source connected to one ring included in the column corresponding to the power line (or in response to the fact that no power source is supplied to one ring), and output a verification result RST including information about the floating error. Alternatively, likewise, in response to the fact that there is no control signal provider connected to one ring included in the column corresponding to the signal line, the computing device 10 can determine that a floating error has occurred in the semiconductor chip design. For example, the verification result RST can include at least one of data indicating that there is a floating error, information about a power line or a signal line on which a floating error has occurred, and information about an input / output cell on which a floating error has occurred.

[0095] The operation of detecting a floating error performed by the computing device 10 will be described below with reference to Figure 9B .

[0096] Figure 9Bis a view of merged data DATA_M and floating error detection according to an example embodiment of the inventive concept. For ease of description, Figure 9B The specific details of the merged data DATA_M shown in FIG. 13 are merely illustrative. Reference will be made to Figure 1 and Figure 9A together describe Figure 9B .

[0097] The computing device 10 can scan columns corresponding to the first to fourth power lines PL1 to PL4 and the first signal line SL1 in the merged data DATA_M.

[0098] The first power line PL1 includes one power line ring, and the power VDD is supplied to the first power line PL1 by the third input / output unit CELL_3, and thus, no floating error occurs. Likewise, no floating error occurs on the second to fourth power lines PL2 to PL4.

[0099] When scanning the first signal line SL1, no control signal provider is connected to the first signal line SL1, and no control signal is supplied to the first signal line SL1. Thus, in operation S340, the computing device 10 can determine that a floating error has occurred on the first signal line SL1. Thus, in operation S360, the computing device 10 can output the verification result RST including information indicating that a floating error has occurred and information about the first signal line SL1.

[0100] Figure 10A is a flowchart of a semiconductor chip design method according to an example embodiment of the inventive concept. Figure 10A may specifically be a method of detecting different types of library errors that have occurred in a semiconductor chip design during operation S164 of Figure 4 Reference will be made to Figure 1 together describe Figure 10A .

[0101] In operation S420, the computing device 10 can scan a plurality of columns corresponding to a plurality of power and signal lines, respectively, by using the merged data. For example, referring to Figure 7 together, the computing device 10 can scan all columns corresponding to the first to mth power and signal lines PSL1 to PSLm in the merged data DATA_M.

[0102] In operation S440, the computing device 10 can determine whether two or more input / output cells corresponding to different libraries exist among the input / output cells connected to each ring included in the corresponding column. Here, the ring included in the column can indicate a path from a first cell having no power and signal line connection to a second cell having no power and signal line connection. Each power and signal line can include only one ring or multiple rings.

[0103] In operation S460, the computing device 10 can determine that a different type library error has occurred in the semiconductor chip design in response to the fact that the input / output cells corresponding to different libraries are included in a single ring included in the corresponding column, and output a verification result RST including information about the different type library error. For example, the verification result RST can include at least one of data indicating that the different type library error exists, information about the signal line on which the different type library error has occurred, and information about the input / output cell on which the different type library error has occurred.

[0104] The operation of detecting the different type library error performed by the computing device 10 will be described below with reference to Figure 10C

[0105] Figure 10B is a view for describing a problem that can occur when the input / output cells belonging to different type libraries are connected in a single ring.

[0106] For ease of description, Figure 10B An example embodiment in which the power and signal lines include a first power line PL1, a second power line PL2, and a first signal line SL1 is shown.

[0107] Referring to Figure 10B , the first input / output cell 1121 and the second input / output cell 1122 can belong to the first library LIB1, and the third input / output cell 1123 can belong to the second library LIB2. The input / output cells belonging to the same library can have the same size and the pins to which the power and signal lines having the same position are connected. According to example embodiments of the inventive concept, for some libraries, the input / output cells belonging to different libraries can have different sizes and the pins to which the power and signal lines having different positions are connected. For example, the size of the third input / output cell 1123 can be different from the size of the first input / output cell 1121 and the second input / output cell 1122, and the positions of the pins to which the power and signal lines of the third input / output cell 1123 are connected can be different from the positions of the pins to which the power and signal lines of the first input / output cell 1121 and the second input / output cell 1122 are connected.

[0108] Therefore, as Figure 10B ​As shown in FIG. 1, when input / output cells belonging to different libraries are connected to a single ring, an error occurs in the arrangement of the input / output cells.

[0109] Figure 10C is a view of merged data DATA M and different type library error detection according to example embodiments of the inventive concept. For ease of description, Figure 10C particular details of the merged data DATA M shown in FIG. 1 are merely illustrative. Reference will be made to Figure 1 and Figure 10A together describe Figure 10C .

[0110] Referring to Figure 10C , the merged data DATA M can further include information about a library to which each input / output cell belongs. Reference will be made to Figure 11A and Figure 11B to describe a configuration of a computing device and / or data for the merged data DATA M.

[0111] In operation S420, the computing device 10 can scan columns corresponding to the first to fourth power lines PL1 to PL4 and the first signal line SL1 in the merged data DATA M.

[0112] The second to seventh input / output cells CELL_2 to CELL_7 belonging to one signal line ring can be connected to the first signal line SL1. However, among the second to seventh input / output cells CELL_2 to CELL_7 belonging to one signal line ring, the second to fifth input / output cells CELL_2 to CELL_5 and the seventh input / output cell CELL_7 belong to the first library LIB1, and the sixth input / output cell CELL_6 belongs to the second library LIB2. Accordingly, in operation S440, the computing device 10 can determine that a different type library error has occurred. Accordingly, in operation S460, the computing device 10 can output a verification result RST including information about the different type library error.

[0113] Figure 11A and Figure 11B are views of the computing devices 20a and 20b according to example embodiments of the inventive concept. Figure 11A and Figure 11B specifically illustrate operations and configurations of the computing device required to detect a different type library error with reference to Figure 10A and Figure 10B will mainly describe Figure 11A and Figure 11B differences from Figure 1 .

[0114] Referring to Figure 11A , with Figure 1Similarly, the computing device 20a can acquire the first data DATA1 and the second data DATA2, and output the verification result RST based on the first data DATA1 and the second data DATA2. However, unlike Figure 1 the second data DATA2 can further include a plurality of pieces of library information (e.g., a first library LIB1 to an n-th library LIBn) corresponding to the plurality of input / output units, respectively.

[0115] Referring to Figure 11B , unlike Figure 1 , the computing device 20b can acquire the first data DATA1, the second data DATA2, and the third data DATA3, and output the verification result RST based on the first data DATA1, the second data DATA2, and the third data DATA3. Here, the third data DATA3 can include a plurality of pieces of library information corresponding to the plurality of input / output units, respectively. The computing device 20b can generate the merged data DATA_M as shown in Figure 10C by merging the first data DATA1, the second data DATA2, and the third data DATA3.

[0116] Figure 12 is a view of the input / output units 1121, 1122, 1123, and 1130, one of which is referred to as a linker unit 1130, according to example embodiments of the inventive concept. Figure 12 is described with reference to Figure 10A and Figure 10C features of correcting the arrangement of the input / output units. It will also be described together with Figure 1 . Figure 12 .

[0117] As described above with reference to Figure 10B , when the input / output units belonging to different libraries are directly connected to each other, a different type library error is caused. When the verification result RST including information about the different type library error is output, the computing device 10 can correct the arrangement error by using the linker unit 1130 as shown in Figure 12 .

[0118] Here, the linker unit 1130 can indicate a unit configured to help wiring between the input / output units belonging to different libraries.

[0119] While the inventive concept has been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of designing a semiconductor chip, the method comprising: obtaining first data indicative of an arrangement of a plurality of cells on a semiconductor chip; obtaining second data indicative of wiring between the plurality of cells and power and signal lines, the power and signal lines including at least one power line and at least one signal line; and outputting a verification result by detecting at least one error in the arrangement of the plurality of cells based on the first data and the second data, wherein the step of outputting the verification result comprises: obtaining merged data by merging wiring information of corresponding cells among the first data and the second data; detecting the at least one error based on the merged data; and generating the verification result indicative of the at least one error.

2. The method of claim 1, further comprising: modifying at least one of the first data and the second data based on the verification result.

3. The method of claim 1, further comprising: outputting design data for manufacturing the semiconductor chip based on the first data, the second data, and the verification result; and manufacturing the semiconductor chip based on the design data.

4. The method of claim 1, wherein, the at least one error includes at least one of a short error, a floating error, and a different type library error.

5. The method of claim 4, wherein, the second data includes a matrix having a plurality of rows corresponding to each of the plurality of cells and a plurality of columns corresponding to each of the power and signal lines, and the matrix includes data indicative of whether a cell is connected to a corresponding power and signal line of the power and signal lines or data indicative of a type of power source or control signal supplied to a corresponding power and signal line of the power and signal lines.

6. The method of claim 5, wherein, the step of detecting the at least one error comprises: scanning the plurality of columns corresponding to each of the power and signal lines in the merged data; and in response to detecting that two different types of power sources are connected to a ring corresponding to one of the plurality of columns, detecting a short error.

7. The method of claim 5, wherein, the step of detecting the at least one error comprises: scanning the plurality of columns corresponding to each of the power and signal lines in the merged data; and in response to detecting that no power source is connected to a ring corresponding to one of the plurality of columns, detecting a floating error.

8. The method of claim 5, wherein, the second data further includes a plurality of library information corresponding to each of the plurality of cells, and the step of detecting the at least one error comprises: scanning the plurality of columns corresponding to each of the power and signal lines in the merged data; determining whether cells corresponding to different libraries are included in a same ring corresponding to one of the plurality of columns based on the plurality of library information; and in response to determining that cells corresponding to different libraries are included in the same ring, detecting a different type library error.

9. The method of claim 5, wherein, the step of obtaining the merged data comprises obtaining the merged data by merging the first data, the second data, and third data including a plurality of library information corresponding to each of the plurality of cells, and the step of detecting the at least one error comprises: scanning the plurality of columns corresponding to each of the power and signal lines in the merged data; determining whether cells corresponding to different banks are included in the same ring corresponding to one column of the plurality of columns based on the plurality of bank information; and in response to determining that cells corresponding to different banks are included in the same ring, detecting a different type bank error.

10. The method of any one of claims 1 to 9, further comprising: based on a type and details of the error included in the verification result, outputting correction information indicating a correction performed on one or more of the first data and the second data.

11. A method of designing a semiconductor chip, the method comprising: obtaining first data indicating an arrangement of a plurality of cells on a semiconductor chip; obtaining second data including wiring information indicating wiring between the plurality of cells and a power supply and a plurality of bank information corresponding to the plurality of cells; obtaining merged data by merging wiring information of corresponding cells among the first data and the second data; detecting at least one error among a short error, a floating error, and a different type bank error based on the merged data; and outputting a verification result indicating the at least one error.

12. The method of claim 11, wherein, The second data includes a matrix having a plurality of rows corresponding to each of the plurality of cells and a plurality of columns corresponding to each of the power and signal lines, and the matrix includes data indicating whether the cell is connected to a corresponding one of the power and signal lines or data indicating a type of a power supply or a control signal supplied to the corresponding one of the power and signal lines.

13. A computing device, the computing device comprising: at least one processor; and a memory storing instructions that, when executed by the at least one processor, configure the at least one processor to: obtain first data indicating an arrangement of a plurality of cells on a semiconductor chip; obtain second data indicating wiring between the plurality of cells and power and signal lines including at least one power line and at least one signal line; and output a verification result by detecting at least one error in the arrangement of the plurality of cells based on the first data and the second data, wherein the instructions, when executed by the at least one processor, configure the at least one processor to output the verification result by: obtaining merged data by merging wiring information of corresponding cells among the first data and the second data; detecting the at least one error based on the merged data; and generating the verification result indicating the at least one error. The at least one error includes at least one of a short error, a floating error, and a different type bank error.

14. The computing device of claim 13, wherein, The second data includes a matrix having a plurality of rows corresponding to each of the plurality of cells and a plurality of columns corresponding to each of the power and signal lines, and the matrix includes data indicating whether the cell is connected to a corresponding one of the power and signal lines or data indicating a type of a power supply or a control signal supplied to the corresponding one of the power and signal lines.

15. The computing device of claim 14, wherein, ​ 16. The computing device of claim 15, wherein, The instructions, when executed by the at least one processor, configure the at least one processor to detect the at least one error by: scanning the plurality of columns corresponding to each of the power and signal lines in the consolidated data; and in response to detecting that at least two different power sources are connected to the ring corresponding to one of the plurality of columns, detecting a short error. The instructions, when executed by the at least one processor, configure the at least one processor to detect the at least one error by:

17. The computing device of claim 15, wherein, scanning the plurality of columns corresponding to each of the power and signal lines in the consolidated data; and in response to detecting that no power source is connected to the ring corresponding to one of the plurality of columns, detecting a floating error. The second data further includes a plurality of bank information corresponding to each of the plurality of cells, and the instructions, when executed by the at least one processor, configure the at least one processor to detect the at least one error by: scanning the plurality of columns corresponding to each of the power and signal lines in the consolidated data; 18. The computing device of claim 15, wherein, determining whether cells corresponding to different banks are included in the same ring corresponding to one of the plurality of columns based on the plurality of bank information; and in response to detecting that cells corresponding to different banks are included in the same ring, detecting a different type bank error. The instructions, when executed by the at least one processor, configure the at least one processor to: obtain consolidated data by consolidating the first data, the second data, and third data, the third data including a plurality of bank information corresponding to each of the plurality of cells, and detect the at least one error by:

19. The computing device of claim 15, wherein, scanning the plurality of columns corresponding to each of the power and signal lines in the consolidated data; determining whether cells corresponding to different banks are included in the same ring corresponding to one of the plurality of columns based on the plurality of bank information; and in response to determining that cells corresponding to different banks are included in the same ring, detecting a different type bank error. 20.A non-transitory computer-readable recording medium including a program that, when executed by a computer, configures the computer to perform the method of designing a semiconductor chip according to any one of claims 1 to 12. ​ ​ ​ ​

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