Memory system

Abstract

The embodiment improves the communication band of a memory system. The memory system (1) of the embodiment includes a first chip (MC) and a second chip (CC) bonded to the first chip. The memory system (1) of the embodiment includes a semiconductor memory device (4) and a memory controller (3). The semiconductor memory device (4) includes a memory cell array (15), a peripheral circuit (18) for controlling the memory cell array (15), and an input / output module (10) connected to the peripheral circuit (18). The memory controller (3) receives instructions from an external host device and controls the semiconductor memory device (4) via the input / output module (10). The first chip (MC) includes the memory cell array (15), and the second chip (CC) includes the peripheral circuit (18), the input / output module (10), and the memory controller (3).

Description

[0001] Related applications

[0002] This application claims priority based on Japanese Patent Application No. 2020-111105 (filing date: June 29, 2020), and the entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system. Background Art

[0004] A NAND flash memory capable of storing data in a nonvolatile manner is known. Summary of the Invention

[0005] Embodiments increase the communication bandwidth of a memory system.

[0006] A memory system according to an embodiment includes a first chip and a second chip bonded to the first chip. The memory system according to an embodiment includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, peripheral circuits for controlling the memory cell array, and an input / output module connected to the peripheral circuits. The memory controller receives instructions from an external host device and controls the semiconductor memory device via the input / output module. The first chip includes the memory cell array, and the second chip includes the peripheral circuits, the input / output module, and the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a configuration example of the memory system according to the first embodiment.

[0008] Figure 2 This is a block diagram showing a configuration example of a semiconductor memory device included in the memory system according to the first embodiment.

[0009] Figure 3 It is a perspective view showing an example of the configuration of the memory system according to the first embodiment.

[0010] Figure 4 This is a block diagram showing an example of the configuration of each component in the memory system according to the first embodiment.

[0011] Figure 5 This is a block diagram showing an example of the arrangement of each component in a memory system according to a first modification of the first embodiment.

[0012] Figure 6 This is a block diagram showing an example of the arrangement of each component in a memory system according to a second modification of the first embodiment.

[0013] Figure 7This is a block diagram showing an example of the arrangement of each component in a memory system according to a third modification of the first embodiment.

[0014] Figure 8 This is a block diagram showing an example of the arrangement of each component in a memory system according to a fourth modification of the first embodiment.

[0015] Figure 9 This is a block diagram showing an example of the arrangement of each component in a memory system according to a fifth modification of the first embodiment.

[0016] Figure 10 This is a block diagram showing an example of the configuration of each component in a memory system according to a sixth modification of the first embodiment.

[0017] Figure 11 This is a block diagram showing an example of the configuration of each component in a memory system according to the seventh modification of the first embodiment.

[0018] Figure 12 This is a block diagram showing an example of the configuration of each component in a memory system according to the eighth modification of the first embodiment.

[0019] Figure 13 It is a cross-sectional view showing an example of the structure of the memory system according to the second embodiment.

[0020] Figure 14 This is a block diagram showing an example of the configuration of each component in the memory system according to the second embodiment.

[0021] Figure 15 This is a block diagram showing an example of the arrangement of each component in a memory system according to a first modification of the second embodiment.

[0022] Figure 16 This is a block diagram showing an example of the arrangement of each component in a memory system according to a second modification of the second embodiment.

[0023] Figure 17 This is a block diagram showing an example of the configuration of each component in a memory system according to a third modification of the second embodiment.

[0024] Figure 18 This is a block diagram showing an example of the configuration of each component in a memory system according to a fourth modification of the second embodiment.

[0025] Figure 19 This is a block diagram showing an example of the configuration of each component in a memory system according to a fifth modification of the second embodiment.

[0026] Figure 20 This is a block diagram showing an example of the configuration of each component in a memory system according to a sixth modification of the second embodiment. DETAILED DESCRIPTION

[0027] The following describes the embodiments with reference to the accompanying drawings. Each embodiment exemplifies an apparatus or method for embodying the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of the drawings may not necessarily correspond to actual dimensions. The technical concept of the invention is not determined by the shape, structure, or arrangement of the components.

[0028] In the following description, components having substantially the same function and structure are denoted by the same reference numerals. The numerals following the characters constituting the reference numerals are referenced by the reference numerals containing the same characters and are used to distinguish components having the same structure from one another. Where it is not necessary to distinguish components indicated by reference numerals containing the same characters, these components are referenced by reference numerals consisting solely of the characters.

[0029] [1] First embodiment

[0030] Hereinafter, a memory system 1 according to the first embodiment will be described.

[0031] [1-1] Structure

[0032] Figure 1 FIG. 1 shows a configuration example of a memory system according to the first embodiment. Figure 1 As shown, the memory system 1 includes a memory controller 3 and a semiconductor memory device 4. The memory controller 3 is connected to a host bus HB. The memory controller 3 and the semiconductor memory device 4 are connected via a NAND bus NB. The memory system 1 is a memory device that meets the UFS (Universal Flash Storage) standard, for example.

[0033] The host device 2 is, for example, a personal computer or a smartphone. A host bus HB connects the memory system 1 and the host device 2. Communication between the memory system 1 and the host device 2 via the host bus HB complies with the UFS standard.

[0034] The memory controller 3 receives commands from the host device 2 via the host bus HB. The memory controller 3 sends instructions to the semiconductor memory device 4 via the NAND bus NB, the instructions being based on the commands received from the host device 2. The memory controller 3 sends data received from the semiconductor memory device 4 via the NAND bus NB to the host device 2 via the host bus HB.

[0035] The semiconductor storage device 4 is a type of NAND flash memory capable of storing data in a nonvolatile manner. The semiconductor storage device 4 performs operations such as writing and reading data based on commands received from the memory controller 3 via the NAND bus NB.

[0036] Figure 2 FIG. 4 shows a configuration example of the semiconductor memory device 4 included in the memory system 1 according to the first embodiment. Figure 2 As shown, the semiconductor memory device 4 includes an input / output module 10, a serial / parallel conversion circuit 13, a register 14, a memory cell array 15, a row decoder 16, a sense amplifier 17, a sequencer 18, a first internal bus IB1, a second internal bus IB2, and a third internal bus IB3.

[0037] The input / output module 10 is connected to the NAND bus NB and transmits and receives signals with the memory controller 3. A plurality of control signals communicated via the NAND bus NB include, for example, signals DQ0 to DQ(i-1), DQS, DQSn, CEn, CLE, ALE, WEn, RE, REn, WPn, and RBn.

[0038] Signals DQ0 to DQ(i-1) are transmitted and received between the semiconductor memory device 4 and the memory controller 3. i is an integer greater than or equal to 2. Signals DQ0 to DQ(i-1) each represent either an "H" level or an "L" level. Signals DQ0 to DQ(i-1) represent i bits of information using the combination of "H" and "L" levels they represent. Signals DQ0 to DQ(i-1) represent the substance of the data transmitted and received between the semiconductor memory device 4 and the memory controller 3 and can include any of commands, addresses, and data.

[0039] Signals DQS and DQSn are transmitted and received between the semiconductor memory device 4 and the memory controller 3. Signals DQS and DQSn are used to control the operation timing when receiving signals DQ0 to DQ(i-1).

[0040] Signal CEn is transmitted from memory controller 3 to semiconductor memory device 4. Signal CEn is used to select or deselect semiconductor memory device 4. For example, if multiple semiconductor memory devices 4 are connected to memory controller 3, memory controller 3 can use a signal to select a semiconductor memory device 4 to be activated. When signal CEn is at an "H" level, memory controller 3 deselects semiconductor memory device 4. When signal CEn is at an "L" level, memory controller 3 selects semiconductor memory device 4.

[0041] Signals CLE, ALE, WEn, RE, REn, and WPn are each transmitted from memory controller 3 to semiconductor memory device 4. Signal CLE notifies that signals DQ0 to DQ(i-1) are commands. Signal ALE notifies that signals DQ0 to DQ(i-1) are addresses. Signal WEn instructs semiconductor memory device 4 to read signals DQ0 to DQ(i-1). Signals RE and REn instruct semiconductor memory device 4 to output signals DQ0 to DQ(i-1). Signals RE and REn control the timing of semiconductor memory device 4's operation when outputting signals DQ0 to DQ(i-1). Signal WPn inhibits write and erase operations in semiconductor memory device 4.

[0042] Signal RBn is transmitted from semiconductor storage device 4 to memory controller 3. Signal RBn indicates whether semiconductor storage device 4 is in a ready state (accepting an external command) or a busy state (not accepting an external command).

[0043] The NAND bus NB includes, for example, a plurality of wirings corresponding to various signals. Specifically, it includes i data lines DW corresponding to signals DQ0 to DQ(i-1), and a plurality of logic lines LW corresponding to signals DQS, DQSn, CEn, CLE, ALE, WEn, RE, REn, WPn, and RBn, respectively.

[0044] Hereinafter, in this specification, the amount of information a bus can transmit at one time is referred to as bus width. For example, if an internal bus has a bus width of 32 bits, the bus includes 32 data lines and can transmit 32 bits of data at a time. For example, a NAND bus NB, which includes 8 common lines for instructions, addresses, and data, has a bus width of 8 bits. Furthermore, the bus width of the NAND bus NB is not limited to 8 bits. It can also have any number of bits, such as a bus width that is a multiple of 4 or a power of 2.

[0045] The first internal bus IB1, the second internal bus IB2, and the third internal bus IB3 serve as paths for transmitting information within the semiconductor memory device 4. For example, the bus width of the first internal bus IB1 is equal to the bus width of the NAND bus NB. Alternatively, for example, the bus width of the first internal bus IB1 is narrower than the bus width of the second internal bus IB2.

[0046] The input / output module 10 includes an input / output circuit 11 and a logic control circuit 12 .

[0047] The input / output circuit 11 transmits and receives signals DQ0 to DQ(i-1), DQS, and DQSn to and from the memory controller 3. The input / output circuit 11 is connected to the first internal bus IB1. The input / output circuit 11 transmits information based on the received signals DQ0 to DQ(i-1) to the serial / parallel conversion circuit 13 via the first internal bus IB1. Furthermore, the input / output circuit 11 outputs signals DQ0 to DQ(i-1) based on the information received from the serial / parallel conversion circuit 13 via the first internal bus IB1.

[0048] The logic control circuit 12 receives signals CEn, CLE, ALE, WEn, RE, REn, and WPn, and transmits a signal RBn. The logic control circuit 12 transmits signals based on the received signals to the input / output circuit 11 and the sequencer 18 .

[0049] The serial / parallel conversion circuit 13 converts serial signals into parallel signals. The serial / parallel conversion circuit 13 is connected to the input / output circuit 11 via the first internal bus IB1 and to the register 14 via the second internal bus IB2. The serial / parallel conversion circuit 13 amplifies the bus width of signals received from the first internal bus IB1 and transmits them to the second internal bus IB2. The serial / parallel conversion circuit 13 reduces the bus width of signals received from the second internal bus and transmits them to the first internal bus IB1.

[0050] The register 14 stores the received information and outputs the stored information to the outside. The register 14 is connected to the serial / parallel conversion circuit 13 via the second internal bus IB2 and to the sense amplifier 17 via the third internal bus IB3. For example, the register 14 stores the information received from the serial / parallel conversion circuit 13 and outputs it to the sense amplifier 17. The register 14 stores the information received from the sense amplifier 17 and outputs it to the serial / parallel conversion circuit 13.

[0051] The memory cell array 15 stores data in a nonvolatile manner. The memory cell array 15 includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MT. The plurality of memory cells MT are arranged, for example, in rows and columns. The plurality of bit lines BL are arranged in the column direction and are connected to the plurality of memory cells MT corresponding to the same column. The plurality of word lines WL are arranged in the row direction and are connected to the plurality of memory cells MT corresponding to the same row.

[0052] The row decoder 16 receives the row address from the register 14 and selects the memory cells MT in the row direction based on the row address. Then, the row decoder 16 applies a voltage to the selected memory cells MT in the row direction.

[0053] When reading data, the sense amplifier 17 reads the read data read from the memory cell MT to the bit line BL and transfers the read data to the register 14. When writing data, the sense amplifier 17 transfers the write data written via the bit line BL to the memory cell MT. The sense amplifier 17 also receives a column address from the register 14 and outputs the column data based on the column address.

[0054] The sequencer 18 controls the overall operation of the semiconductor memory device 4 . For example, the sequencer 18 receives a command from the register 14 and executes a read operation based on the received command. Furthermore, the sequencer 18 controls the input / output circuit 11 based on control by the logic control circuit 12 .

[0055] Figure 3 FIG. 1 shows an example of the structure of the memory system 1 according to the first embodiment. Figure 3 As shown, the memory system 1 includes a memory chip MC and a CMOS chip CC, and has a structure in which the lower surface of the memory chip MC is bonded to the upper surface of the CMOS chip CC. The size of the memory chip MC in the XY plane is approximately equal to the size of the CMOS chip CC in the XY plane. The memory chip MC includes, for example, a structure corresponding to the memory cell array 15. The memory chip MC is manufactured using a NAND process. The CMOS chip CC includes, for example, a structure corresponding to the input / output module 10. The CMOS chip CC is manufactured using a CMOS process. Details of the circuits included in each of the memory chip MC and the CMOS chip CC will be described later.

[0056] The memory chip MC has a plurality of bonding pads BP at its lower portion. The bonding pads BP of the memory chip MC are electrically connected to the circuitry within the memory chip MC. The CMOS chip CC has a plurality of bonding pads BP at its upper portion. The bonding pads BP of the CMOS chip CC are electrically connected to the circuitry within the CMOS chip CC. When the memory chip MC and the CMOS chip CC are aligned and overlapped, the bonding pads BP of the memory chip MC and the bonding pads BP of the CMOS chip are arranged so as to overlap. The bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are bonded to each other and electrically connected.

[0057] Figure 4 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the first embodiment. Figure 4As shown, in the memory system 1 of the first embodiment, the memory controller 3 and a portion of the semiconductor memory device 4 are included in the CMOS chip CC, while the portion of the semiconductor memory device 4 not included in the CMOS chip CC is included in the memory chip MC. Specifically, the memory controller 3, the input / output module 10, the serial / parallel conversion circuit 13, the register 14, and the sequencer 18 of the semiconductor memory device 4 are included in the CMOS chip CC. The memory cell array 15, the row decoder 16, and the sense amplifier 17 of the semiconductor memory device 4 are included in the memory chip MC.

[0058] The NAND bus NB has, for example, an 8-bit bus width and is provided within the CMOS chip CC. The first internal bus IB1 has, for example, an 8-bit bus width and is provided within the CMOS chip CC. The second internal bus IB2 has, for example, a 32-bit bus width and is provided within the CMOS chip CC. The third internal bus IB3 has, for example, a 32-bit bus width and is provided across the CMOS chip CC and the memory chip MC. Specifically, the third internal bus IB3 includes electrical connections via bonding pads BP.

[0059] [1-2] Effects of the First Embodiment

[0060] According to the memory system 1 of the first embodiment described above, it is possible to improve the communication bandwidth of the memory system 1. Hereinafter, the effects of the memory system 1 of the first embodiment will be described in detail.

[0061] To achieve larger capacity in semiconductor memory devices, it is desirable to increase the dedicated area of the memory cell array. To address this, a known semiconductor memory device has a bonded structure in which a NAND chip including the memory cell array and a CMOS chip including peripheral circuits surrounding the memory cell array are fabricated from separate wafers and bonded together.

[0062] The bonded structure can increase the dedicated area of the memory cell array, reducing the chip area. Furthermore, the bonded structure can suppress degradation of the CMOS circuitry caused by the NAND process, including the high-temperature heat treatment required to form the memory cell array. Furthermore, the bonded structure is constructed by bonding two chips of roughly equal size. Therefore, while the area of the peripheral circuitry can be reduced relative to the area of the memory cell array, this can create unused space within the CMOS chip CC.

[0063] Furthermore, as the volume of data processed by host devices increases, there is a demand for faster communication speeds within memory systems. To achieve these speeds, it is also necessary to consider wiring losses, such as those in the bonding wires and printed circuit boards between the semiconductor memory device and the memory controller. Therefore, parasitic components such as parasitic resistance, capacitance, and inductance in the wiring are preferably minimized.

[0064] Therefore, in the memory system 1 of the first embodiment, the memory controller 3 is arranged on the CMOS chip CC. Specifically, the memory controller 3 and the input / output module 10 of the semiconductor memory device 4 are arranged on the CMOS chip CC. This arrangement allows the wiring between the memory controller 3 and the semiconductor memory device 4 to be arranged within the CMOS chip CC with an extremely short distance, thus suppressing parasitic components. As a result, the memory system 1 of the first embodiment can increase the operating frequency and thus the communication bandwidth.

[0065] Furthermore, in the memory system 1 of the first embodiment, since the memory controller 3 can be arranged in the free space of the CMOS chip CC, a separate chip on which the memory controller 3 is mounted is no longer required. Furthermore, in the memory system 1 of the first embodiment, the process of connecting the memory controller 3 to the semiconductor memory device 4 is integrated into the process of forming the CMOS chip CC, and the manufacturing process for forming the memory controller 3 is appropriately integrated into the manufacturing process for forming the peripheral circuits of the semiconductor memory device 4. As a result, the memory system 1 of the first embodiment can reduce the cost of forming and connecting the memory controller 3.

[0066] [1-3] Modification of the First Embodiment

[0067] The memory system 1 of the first embodiment can be modified in various ways. Various modification examples are described below.

[0068] (First Modification of the First Embodiment)

[0069] Figure 5 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the first modification of the first embodiment. Figure 5As shown, the memory system 1 of the first variation of the first embodiment differs from the memory system 1 of the first embodiment in that the bus widths of the NAND bus NB, the first internal bus IB1, the second internal bus IB2, and the third internal bus IB3 are different. Specifically, in the memory system 1 of the first variation of the first embodiment, the NAND bus NB has a bus width of 32 bits, the first internal bus IB1 has a bus width of 32 bits, the second internal bus IB2 has a bus width of 64 bits, and the third internal bus IB3 has a bus width of 64 bits. The rest of the structure of the memory system 1 of the first variation of the first embodiment is the same as that of the first embodiment.

[0070] The amount of information a bus can transmit simultaneously depends on its width. Increasing the bus width is a possible method for achieving higher-speed communication. However, increasing the bus width increases the number of signal lines included in the bus, potentially increasing the area and volume required for bus installation. For example, if the controller and semiconductor memory device are provided on separate chips and mounted on separate printed circuit boards, increasing the bus width of the NAND bus NB requires additional pins on each chip and wiring on the printed circuit board to accommodate the additional signal lines.

[0071] In the memory system 1 of the first embodiment, the NAND bus NB is provided within the CMOS chip CC. Therefore, when the bus width of the NAND bus NB is increased, as in the memory system 1 of the first variation of the first embodiment, the design changes associated with the increased bus width are completed within the CMOS chip CC. In other words, the memory system 1 of the first variation of the first embodiment can increase the bus width of the NAND bus NB without increasing the number of chip pins or wiring on the printed circuit board.

[0072] In the memory system 1 according to the first modified example of the first embodiment, the bus width of the first internal bus IB1 is also increased to 32 bits, corresponding to the increase in the bus width of the NAND bus NB to 32 bits. Furthermore, the bus widths of the second internal bus IB2 and the third internal bus IB3 are also increased to 64 bits. Since the first internal bus IB1 and the second internal bus IB2 are provided within the CMOS chip CC, similar to the NAND bus NB, the bus width can be increased without increasing the number of chip pins or wiring on the printed circuit board.

[0073] The third internal bus IB3 spans the CMOS chip CC and the memory chip MC and includes electrical connections via bonding pads BP. Therefore, increasing the bus width of the third internal bus IB3 increases the number of signal lines included in the third internal bus IB3 and the number of bonding pads BP. However, in a bonding structure, the bonding pads BP are connected in one step, so even if the number of bonding pads BP increases, the cost increase can be suppressed. Therefore, the memory system 1 of the first variant of the first embodiment can increase the bus width of the third internal bus IB3 while suppressing cost increases.

[0074] As described above, the memory system 1 according to the first modification of the first embodiment can increase the bus width of each bus while suppressing an increase in cost, thereby improving the communication bandwidth, compared to the memory system 1 according to the first embodiment.

[0075] Furthermore, increasing the bus width can, for example, suppress increases in operating frequency while also increasing the communication bandwidth. The NAND bus NB of the memory system 1 of the first variant of the first embodiment has a bus width that is four times that of the NAND bus NB of the memory system 1 of the first embodiment. For example, if the operating frequency of the NAND bus NB of the memory system 1 of the first variant of the first embodiment is one-third of the operating frequency of the NAND bus NB of the memory system 1 of the first embodiment, the communication bandwidth of the memory system 1 of the first variant of the first embodiment can achieve a communication speed that is four-thirds that of the memory system 1 of the first embodiment. Thus, increasing the bus width can suppress the operating frequency and increase the communication bandwidth of the bus compared to a case where the bus width is not increased. Furthermore, by reducing the operating frequency of the bus, circuit installation can be facilitated. Consequently, the development and installation costs of the memory system 1 can be reduced.

[0076] (Second Modification of the First Embodiment)

[0077] Figure 6 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the second modified example of the first embodiment. Figure 6As shown, the memory system 1 according to the second modification of the first embodiment has the following structure: compared to the memory system 1 according to the first modification of the first embodiment, the NAND bus NB is omitted, and the memory system 1 further includes a data bus DB and a logic bus LB. Furthermore, the semiconductor memory device 4 included in the memory system 1 according to the second modification of the first embodiment has the following structure: compared to the semiconductor memory device 4 included in the memory system 1 according to the first modification of the first embodiment, the input / output module 10 is replaced with an input / output module 10a, and the serial / parallel conversion circuit 13, the first internal bus IB1, and the second internal bus IB2 are omitted.

[0078] In the memory system 1 according to the second variation of the first embodiment, the memory controller 3 and the semiconductor memory device 4 are connected via a data bus DB and a logic bus LB. Data bus DB transmits signals corresponding to signals DQ0 to DQ(i-1) in the first embodiment. Logic bus LB transmits signals corresponding to signals DQS, DQSn, CEn, CLE, ALE, WEn, RE, REn, WPn, and RBn in the first embodiment. The remaining configuration is the same as that of the first variation of the first embodiment.

[0079] In the semiconductor memory device 4 of the second variation of the first embodiment, the memory controller 3 and registers 14 are directly connected via a data bus DB having a bus width of 64 bits. That is, the signal path between the memory controller 3 and registers 14 does not include a serial / parallel conversion circuit or an input / output module. Therefore, the memory system 1 of the second variation of the first embodiment can reduce circuit scale and increase the bus width of the bus connecting the memory controller 3 and semiconductor memory device 4. Consequently, the memory system 1 of the second variation of the first embodiment can increase the communication bandwidth.

[0080] (Third Modification of the First Embodiment)

[0081] Figure 7 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the third modified example of the first embodiment. Figure 7 As shown, the memory system 1 of the third variant of the first embodiment has the following structure: relative to the first variant of the first embodiment, the NAND bus NB is replaced by the first NAND bus NB1 and the second NAND bus NB2, and further includes a switching module 5, a first test bus TB1 and a second test bus TB2.

[0082] The memory controller 3 and the switching module 5 are connected via a first NAND bus NB1. The first NAND bus NB1 has, for example, a bus width of 32 bits. The switching module 5 is connected to the input / output module 10 included in the semiconductor memory device 4 via a second NAND bus NB2. The second NAND bus NB2 has, for example, a bus width of 32 bits. The switching module 5 is connected to a first test bus TB1 and a second test bus TB2, respectively. The first test bus TB1 and the second test bus TB2 are configured to be connectable to the outside of the memory system 1. The first test bus TB1 has, for example, a bus width of 8 bits. The second test bus TB2 has, for example, a bus width of 8 bits.

[0083] The first test bus TB1 is connected to, for example, a memory controller 3a provided outside the memory system 1. The memory controller 3a is connected to a host device (not shown) via a host bus HB. The second test bus TB2 is connected to, for example, a semiconductor storage device 4a provided outside the memory system 1.

[0084] The switching module 5 receives the signal SW and switches the signal based on the signal SW. Furthermore, the switching module 5 has a function of performing serial / parallel conversion when connecting two buses of different bus widths. For example, when the switching module 5 connects the first NAND bus NB1 to the second NAND bus NB2, the memory controller 3 communicates with the semiconductor memory device 4 and functions as the memory system 1. For example, when the switching module 5 connects the first test bus TB1 to the second NAND bus NB2, the memory controller 3a communicates with the semiconductor memory device 4, and the operation of the semiconductor memory device 4 can be controlled by the memory controller 3a. For example, when the switching module 5 connects the first NAND bus NB1 to the second test bus TB2, the memory controller 3 communicates with the semiconductor memory device 4a, and the operation of the semiconductor memory device 4a can be controlled by the memory controller 3. The remaining structure is the same as that of the first variant of the first embodiment.

[0085] It is conceivable to perform separate operational tests on the memory controller 3 and semiconductor memory device 4 that constitute the memory system 1. In the memory system 1 according to the third modified example of the first embodiment, the external memory controller 3a can be connected to the semiconductor memory device 4, or the memory controller 3 can be connected to the external semiconductor memory device 4a, via the switching module 5, the first test bus TB1, and the second test bus TB2. This allows the operation of the semiconductor memory device 4 within the memory system 1 to be confirmed via the external memory controller 3a. Furthermore, the operation of the memory controller 3 within the memory system 1 can be confirmed via the external semiconductor memory device 4a.

[0086] Furthermore, in the memory system 1 according to the third variation of the first embodiment, the switching module 5 has a function of performing serial / parallel conversion. Consequently, in the memory system 1 according to the third variation of the first embodiment, the external memory controller 3a can be connected using the first test bus TB1, which has a narrower bus width than the first NAND bus NB1. Furthermore, the external semiconductor storage device 4a can be connected using the second test bus TB2, which has a narrower bus width than the second NAND bus NB2.

[0087] To connect the memory system 1 to an external circuit, it is conceivable to provide pads for connection on the chip, or to provide pins that allow external connection from the package containing the memory system 1. In the memory system 1 according to the third variation of the first embodiment, the bus widths of the first test bus TB1 and the second test bus TB2 are smaller than those of the first NAND bus NB1 and the second NAND bus NB2. This reduces the number of pads, pins, and the like used to connect the memory system 1 to an external circuit.

[0088] Furthermore, the operating frequencies of the first NAND bus NB1, second NAND bus NB2, first test bus TB1, and second test bus TB2 can each be arbitrarily set. For example, if the first NAND bus has a bus width of 32 bits and the first test bus TB1 has a bus width of 8 bits, the operating frequency of the first test bus TB1 can be set to four times that of the first NAND bus NB1. By setting the operating frequency in this way, even if the bus width of the first test bus TB1 is narrower than that of the first NAND bus NB1, the same amount of information can be transmitted.

[0089] Alternatively, for example, the operating frequency of the first test bus TB1 may be set lower than the operating frequency of the first NAND bus NB1. By setting the operating frequency in this way, communication via the first test bus TB1 can be slower than communication via the first NAND bus NB1, but operation tests can still be performed.

[0090] In the third modified example of the first embodiment, the bus widths of the first test bus TB1 and the second test bus TB2 are each narrower than the bus widths of the first NAND bus NB1 and the second NAND bus NB2. However, the bus width relationship is not limited to this. For example, the bus widths of the first NAND bus NB1 and the first test bus TB1 may be equal.

[0091] Furthermore, the external memory controller 3a can be configured to connect to a host device different from the memory controller 3 included in the memory system 1. For example, if the memory controller 3 included in the memory system 1 complies with the UFS standard, the external memory controller 3a can also comply with the eMMC (embedded MMC) standard. In this configuration, by combining the memory system 1 and the external memory controller 3a, it is possible to comply with a standard different from that complied by the memory system 1, such as the eMMC standard.

[0092] (Fourth Modification of the First Embodiment)

[0093] Figure 8 FIG. 4 shows an example of the configuration of each component in the memory system 1 according to the fourth modified example of the first embodiment. Figure 8 As shown, the memory system 1 according to the fourth modification of the first embodiment has a configuration in which, compared to the memory system 1 of the first embodiment, the NAND bus NB is continuously provided to the outside of the CMOS chip CC and further includes a semiconductor storage device 4b.

[0094] In the memory system 1 of the fourth variant of the first embodiment, the NAND bus NB is continuously provided inside and outside the CMOS chip CC. A memory controller 3, a semiconductor storage device 4, and a semiconductor storage device 4b are connected to the NAND bus NB. The semiconductor storage device 4b can be configured in any manner as long as it can perform actions such as storing or reading data based on instructions received from the memory controller 3 via the NAND bus NB. For example, it can have a structure in which the CMOS chip CC and the memory chip MC are bonded together, or it can be configured on a single semiconductor substrate, or it can have a structure in which multiple semiconductor substrates are stacked. The other structures are the same as those of the fourth variant of the first embodiment.

[0095] The memory system 1 according to the fourth variation of the first embodiment can expand its storage capacity by connecting multiple semiconductor storage devices to the NAND bus NB. Furthermore, while the fourth variation of the first embodiment illustrates an example in which the semiconductor storage device 4 and the semiconductor storage device 4b are connected to the NAND bus NB, the number of semiconductor storage devices connected to the NAND bus NB is not limited to this. The memory system 1 according to the fourth variation of the first embodiment can further expand its storage capacity by connecting multiple semiconductor storage devices to the NAND bus NB.

[0096] (Fifth Modification of the First Embodiment)

[0097] Figure 9FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the fifth modification of the first embodiment. Figure 9 As shown, the memory system 1 according to the fifth modification of the first embodiment further includes a chip AC compared to the memory system 1 of the first embodiment, and a part of the functions of the memory controller 3 is arranged in the chip AC.

[0098] In the memory system 1 according to the fifth variation of the first embodiment, the memory controller 3 includes a host interface module 31 (HOSTIF module), a control unit 32, and a NAND interface module 33 (NANDIF module). The host interface module 31 and the control unit 32 are provided in chip AC. The NAND interface module 33 is provided in CMOS chip CC.

[0099] The host interface module 31 is connected to the host bus HB and communicates with the host bus HB via the host device 2. The host interface module 31 transmits signals received from the host device 2 to the control unit 32. In addition, the host interface module 31 transmits signals received from the control unit 32 to the host device 2 via the host bus HB.

[0100] The control unit 32 controls the overall operation of the memory controller 3. The control unit 32 is connected to the NAND interface module 33 via the controller bus CB. The control unit 32 receives signals from the host interface module 31 and sends signals to the NAND interface module 33. In addition, the control unit 32 receives signals from the NAND interface module 33 and sends signals to the host interface module 31.

[0101] The NAND interface module 33 is connected to the control unit 32 via the controller bus CB, and is connected to the input / output module 10 included in the semiconductor storage device 4 via the NAND bus NB. The NAND interface module 33 transmits signals received from the control unit 32 to the input / output module 10. In addition, the NAND interface module 33 transmits signals received from the input / output module to the control unit 32.

[0102] The controller bus CB is, for example, an AHB bus, and has a bus width of, for example, 32 bits.

[0103] For example, if the CMOS chip CC and memory chip MC are small, or if the circuit scale of the memory controller 3 is large, it is difficult to place all controllers on the CMOS chip CC. In the memory system 1 according to the fifth modified example of the first embodiment, the NAND interface module 33 of the memory controller 3 is placed on the CMOS chip CC. Furthermore, circuits other than the NAND interface module 33 of the memory controller 3 are placed on the chip AC, which is connected to the CMOS chip CC via a controller bus CB. The remaining structure is the same as that of the first embodiment.

[0104] With this configuration, in the memory system 1 according to the fifth variation of the first embodiment, even if not all memory controllers 3 are provided on the CMOS chip CC, the NAND bus NB can be provided within the CMOS chip CC, similar to the memory system 1 according to the first embodiment. Furthermore, the controller bus CB connecting the chip AC and the CMOS chip CC is a relatively wide bus, such as a 32-bit bus width. Therefore, in the memory system 1 according to the fifth variation of the first embodiment, communication between the chip AC and the CMOS chip CC can be accelerated.

[0105] (Sixth Modification of the First Embodiment)

[0106] Figure 10 FIG. 6 shows an example of the configuration of each component in the memory system 1 according to the sixth modification of the first embodiment. Figure 10 As shown, the memory system 1 according to the sixth modification of the first embodiment has a configuration similar to the memory system 1 according to the fifth modification of the first embodiment, further including a NAND interface module 33 a and a semiconductor storage device 4 c .

[0107] In the memory system 1 according to the sixth variation of the first embodiment, the NAND interface module 33a is connected to the controller bus CB. The NAND interface module 33a is connected to the semiconductor storage device 4c via the NAND bus NB. The NAND interface module 33a and the semiconductor storage device 4c may, for example, have a structure formed by laminating a CMOS chip CC and a memory chip MC, or they may be provided as separate chips or constructed on a single semiconductor substrate. The remaining structure is the same as that of the fifth variation of the first embodiment.

[0108] In this manner, by connecting multiple NAND interface modules and semiconductor storage devices to the controller bus CB, the storage capacity of the memory system 1 can be expanded. Furthermore, in the sixth variation of the first embodiment, an example is shown in which the NAND interface module 33 and the NAND interface module 33a are connected to the controller bus CB. However, the number of connected NAND interface modules and the number of semiconductor storage devices included in the memory system 1 are not limited thereto. The memory system 1 of the sixth variation of the first embodiment can further expand its storage capacity by providing multiple NAND interface modules and semiconductor storage devices.

[0109] (Seventh and Eighth Modifications of the First Embodiment)

[0110] Figure 11 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the seventh modification of the first embodiment. Figure 11 As shown, the memory system 1 according to the seventh modification of the first embodiment differs from the memory system 1 according to the first embodiment in that the row decoder 16 is provided in the CMOS chip CC. The remaining configuration is the same as that of the first embodiment.

[0111] Figure 12 FIG. 8 shows an example of the configuration of each component in the memory system 1 according to the eighth modification of the first embodiment. Figure 12 As shown, the memory system 1 according to the eighth modification of the first embodiment differs from the memory system 1 according to the first embodiment in that a row decoder 16 and a sense amplifier 17 are provided on the CMOS chip CC. The remaining configuration is the same as that of the first embodiment.

[0112] The memory chip MC is manufactured using a NAND process that includes a memory cell array manufacturing process. The memory chip MC only needs to include the memory cell array 15. The row decoder 16 and sense amplifier 17 can be provided in the memory chip MC or in the CMOS chip CC. The first through sixth variations of the first embodiment can also be modified in the same way as the seventh and eighth variations of the first embodiment.

[0113] [2] Second embodiment

[0114] The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in terms of chip structure and connection method. Hereinafter, the differences between the semiconductor memory device of the second embodiment and the first embodiment will be described.

[0115] [2-1] Structure

[0116] Figure 13FIG. 1 shows an example of a cross-sectional structure of the memory system 1 according to the second embodiment. Figure 13 As shown, the memory system 1 of the second embodiment includes core chips 100-1 to 100-8, an IF chip 200, a controller chip 300, a sealing resin 40, a packaging substrate 51, a plurality of solder balls 52, a plurality of spacers 53, an adhesive 54, a support plate 55, a plurality of through electrodes 56, a plurality of solder balls 57, 58 and 59, and redistribution layers 61 and 62 and a packaging member 64.

[0117] Each of core chips 100-1 through 100-8 includes at least a memory cell array. Each of core chips 100-1 through 100-8 is manufactured using a NAND process. IF chip 200 includes at least an input / output module 10. Controller chip 300 includes at least a portion of memory controller 3. Controller chip 300 is manufactured using a CMOS process. Details of the circuits included in each chip will be described later.

[0118] A redistribution layer 62 is disposed on the upper portion of the package substrate 51. The package substrate 51 is a BGA (Ball Grid Array) substrate having a plurality of solder balls 52. The plurality of solder balls 52 serve as terminals for connection to an external device, such as the host device 2. The package substrate 51 is made of, for example, BT (bismaleimide triazine).

[0119] The IF chip 200 and the controller chip 300 are bonded to each other on the package substrate 51 and the rewiring layer 62. The IF chip 200 and the controller chip 300 are similar to those used in the first embodiment. Figure 3 The same as the example described above, has a fitting structure. Figure 13 In the example shown, the upper portion is the IF chip 200 and the lower portion is the controller chip 300. Figure 13 Although hatching is omitted in FIG, the space between the package substrate 51 and the controller chip 300 is filled with the sealing resin 40. Alternatively, the structure formed by bonding the IF chip 200 and the controller chip 300 may be directly disposed on the package substrate 51 without the sealing resin 40 interposed therebetween.

[0120] A rewiring layer 61 is arranged on top of the structure in which the IF chip 200 and the controller chip 300 are bonded. A stack of core chips 100-1 to 100-8 is arranged on top of the rewiring layer 61. A spacer 53 is provided between two adjacent core chips 100 to ensure spacing. For example, an adhesive insulating resin such as epoxy resin, polyimide resin, acrylic resin, phenolic resin, or pentenecyclobutene resin can be used as the spacer 53. Surface wiring and backside wiring are formed on each core chip 100, and the core chips 100 are stacked with the surface wiring facing downward (face down).

[0121] The top surface of the topmost core chip 100-8 is bonded to a support plate 55 via an adhesive 54. Adhesive 54 can be made of an insulating resin or a touch film. Support plate 55 prevents damage to the core chips 100 due to mechanical stress during handling of the core chip 100 stack. A metal plate such as a lead frame can also be used as support plate 55. Examples of materials for support plate 55 include Cu and 42 alloy (Fe-Ni alloy).

[0122] Core chips 100-1 to 100-7, other than the topmost core chip 100-8, are provided with a plurality of through-electrodes 56. Although not shown, the through-electrodes 56 are insulated from the core chip 100 by sidewall insulating films. Materials such as Cu, Ni, and Al can be used for the through-electrodes 56. The through-electrodes 56 of core chips 100-1 to 100-7 are connected to the through-electrodes of core chips 100-2 to 100-8 located above them via solder balls 57. This interconnects the through-electrodes 56 located at the same position in the XY plane of core chips 100-1 to 100-8, and the core chips 100-1 to 100-8 are connected to each other via the through-electrodes 56 and solder balls 57.

[0123] The through-electrodes of the bottom-stacked core chip 100-1 are electrically connected to the wiring within the redistribution layer 61. IF chip 200 is electrically connected to the wiring within redistribution layer 61 via multiple solder balls 58. The wiring within redistribution layer 61 is electrically connected to the wiring within redistribution layer 62 via solder balls 59. The wiring within redistribution layer 62 is connected to solder balls 52 via wiring 63. In other words, the core chip 100 stack is electrically connected to the structure formed by laminating the IF chip 200 and the controller chip 300. Furthermore, the core chip 100 stack and the structure formed by laminating the IF chip 200 and the controller chip 300 are each electrically connected to the external host device 2 via multiple wiring layers and solder balls.

[0124] The stacked structure of core chip 100 and the structure formed by bonding IF chip 200 and controller chip 300 are placed in a package 64 filled with sealing resin 40. In other words, the stacked structure of core chip 100, IF chip 200, and controller chip 300 are sealed with the sealing resin to form a single package. Package 64 can also be made of the same material as sealing resin 40.

[0125] Alternatively, the controller chip 300 may be connected to the host device 2 via the IF chip 200. For example, the IF chip 200 may include a through-electrode extending from the bonding surface to the back surface of the IF chip 200. Furthermore, the controller chip 300 may be connected to the solder balls 58 via the through-electrode provided on the IF chip 200.

[0126] Furthermore, the controller chip 300 may be connected to the host device 2 without going through the IF chip 200. Specifically, the controller chip 300 may be electrically connected to the wiring within the redistribution layer 61 without going through the IF chip 200. The wiring within the redistribution layer 61 is electrically connected to the wiring within the redistribution layer 62 via the solder balls 59. The wiring within the redistribution layer 62 is connected to the solder balls 52 via the wiring 63. Alternatively, the controller chip 300 may be connected to the wiring within the redistribution layer 62 without going through the wiring within the redistribution layer 61, and connected to the solder balls 52 via the wiring 63. In this case, the controller chip 300 may be connected to the solder balls 58 via the through electrodes provided in the controller chip 300.

[0127] Figure 14 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the second embodiment. Figure 14 As shown, in the memory system 1 of the second embodiment, the plurality of core chips 100 each include a memory cell array 15, a row decoder 16, a sense amplifier 17, a portion of a register 14, and a portion of a sequencer 18. The IF chip 200 includes an input / output module 10, a serial / parallel conversion circuit 13, a portion of the register 14, and a portion of the sequencer 18. The controller chip 300 includes a memory controller 3.

[0128] The NAND bus NB has a bus width of, for example, 8 bits and is provided across the controller chip 300 and the IF chip 200. The NAND bus NB includes electrical connections via bonding pads. The third internal bus IB3 is provided within the core chip 100. The remaining structure is the same as that of the first embodiment.

[0129] In addition, Figure 14In the illustrated example, a portion of the register 14 and a portion of the sequencer 18 are provided in each of the multiple core chips 100 and the IF chip 200. The arrangement of the register 14 and the sequencer 18 is not limited to this. For example, the register 14 may be provided only in the IF chip 200 or in multiple core chips 100. Furthermore, the sequencer 18 may be provided only in the IF chip 200 or in multiple core chips 100.

[0130] [2-2] Effects of the Second Embodiment

[0131] According to the memory system 1 of the second embodiment described above, the communication bandwidth of the memory system 1 can be increased, similarly to the first embodiment. Hereinafter, the effects of the memory system 1 of the second embodiment will be described in detail, focusing on differences from the first embodiment.

[0132] In the memory system 1 of the second embodiment, the semiconductor memory device 4 is composed of multiple core chips 100 and IF chips 200. In the semiconductor memory device 4 included in the memory system 1 of the second embodiment, multiple core chips 100 including the memory cell array 15 are stacked, and the IF chip 200 including the input / output module 10 is shared by the multiple core chips 100. This configuration reduces costs and increases storage capacity compared to a case where multiple semiconductor memory devices are provided.

[0133] Furthermore, the memory system 1 of the second embodiment has a structure in which the IF chip 200 including the input / output module 10 and the controller chip 300 including the memory controller 3 are bonded together. With this structure, the NAND bus NB included in the memory system 1 of the second embodiment is provided with a path including connections using bonding pads, extending across the IF chip 200 and the controller chip 300.

[0134] Connections using bonding pads can reduce parasitic components in signal lines compared to connections using wiring on a printed circuit board or connections using bonding wires. Thus, in the memory system 1 of the second embodiment, similar to the memory system 1 of the first embodiment, communication between the memory controller 3 and the semiconductor memory device 4 can be accelerated.

[0135] [2-3] Modification of the Second Embodiment

[0136] The memory system 1 of the second embodiment can be modified in various ways. Various modification examples are described below.

[0137] (First Modification of the Second Embodiment)

[0138] Figure 15FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the first modified example of the second embodiment. Figure 15 As shown, the memory system 1 of the first variant of the second embodiment undergoes the same modifications as the first variant of the first embodiment relative to the memory system 1 of the second embodiment. Specifically, the memory system 1 of the first variant of the second embodiment differs from the memory system 1 of the second embodiment in that the bus widths of the NAND bus NB, the first internal bus IB1, the second internal bus IB2, and the third internal bus IB3 are different. Specifically, in the memory system 1 of the first variant of the second embodiment, the NAND bus NB has a bus width of 32 bits, the first internal bus IB1 has a bus width of 32 bits, the second internal bus IB2 has a bus width of 64 bits, and the third internal bus IB3 has a bus width of 64 bits. The remaining configuration is the same as that of the memory system 1 of the second embodiment.

[0139] The memory system 1 according to the first modification of the second embodiment, like the memory system 1 according to the first modification of the first embodiment, can increase the bus width of each bus while suppressing an increase in cost, thereby improving the communication bandwidth.

[0140] (Second Modification of the Second Embodiment)

[0141] Figure 16 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the second modification of the second embodiment. Figure 16 As shown, the memory system 1 of the second variation of the second embodiment has undergone the same modifications as the memory system 1 of the first variation of the second embodiment. Specifically, the memory system 1 of the second variation of the second embodiment differs from the memory system 1 of the first variation of the second embodiment in that communication is performed using a data bus DB and a logic bus LB instead of a NAND bus NB. Furthermore, the semiconductor memory device 4 included in the memory system 1 of the second variation of the second embodiment has the following structure: the input / output module 10 is replaced with an input / output module 10a, and the serial / parallel conversion circuit 13, the first internal bus IB1, and the second internal bus IB2 are omitted.

[0142] The memory system 1 according to the second variation of the second embodiment, like the memory system 1 according to the second variation of the first embodiment, can reduce circuit scale and increase the bus width of the bus connecting the memory controller 3 and the semiconductor memory device 4. Consequently, the memory system 1 according to the second variation of the second embodiment can increase the communication bandwidth.

[0143] (Third Modification of the Second Embodiment)

[0144] Figure 17 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the third modified example of the second embodiment. Figure 17 As shown, the memory system 1 of the third modification of the second embodiment is different from the memory system 1 of the second embodiment in that the controller is provided across the controller chip 300 and the IF chip 200 , and the controller chip 300 and the IF chip 200 are connected by a controller bus CB.

[0145] In the memory system 1 according to the third variation of the second embodiment, the memory controller 3 includes a host interface module 31 (HOST IF module), a control unit 32, and a NAND interface module 33 (NAND IF module). The host interface module 31 and the control unit 32 are provided in the controller chip 300. The NAND interface module 33 is provided in the IF chip 200.

[0146] The host interface module 31 is connected to the host bus HB and communicates with the host device 2 via the host bus HB. The host interface module 31 transmits signals received from the host device 2 to the control unit 32. In addition, the host interface module 31 transmits signals received from the control unit 32 to the host device 2 via the host bus HB.

[0147] The control unit 32 controls the overall operation of the memory controller 3. The control unit 32 is connected to the NAND interface module 33 via the controller bus CB. The control unit 32 receives signals from the host interface module 31 and sends signals to the NAND interface module 33. In addition, the control unit 32 receives signals from the NAND interface module 33 and sends signals to the host interface module 31.

[0148] The NAND interface module 33 is connected to the control unit 32 via the controller bus CB, and is connected to the input / output module 10 included in the semiconductor storage device 4 via the NAND bus NB. The NAND interface module 33 transmits signals received from the control unit 32 to the input / output module 10. In addition, the NAND interface module 33 transmits signals received from the input / output module to the control unit 32.

[0149] The controller bus CB is, for example, an AHB bus, and has a bus width of, for example, 32 bits.

[0150] For example, if the circuits included in the controller chip 300 are large in scale and the circuits included in the IF chip 200 are small in scale, the controller chip 300 and the IF chip 200 are provided with equal sizes. This reduces the integration density of the chip with the smaller circuit scale, potentially increasing costs. In the memory system 1 of the third modified example of the second embodiment, the memory controller 3 is provided across the controller chip 300 and the IF chip 200. Specifically, the NAND interface module 33 of the memory controller 3 is provided in the IF chip 200. Circuits other than the NAND interface module 33 of the memory controller 3 are provided in the controller chip 300. The controller chip 300 and the IF chip 200 are connected via a controller bus CB.

[0151] With this configuration, in the memory system 1 according to the third variation of the second embodiment, the circuit scale of the circuits included in the controller chip 300 can be made approximately equal to the circuit scale of the circuits included in the IF chip 200. This improves the integration density of the controller chip 300 and the IF chip 200, thereby reducing costs. Furthermore, the NAND bus NB can be located within the IF chip 200, reducing parasitic components in the signal lines that comprise the NAND bus NB. Furthermore, the controller bus CB connecting the controller chip 300 and the IF chip 200 is a relatively wide bus, such as a 32-bit bus width. Consequently, the memory system 1 according to the third variation of the second embodiment can increase the communication bandwidth.

[0152] (Fourth Modification of the Second Embodiment)

[0153] Figure 18 FIG. 4 shows an example of the configuration of each component in the memory system 1 according to the fourth modified example of the second embodiment. Figure 18 As shown, the memory system 1 according to the fourth modification of the second embodiment is different from the memory system 1 according to the second embodiment in that the register 14 is changed to a register 14 a and the chip in which each circuit is arranged is changed.

[0154] Specifically, the register 14 a is a register larger in size than the register 14 included in the memory system 1 of the second embodiment. The register 14 a is provided throughout the IF chip 200 and the plurality of core chips 100 , but most of the registers 14 a are provided in the IF chip 200 .

[0155] Most of the registers 14a and part of the sequencer 18 are located in the IF chip 200. The majority of the area of the IF chip 200 is occupied by the registers 14a. The controller chip 300 includes the memory controller 3, the input / output module 10, and the serial / parallel conversion circuit 13. The NAND bus NB is located within the controller chip 300. The first internal bus IB1 is also located within the controller chip 300. The second internal bus IB2 extends across the controller chip 300 and the IF chip 200, including connections via bonding pads.

[0156] The register 14a can be used as, for example, a cache memory of the semiconductor memory device 4. In the memory system 1 according to the fourth modification of the second embodiment, a large-capacity cache memory can be realized by the large-scale register 14a.

[0157] (Fifth Modification of the Second Embodiment)

[0158] Figure 19 FIG. 2 shows an example of the configuration of each component in the memory system 1 according to the fifth modification of the second embodiment. Figure 19 As shown, the memory system 1 according to the fourth modification of the second embodiment has a configuration in which the NAND bus NB is provided to the outside of the controller chip 300 and a semiconductor storage device 4d is further included.

[0159] In the memory system 1 according to the fifth variation of the second embodiment, the NAND bus NB is continuously provided inside and outside the controller chip 300. A semiconductor memory device 4d is connected to the NAND bus NB outside the controller chip 300. The semiconductor memory device 4d can be configured in any manner as long as it can perform operations such as storing or reading data based on instructions received from the memory controller 3 via the NAND bus NB. For example, it can have a structure comprising multiple laminated substrates, a single semiconductor substrate, or a stack of multiple semiconductor substrates.

[0160] In this manner, by connecting multiple semiconductor storage devices to the NAND bus NB, the storage capacity of the memory system 1 can be expanded. Furthermore, in the fifth variation of the second embodiment, an example is shown in which the semiconductor storage device 4 and the semiconductor storage device 4d are connected to the NAND bus NB. However, the number of semiconductor storage devices connected to the NAND bus NB is not limited to this. The memory system 1 of the fifth variation of the second embodiment can further expand its storage capacity by connecting multiple semiconductor storage devices to the NAND bus NB.

[0161] (Sixth Modification of the Second Embodiment)

[0162] Figure 20 FIG. 1 shows an example of the configuration of each component in the memory system 1 according to the sixth modification of the second embodiment. Figure 20 As shown, the memory system 1 of the sixth modification of the second embodiment has the following configuration: Compared to the memory system 1 of the second embodiment, it further includes a chip 400, a NAND interface module 33b, and a semiconductor storage device 4e, but does not include a serial / parallel conversion circuit. The input / output module 10 is replaced by an input / output module 10a. Furthermore, the chip on which each circuit is located is changed.

[0163] In the memory system 1 according to the sixth variation of the second embodiment, the memory controller 3 includes a host interface module 31 (HOST IF module), a control unit 32, and a NAND interface module 33 (NAND IF module). The functions of the host interface module 31, the control unit 32, and the NAND interface module 33 are the same as those described in the third variation of the second embodiment.

[0164] The IF chip 200 includes an input / output module 10a, a portion of the register 14, and a portion of the sequencer 18. The controller chip 300 includes a NAND interface module 33. The chip 400 includes a host interface module 31 and a control unit 32.

[0165] The register 14 of the IF chip 200 is connected to the NAND interface module 33 of the controller chip 300 via a data bus DB. The input / output module 10a of the IF chip is connected to the NAND interface module 33 of the controller chip 300 via a logic bus LB. The functions of the input / output module 10a, data bus DB, and logic bus LB are the same as those described in the second modified example of the first embodiment.

[0166] The IF chip 200 is bonded to the controller chip 300. A plurality of signal lines constituting each of the data bus DB and the logic bus LB are connected using bonding pads.

[0167] The NAND interface module 33 of the controller chip 300 is connected to the control unit 32 of the chip 400 via a controller bus CB. The controller bus CB is, for example, an AHB bus. The bus width of the controller bus CB is, for example, 32 bits. In the memory system 1 according to the sixth variation of the second embodiment, the controller bus CB includes, for example, wiring on a printed circuit board.

[0168] A NAND interface module 33b is connected to the controller bus CB. The NAND interface module 33b is connected to the semiconductor storage device 4d. The NAND interface module 33b and the semiconductor storage device 4d can, for example, have a structure in which a CMOS chip CC and a memory chip MC are bonded together, or they can be provided as separate chips, constructed on a single semiconductor substrate, or even comprised of multiple stacked semiconductors. Furthermore, the NAND interface module 33b and the semiconductor storage device 4d can be connected via a NAND bus, a data bus, or a logic bus.

[0169] In the memory system 1 according to the sixth variation of the second embodiment, the memory controller 3 and registers 14 are directly connected via a data bus DB. That is, the signal path between the memory controller 3 and registers 14 does not include a serial / parallel conversion circuit or an input / output module. Therefore, the memory system 1 according to the sixth variation of the second embodiment can reduce circuit size and increase the bus width of the bus connecting the memory controller 3 and the semiconductor memory device 4. Consequently, the memory system 1 according to the sixth variation of the second embodiment can increase the communication bandwidth.

[0170] Furthermore, in the memory system 1 according to the sixth variation of the second embodiment, the chip 400 and the controller chip 300 are connected via a controller bus CB. The controller bus CB has a wide bus width. Therefore, the memory system 1 according to the sixth variation of the second embodiment can achieve high-speed communication between the chip 400 and the controller chip 300.

[0171] Furthermore, in the memory system 1 according to the sixth variation of the second embodiment, multiple NAND interface modules and semiconductor storage device pairs are connected to the controller bus CB. Thus, the memory system 1 according to the sixth variation of the second embodiment can expand storage capacity by providing multiple NAND interface modules and semiconductor storage devices.

[0172] [3] Other variations, etc.

[0173] In the embodiment, the memory system 1 is described as meeting the UFS standard. The standard met by the memory system 1 is not limited to this. As an example, the host bus HB is a bus for serial communication. In this case, the communication performed via the host bus HB meets the USB (Universal Serial Bus) or SAS (Serial Attached SCSI) or PCIe TM In addition, as another example, the host bus HB may be a UHS-I bus of the SDTM card standard or a parallel communication bus that meets the eMMC standard.

[0174] In this specification, a "wide" bus width means that the bus can transmit a large amount of information at a time. In this specification, a "narrow" bus width means that the bus can transmit a small amount of information at a time. For example, a bus with a 32-bit bus width has a wider bus width than a bus with an 8-bit bus width. For example, a bus with an 8-bit bus width has a narrower bus width than a bus with a 32-bit bus width.

[0175] In this specification, "connection" means electrical connection, and does not exclude the case where other elements are interposed. In addition, "electrical connection" can be any connection as long as the same operation as the electrical connection is possible, and may be connected through an insulator.

[0176] While several embodiments of the present invention have been described above, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are intended to be included within the scope and gist of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0177] Description of Reference Numerals

[0178] 1…Memory system, 3…Memory controller, 4…Semiconductor memory device, 5…Switching module, 10…I / O module, 11…I / O circuit, 12…Logic control circuit, 13…Serial / parallel conversion circuit, 14…Register, 15…Memory cell array, 16…Row decoder, 17…Sense amplifier, 18…Sequencer, 31…Host interface module, 32…Control unit, 33…NAND interface module, 40…Sealing resin, 51…Packaging substrate, 52…Solder ball, 53…Spacer, 54…Adhesive, 55…Support plate, 56…Through electrode, 57…Solder ball, 58…Solder ball, 59…Solder ball, 61…Return Wiring layer, 62…rewiring layer, 63…wiring, 64…package, 100…core chip, 200…IF chip, 300…controller chip, 400…chip, AC…chip, BL…bit line, BP…bonding pad, CB…controller bus, CC…CMOS chip, DB…data bus, DW…data line, HB…host bus, IB1…first internal bus, IB2…second internal bus, IB3…third internal bus, LB…logic bus, LW…logic line, MC…memory chip, MT…memory cell, NB…NAND bus, TB1…first test bus, TB2…second test bus, WL…word line.

Claims

1. A memory system comprising a first chip and a second chip bonded to the first chip, the memory system comprising: A semiconductor memory device comprising: a memory cell array for storing data non-volatilely; a register; and a peripheral circuit including a sequencer for executing a read operation and a write operation on memory cells constituting the memory cell array based on instructions stored in the register. and an input and output module connected to the peripheral circuit; as well as a memory controller that receives an instruction from an external host device and sends the command based on the instruction to the semiconductor memory device; The first chip includes the memory cell array. The second chip includes the register storing the instruction, the peripheral circuit including the sequencer, the input / output module, and the memory controller.

2. The memory system according to claim 1, wherein: Also features: a plurality of data lines connecting the input / output module and the memory controller for transmitting and receiving data; and A plurality of logic lines connect the input / output module and the memory controller and are used for communicating control signals of the semiconductor memory device.

3. The memory system according to claim 2, wherein: The number of the plurality of data lines is greater than 32.

4. The memory system according to claim 1, wherein: The register temporarily stores data written to the memory cell array and data read from the memory cell array. The semiconductor memory device further comprises: a plurality of data lines connecting the register and the memory controller for transmitting and receiving data; and A plurality of logic lines connect the input / output module and the memory controller and are used for communicating control signals of the semiconductor memory device.

5. The memory system according to claim 4, wherein: The number of the plurality of data lines is greater than 64. The memory system according to claim 2 , wherein: Also includes: Switching modules; and a plurality of wirings connected to the switching module and configured to be electrically connected to the outside of the second chip; The switching module is configured to electrically connect the memory controller to the plurality of wirings or to electrically connect the input / output module to the plurality of wirings. The number of the plurality of wirings is equal to or less than the total number of the data lines and the number of the logic lines.

7. The memory system according to claim 2, wherein: The plurality of data lines and the plurality of logic lines are configured to be electrically connectable to the outside of the second chip.

8. The memory system according to claim 1, wherein: The first chip comprises: a row decoder that receives a row address from the register and selects the memory cell in a row direction based on the row address; and The sense amplifier reads the read data read from the memory cell to the bit line during the data read operation and transfers the read data to the register. During the data write operation, the sense amplifier transfers the write data written via the bit line to the memory cell.

9. The memory system according to claim 1, wherein: The second chip further comprises: The sense amplifier reads the read data read from the memory cell to the bit line during the data read operation and transfers the read data to the register. During the data write operation, the sense amplifier transfers the write data written via the bit line to the memory cell.

10. The memory system according to claim 1, wherein: The input / output module is connected to the memory controller included in the second chip and does not output a signal to the outside of the second chip.

11. A memory system comprising: Chip 1; a second chip bonded to the first chip; and a plurality of third chips electrically connected to and stacked on the first chip, The memory system comprises: A semiconductor memory device includes a plurality of memory cell arrays for storing data nonvolatilely and an input / output module. A memory controller receives an instruction from an external host device and sends a command based on the instruction to the semiconductor memory device. The first chip includes the input / output module, a register storing the instructions, and a sequencer, wherein the sequencer executes a read operation and a write operation on the memory cells constituting the memory cell array based on the instructions stored in the register. The second chip includes the memory controller, The plurality of third chips respectively include the plurality of memory cell arrays.

12. The memory system according to claim 11, wherein: The first chip and the second chip each further include a plurality of bonding pads on the surface to be bonded. The input / output module and the memory controller are connected by a plurality of wirings including the plurality of bonding pads.

13. The memory system according to claim 12, wherein: The plurality of wirings include: a plurality of data lines connecting the input / output module and the memory controller for transmitting and receiving data; and a plurality of logic lines connecting the input / output module and the memory controller for communicating control signals of the semiconductor memory device; The number of the plurality of data lines is greater than 32.

14. The memory system according to any one of claims 1 to 13, wherein: The memory controller includes a host interface connectable to the external host device.

15. The memory system according to claim 14, wherein: The host interface uses serial communication.

16. A memory system comprising: The first chip has an input and output module; a second chip, bonded to the first chip, receiving an instruction from an external host device and sending a command based on the instruction to the first chip; and A plurality of third chips are electrically connected to the first chip and have a plurality of memory cell arrays for storing data in a non-volatile manner. The first chip includes, in addition to the input / output module, a sequencer and a register storing the instructions. The sequencer executes a read operation and a write operation on the memory cells constituting the memory cell array based on the instructions stored in the register. The plurality of third chips are stacked and electrically connected to each other via through electrodes.

17. The memory system according to claim 16, wherein: The first chip, the second chip, and the plurality of third chips are sealed with resin to form a single package.

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