Memory systems to ensure reliability

Abstract

The present disclosure relates to a memory system, which includes: a memory device and a controller. The controller includes: a first internal storage device; a second internal storage device configured to store a recovery code; a level detector configured to detect whether the level change of the power supply voltage exceeds the reference level range respectively; a protection operation component configured to determine to enter and exit the protection mode in response to the result of the level detector, perform a first protection operation, the first protection operation generates event information and snapshot information, and stores the event information and snapshot information in the first internal storage device; and a recovery operation component configured to receive a recovery code from the second internal storage device in response to exiting the protection mode, enter a recovery mode, receive event information and snapshot information from the first internal storage device, and perform a recovery operation on the memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0085978, filed on Jul. 13, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to a memory system, and more particularly, to a memory system for ensuring reliability. Background Art

[0004] Recently, the paradigm of computer environment has shifted to ubiquitous computing, which enables access to computer systems almost anywhere, at any time. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has increased. Such portable electronic devices generally use or include a memory system including or embedded with at least one memory device, such as a data storage device. The data storage device can be used as a primary storage device or a secondary storage device of the portable electronic device.

[0005] Computing devices benefit from implementing data storage in the form of nonvolatile semiconductor memory devices because nonvolatile semiconductor memory devices have excellent stability and durability due to the absence of mechanical drive components (e.g., a mechanical arm in a hard disk), and can exhibit high data access speeds and low power consumption. Examples of semiconductor data storage devices include universal serial bus (USB) memory devices, memory cards with various interfaces, and / or solid-state drives (SSDs). Summary of the invention

[0006] Various embodiments are directed to a memory system capable of effectively ensuring reliability even when the level of a power supply voltage supplied from the outside is changed.

[0007] In an embodiment, a memory system may include: a memory device; and a controller operably connected to the memory device through a plurality of interfaces. The controller may include: a first internal storage device having a volatile characteristic; a second internal storage device having a non-volatile characteristic and configured to store a recovery code; a level detector configured to detect whether the level change of the power supply voltage exceeds a reference level range, respectively, and generate a detection signal corresponding to the result of the detection; a protection operation component configured to determine entry and exit of a protection mode in response to the detection signal, and to perform a first protection operation when entering the protection mode, the first protection operation generating event information about the state of the memory system, generating a logic value of each of a plurality of interfaces as snapshot information, and storing the event information and the snapshot information in the first internal storage device, and the protection operation component is further configured to perform a second protection operation, the second protection operation fixing each of the plurality of interfaces to a set logic value; and a recovery operation component configured to receive a recovery code from the second internal storage device in response to the memory system exiting the protection mode, entering the recovery mode, receiving the event information and the snapshot information from the first internal storage device, and performing a recovery operation on the memory device.

[0008] The protection operation component can generate operation information and execution information when entering the protection mode in response to the detection signal, and can store the operation information and execution information in the first internal storage device as event information, the operation information is related to the operation of entering the protection mode, and the execution information indicates whether the second protection operation has been completed.

[0009] The controller may further include a buffer configured to buffer signals to be transmitted to the memory device through the plurality of interfaces. The protection operation component may generate a logic value of the signal buffered by the buffer as snapshot information when entering the protection mode, and store the snapshot information in the first internal storage device.

[0010] The recovery operation component may identify data having an error probability higher than a reference probability among data stored in the memory device in response to event information and snapshot information in a recovery mode, and may perform an error correction operation on the identified data.

[0011] The power supply voltage may include: a first power supply voltage targeting a first reference level and used as an operating voltage for the controller and the memory device; and a second power supply voltage targeting a second reference level greater than the first reference level and used as an operating voltage for multiple interfaces.

[0012] The reference level range may include a first reference level range in which the first reference level is an intermediate level and a second reference level range in which the second reference level is an intermediate level. The level detector may enable a first detection signal in the detection signal when the first power supply voltage exceeds a maximum level of the first reference level range or drops below a minimum level of the first reference level range, and may enable a second detection signal in the detection signal when the second power supply voltage exceeds a maximum level of the second reference level range or drops below a minimum level of the second reference level range.

[0013] The protection operation component may enter the protection mode in response to activation of at least one of the first and second detection signals, and exit the protection mode in response to deactivation of both the first and second detection signals.

[0014] The protection operation component may generate operation information indicating whether the first detection signal has been enabled and whether the second detection signal has been enabled.

[0015] The memory system may further include: a voltage generator configured to receive the first power supply voltage and generate a third power supply voltage, the third power supply voltage targeting a third reference level and used as an operating voltage of the controller; receive the first power supply voltage and generate a fourth power supply voltage, the fourth power supply voltage targeting a fourth reference level and used as an operating voltage of the memory device; receive the second power supply voltage and generate a fifth power supply voltage, the fifth power supply voltage targeting a fifth reference level greater than the third reference level and used as an operating voltage of a circuit in the controller for driving multiple interfaces; receive the second power supply voltage and generate a sixth power supply voltage, the sixth power supply voltage targeting a sixth reference level greater than the fourth reference level and used as an operating voltage of a circuit in the memory device for driving multiple interfaces.

[0016] The reference level range may include a third reference level range in which the third reference level is an intermediate level, a fourth reference level range in which the fourth reference level is an intermediate level, a fifth reference level range in which the fifth reference level is an intermediate level, and a sixth reference level range in which the sixth reference level is an intermediate level. The level detector may enable a third detection signal in the detection signal when the third power supply voltage exceeds a maximum level of the third reference level range or drops below a minimum level of the third reference level range, may enable a fourth detection signal in the detection signal when the fourth power supply voltage exceeds a maximum level of the fourth reference level range or drops below a minimum level of the fourth reference level range, may enable a fifth detection signal in the detection signal when the fifth power supply voltage exceeds a maximum level of the fifth reference level range or drops below a minimum level of the fifth reference level range, and may enable a sixth detection signal in the detection signal when the sixth power supply voltage exceeds a maximum level of the sixth reference level range or drops below a minimum level of the sixth reference level range.

[0017] The protection operation component may enter the protection mode in response to activation of any one of the third to sixth detection signals, and may exit the protection mode in response to deactivation of all of the third to sixth detection signals.

[0018] The protection operation component may generate operation information indicating whether the third detection signal has been enabled, whether the fourth detection signal has been enabled, whether the fifth detection signal has been enabled, and whether the sixth detection signal has been enabled.

[0019] The power supply voltages may include: a seventh power supply voltage, which targets a seventh reference level and is used as an operating voltage of the controller; an eighth power supply voltage, which targets an eighth reference level and is used as an operating voltage of the memory device; a ninth power supply voltage, which targets a ninth reference level greater than the seventh reference level and is used as an operating voltage of a circuit in the controller for driving multiple interfaces; and a tenth power supply voltage, which targets a tenth reference level greater than the eighth reference level and is used as an operating voltage of a circuit in the memory device for driving multiple interfaces.

[0020] The reference level range may include a seventh reference level range in which the seventh reference level is an intermediate level, an eighth reference level range in which the eighth reference level is an intermediate level, a ninth reference level range in which the ninth reference level is an intermediate level, and a tenth reference level range in which the tenth reference level is an intermediate level. The level detector may enable the seventh detection signal in the detection signal when the seventh power supply voltage exceeds the maximum level of the seventh reference level range or drops below the minimum level of the seventh reference level range, may enable the eighth detection signal in the detection signal when the eighth power supply voltage exceeds the maximum level of the eighth reference level range or drops below the minimum level of the eighth reference level range, may enable the ninth detection signal in the detection signal when the ninth power supply voltage exceeds the maximum level of the ninth reference level range or drops below the minimum level of the ninth reference level range, and may enable the tenth detection signal in the detection signal when the tenth power supply voltage exceeds the maximum level of the tenth reference level range or drops below the minimum level of the tenth reference level range.

[0021] The protection operation component may enter the protection mode in response to activation of any one of the seventh to tenth detection signals, and may exit the protection mode in response to deactivation of all of the seventh to tenth detection signals.

[0022] The protection operation component may generate operation information indicating whether the seventh detection signal has been enabled, whether the eighth detection signal has been enabled, whether the ninth detection signal has been enabled, and whether the tenth detection signal has been enabled.

[0023] The multiple interfaces may include a command interface, an address interface, and a data interface, and the protection operation component may perform a second protection operation when entering a protection mode, wherein the second protection operation fixes the logic value of the command interface to a first logic value to stop the operation of the memory device, fixes the logic value of the data interface to a second logic value, and fixes the logic value of the address interface to a third logic value to prevent the memory device from being accessed.

[0024] The protection operation component may simultaneously start the first protection operation and the second protection operation when entering the protection mode.

[0025] In an embodiment, a memory system may include: a memory device; a controller including a volatile memory device and a non-volatile memory device configured to store a recovery code; and a plurality of interfaces located between the controller and the memory device. The controller may be configured to: detect whether a first voltage and a second voltage exceed respective reference level ranges, the first voltage being used to operate the controller and the memory device, and the second voltage being used to operate the plurality of interfaces; when it is detected that one of the first voltage and the second voltage exceeds the corresponding reference level range, enter a protection mode to store event information and snapshot information in the volatile memory device, the event information being associated with the protection mode, and the snapshot information being associated with the plurality of interfaces; and in response to the memory system exiting the protection mode and entering the recovery mode, receive a recovery code from the non-volatile memory device and receive event information and snapshot information from the volatile memory device, select at least one data item from among the data items stored in the memory device using the recovery code, the event information, and the snapshot information, and perform an error correction operation on the selected at least one data item.

[0026] According to the present disclosure, when the level variation of the power supply voltage supplied to the memory system exceeds the reference level range, a protection operation for ensuring the reliability of the memory device can be performed in hardware, and then when the level variation of the power supply voltage supplied from the outside is stable, a recovery operation for ensuring the reliability of the memory device can be performed in software.

[0027] Therefore, even when the level of the power supply voltage supplied to the memory system varies beyond the reference level range, there is an effect that the operational stability of the memory system can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a diagram showing a configuration of a memory system according to an embodiment.

[0029] Figure 2 is a diagram illustrating an example of characteristic operation of a memory system according to an embodiment.

[0030] Figure 3 is a diagram illustrating another example of a characteristic operation of a memory system according to an embodiment.

[0031] Figure 4 is a diagram illustrating another example of a characteristic operation of a memory system according to an embodiment.

[0032] Figure 5 is a diagram illustrating characteristic operations of a memory system according to an embodiment. DETAILED DESCRIPTION

[0033] The various examples of the present disclosure are described in more detail below with reference to the accompanying drawings. However, aspects and features of the present invention can be implemented in different ways to form other embodiments, including variations of any disclosed embodiment. Therefore, the present invention is not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the present disclosure is thorough and complete, and fully convey the present disclosure to those skilled in the art to which the present invention belongs. Throughout the disclosure, the same figure numerals refer to the same parts in the various figures and examples of the present disclosure. It is noted that references to "embodiment", "another embodiment" etc. do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily directed to the same (multiple) embodiments.

[0034] It will be understood that although the terms "first," "second," "third," etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. Thus, a first element in one instance may be referred to as a second or third element in another instance without indicating any changes to the element itself.

[0035] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated in order to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it is understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it will also be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present.

[0036] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form, and vice versa. Similarly, the indefinite articles "a" and "an" mean one or more unless it is clear from the language or context that only one is present.

[0037] It will be further understood that when the terms "include", "comprising", and "including" are used in this specification, the elements described are specified to exist, and the existence or addition of one or more other elements is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art in view of the present disclosure. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the present disclosure and the relevant technology, and should not be interpreted in an idealized or excessive formal sense unless explicitly indicated herein.

[0039] In the following description, in order to provide a thorough understanding of the present invention, many specific details are set forth. The present invention may be practiced without some or all of these specific details. In other cases, in order to avoid making the present invention unclear unnecessarily, well-known processing structures and / or processes are not described in detail.

[0040] It is also noted that unless explicitly stated otherwise, in some cases, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, as would be apparent to one skilled in the relevant art.

[0041] Embodiments of the present disclosure are described in detail below with reference to the drawings, wherein like reference numerals refer to like elements.

[0042] Figure 1 is a diagram for explaining the configuration of a memory system 110 according to an embodiment.

[0043] Reference Figure 1 , the memory system 110 may include a controller 130 and a memory device 150 .

[0044] The memory system 110 may operate in response to a request of the host 102, and in particular, may store data accessed by the host 102. In other words, the memory system 110 may be used as a primary storage device or an auxiliary storage device of the host 102. The memory system 110 may be manufactured as any of various types of storage devices according to a host interface protocol connected to the host 102. For example, the memory system 110 may be implemented as any of various types of storage devices such as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), an MMC in the form of a reduced size MMC (RS-MMC) or a micro MMC, an SD card in the form of a secure digital (SD), a mini SD or a micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card and / or a memory stick.

[0045] The memory system 110 may be implemented as a volatile memory device in the form of a dynamic random access memory (DRAM) and / or a static RAM (SRAM). In another embodiment, the memory system 110 may be implemented as a non-volatile memory device in the form of a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and / or a flash memory.

[0046] The memory system 110 may be manufactured as any of various types of packages such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and / or wafer-level stacked package (WSP).

[0047] The host 102 may be implemented by any of a variety of electronic devices. Examples of such devices include portable electronic devices such as mobile phones, MP3 players, and laptop computers, as well as larger electronic devices such as desktop computers, game consoles, televisions, and projectors. That is, the host 102 may be implemented by any of a variety of wired / wireless electronic devices.

[0048] The host 102 includes at least one operating system (OS), which generally manages and controls the functions and operations of the host 102, and provides interaction between the user who uses the memory system 110 and the host 102. Here, the operating system supports functions and operations corresponding to the user's purpose of use. According to the mobility of the host 102, the OS can be divided into, for example, a general-purpose operating system and a mobile operating system. In addition, according to the use environment, the general-purpose operating system in the operating system can be divided into a personal operating system and an enterprise operating system. For example, the personal operating system is a system specifically used to support service provision functions for ordinary users, and may include Windows, Chrome, etc., and the enterprise operating system is a system specifically used to ensure and support high performance, and may include Windows server, Linux, Unix, etc. In addition, the mobile operating system in the operating system is a system specifically used to provide mobility service provision functions and power saving functions to users to support the system, and may include Android, iOS, Windows Mobile, etc. The host 102 may include multiple operating systems, and the multiple operating systems are run to perform operations corresponding to user requests with the memory system 110. In addition, the host 102 transmits multiple commands corresponding to the user request to the memory system 110, so that the memory system 110 performs operations corresponding to the commands, that is, operations corresponding to the user request.

[0049] More specifically, the memory system 110 includes a memory device 150 storing data accessed by the host 102 and a controller 130 controlling storage of the data into the memory device 150 .

[0050] The controller 130 and the memory device 150 may be integrated into one semiconductor device. As an example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to form an SSD. When the memory system 110 is used as an SSD, the operation speed of the host 102 electrically connected to the memory system 110 may be further improved. In addition, the controller 130 and the memory device 150 may also be integrated into one semiconductor device to form a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media Card (e.g., SM and SMC), a Memory Stick, a Multimedia Card (e.g., MMC, RS-MMC, or Micro MMC), a Secure Digital (SD) card (e.g., SD, Mini SD, Micro SD, and SDHC), and / or a Universal Flash Storage (UFS) device.

[0051] In another example, the memory system 110 may constitute one or more of the following: a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional television, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, a device capable of transmitting and receiving information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, and various components constituting a computing system.

[0052] Even without power supply, the memory device 150 can retain stored data, and in particular, stores data provided from the host 102 through a write operation, and provides the stored data to the host 102 through a read operation. In addition, the memory device 150 may be a nonvolatile memory device such as a flash memory, and the flash memory may have a three-dimensional stacked structure.

[0053] The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide the host 102 with data read from the memory device 150, and store the data provided from the host 102 in the memory device 150. To this end, the controller 130 may control operations of the memory device 150, such as a read operation, a write operation, a program operation, and an erase operation.

[0054] In the following, the following description is given under the assumption that the memory device 150 is a flash memory having non-volatile characteristics. However, the memory device 150 implemented as a flash memory is only an embodiment. In another embodiment, the memory device 150 may be a dynamic random access memory (DRAM) and / or a static RAM (SRAM) having volatile characteristics, or may be a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), and / or a resistive RAM (RRAM) having non-volatile characteristics. Which type of memory is used to implement the memory device 150 may depend on the operating environment and / or the intended use or design specifications of the memory system 110.

[0055] The memory system 110 may use the power supply voltage VCC input from an external source or component as an operating voltage. That is, the operating voltage of each of the controller 130 and the memory device 150 in the memory system 110 is derived from the power supply voltage VCC.

[0056] The controller 130 may include a first internal storage device 1301 , a second internal storage device 1302 , a protection operation component 1303 , a recovery operation component 1304 , and a level detector 1305 .

[0057] The first internal storage device 1301 may have a volatile characteristic and may store data generated within the controller 130 .

[0058] The second internal storage device 1302 may have a non-volatile characteristic and may store a recovery code. The recovery code may be executed by the controller 130 to enter a recovery mode and perform a recovery operation on error data stored in the memory device 150.

[0059] The level detector 1305 may detect whether the level variation of the power supply voltage VCC exceeds a set reference level range, and generate a detection signal indicating a result of the detection.

[0060] The protection operation component 1303 may determine to enter and exit the protection mode in response to the detection signal generated by the level detector 1305. In addition, the protection operation component 1303 may perform a first protection operation upon entering the protection mode, the first protection operation generating event information about the state of the memory system 110, and generating a current logic value of each of the plurality of interfaces 10 connected to the memory device 150 as snapshot information, and storing the event information and the snapshot information in the first internal storage device 1301. In addition, the protection operation component 1303 may perform a second protection operation upon entering the protection mode, the second protection operation fixing each of the plurality of interfaces 10 connected to the memory device 150 to a set logic value. The protection operation component 1303 may start the first protection operation and the second protection operation simultaneously upon entering the protection mode.

[0061] The recovery operation component 1304 may receive a recovery code from the second internal storage device 1302 in response to exiting the protection mode, enter the recovery mode, receive event information and snapshot information from the first internal storage device 1301 , and then perform a recovery operation on the memory device 150 .

[0062] Figure 2 is a diagram illustrating an example of characteristic operations of the memory system 110 according to the embodiment.

[0063] Figure 5 is a diagram illustrating characteristic operations of the memory system 110 according to an embodiment.

[0064] Reference Figure 2 , the memory system 110 may include a controller 130 and a memory device 150 , and the controller 130 and the memory device 150 may be electrically connected through a plurality of interfaces 10 .

[0065] The controller 130 may include a first internal storage device 1301 , a second internal storage device 1302 , a protection operation component 1303 , a recovery operation component 1304 , and a level detector 1305 .

[0066] The first internal storage device 1301 may have a volatile characteristic and may store data generated within the controller 130 , for example, event information EVEN and snapshot information SNAP generated by the protection operation component 1303 .

[0067] In addition, the second internal storage device 1302 may have a non-volatile characteristic and may store a recovery code RVCD. The recovery code RVCD may be executed by the controller 130 to enable the recovery operation component 1304 to enter a recovery mode and perform a recovery operation on error data stored in the memory device 150.

[0068] Specifically, the recovery code RVCD may be stored in the second internal storage device 1302 during the manufacture of the memory system 110. That is, the recovery code RVCD may be a program code written in advance by a designer during the manufacture of the memory system 110, and the recovery code is then used for the recovery operation of the memory system 110. Therefore, if the content of the recovery code RVCD is changed after being written during the manufacture of the memory system 110, a normal recovery operation may not be performed. That is, when the content of the recovery code RVCD is changed for any reason during the operation of the memory system 110, even when the recovery code RVCD is run to perform a recovery operation on the memory system 110, the memory system 110 cannot be recovered normally.

[0069] Therefore, the second internal storage device 1302 storing the recovery code RVCD may be implemented as a memory device having a non-volatile characteristic, for example, a read-only memory (ROM). That is, when the recovery code RVCD is stored in the second internal storage device 1302 implemented as a ROM, there is no realistic possibility that the content of the recovery code RVCD is changed due to the operation of the memory system 110 or during the operation of the memory system 110. For reference, the second internal storage device 1302 implemented as a ROM may store a program code such as a boot code, the content of which may be prohibited from being changed after being written during the manufacture of the memory system 110, as well as the recovery code RVCD.

[0070] In some embodiments, the memory system 110 may receive two power supply voltages VCC and VCCQ from an external source and use them as operating voltages.

[0071] The first power supply voltage VCC may target a first reference level and may be used as an operating voltage of the controller 130 and the memory device 150. The second power supply voltage VCCQ may target a second reference level higher than the first reference level and may be used as an operating voltage of a plurality of interfaces 10 for transmitting signals between the memory device 150 and the controller 130. Therefore, each of the first internal storage device 1301, the second internal storage device 1302, and the protection operation component 1303 may receive the first power supply voltage VCC and use the first power supply voltage VCC as an operating voltage. The plurality of interfaces 10 for electrically connecting between the controller 130 and the memory device 150 may receive the second power supply voltage VCCQ and use the second power supply voltage VCCQ as an operating voltage.

[0072] In some embodiments, the level detector 1305 can detect whether the level change of the first power supply voltage VCC exceeds the set first reference level range, and generate a first detection signal DET corresponding to the detection result. <1> In addition, the level detector 1305 can detect whether the level change of the second power supply voltage VCCQ exceeds the set second reference level range, and generate a second detection signal DET corresponding to the detection result. <2> .

[0073] More specifically, refer to Figure 2 and Figure 5Preferably, the first power supply voltage VCC substantially maintains the first reference level REF_TARGET <1> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply; therefore, the voltage level of the first power supply voltage VCC may vary. The first reference level range may be composed of a maximum first reference level REF_MAX <1> and the minimum first reference level REF_MIN <1> To define, the REF_MAX <1> and REF_MIN <1> Each distance in REF_MAX <1> and REF_MIN <1> The first reference level REF_TARGET in the middle <1> There is a set level difference.

[0074] In addition, preferably, the second power supply voltage VCCQ substantially maintains the second reference level REF_TARGET <2> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply; therefore, the voltage level of the second power supply voltage VCCQ may vary. The second reference level range can be composed of a maximum second reference level REF_MAX <2> and the minimum second reference level REF_MIN <2> To define, the REF_MAX <2> and REF_MIN <2> Each distance in REF_MAX <2> and REF_MIN <2> The second reference level REF_TARGET in the middle <2> There is a set level difference.

[0075] As an example, Figure 5 shows the first reference level REF_TARGET <1> and the second reference level REF_TARGET <2> Basically the same, but the second reference level REF_TARGET <2> Can be higher than the first reference level REF_TARGET <1> Because it is assumed that the second reference level REF_TARGET <2> Higher than the first reference level REF_TARGET <1> , so the minimum second reference level REF_MIN <2> Can be higher, equal to or lower than the maximum first reference level REF_MAX <1> .

[0076] To ensure stable operation of the memory system 110, it is important that any variation in the level of the first power supply voltage VCC does not exceed the first reference level range. It is also important that any variation in the level of the second power supply voltage VCCQ does not exceed the second reference level range.

[0077] That is, when the first reference level REF_TARGET <1> The level of the target first power supply voltage VCC is at the maximum first reference level REF_MAX <1> and the minimum first reference level REF_MIN <1> , the controller 130 and the memory device 150 using the first power supply voltage VCC as an operating voltage can operate stably. However, when the level of the first power supply voltage VCC rises to exceed the maximum first reference level REF_MAX <1> or drops below the minimum first reference level REF_MIN <1> When the first power supply voltage VCC is used as the operating voltage, the controller 130 and the memory device 150 may not be stably operated.

[0078] Similarly, when the second reference level REF_TARGET <2> The level of the target second power supply voltage VCCQ is at the maximum second reference level REF_MAX <2> and the minimum second reference level REF_MIN <2> , the plurality of interfaces 10 using the second power supply voltage VCCQ as the operating voltage can operate stably. However, when the level of the second power supply voltage VCCQ rises to exceed the maximum second reference level REF_MAX <2> or drops below the minimum second reference level REF_MIN <2> When the second power supply voltage VCCQ is used as an operating voltage, the plurality of interfaces 10 may not be able to operate stably.

[0079] When the level change of the first power supply voltage VCC exceeds the first reference level range, that is, when the level change of the first power supply voltage VCC rises to exceed the maximum first reference level REF_MAX <1> or drops below the minimum first reference level REF_MIN <1> When the level detector 1305 can enable the first detection signal DET <1> When the level variation of the first power voltage VCC is maintained within the first reference level range, the level detector 1305 may disable the first detection signal DET <1> .

[0080] When the level change of the second power supply voltage VCCQ exceeds the second reference level range, that is, when the level change of the second power supply voltage VCCQ rises to exceed the maximum second reference level REF_MAX <2> or drops below the minimum second reference level REF_MIN <2> When the level detector 1305 can enable the second detection signal DET <2> When the level variation of the second power voltage VCCQ is maintained within the second reference level range, the level detector 1305 may disable the second detection signal DET <2> .

[0081] Reference Figure 2The protection operation component 1303 may respond to the first detection signal DET generated by the level detector 1305 <1> and the second detection signal DET <2> That is, the protection operation component 1303 can respond to the first detection signal DET generated by the level detector 1305. <1> and the second detection signal DET <2> In addition, the protection operation component 1303 can respond to the first detection signal DET generated by the level detector 1305. <1> and the second detection signal DET <2> Deactivate both to exit protection mode.

[0082] In addition, the protection operation component 1303 may perform a first protection operation when entering the protection mode, the first protection operation generating event information EVEN about the state of the memory system 110 and generating the current logic value of each of the plurality of interfaces 10 as snapshot information SNAP, and storing the event information EVEN and the snapshot information SNAP in the first internal storage device 1301. In addition, the protection operation component 1303 may perform a second protection operation when entering the protection mode, the second protection operation fixing each of the plurality of interfaces 10 to a set logic value. The protection operation component 1303 may generate a logic fixing signal (LFS) when entering the protection mode of the second protection operation, and transmit the logic fixing signal (LFS) to each of the plurality of interfaces 10. Each of the plurality of interfaces 10 may be fixed to a set logic value in response to the logic fixing signal (LFS). In some embodiments, the protection operation component 1303 may start the first protection operation and the second protection operation simultaneously when entering the protection mode.

[0083] The first protection operation performed by the protection operation component 1303 is described in detail as follows.

[0084] The protection operation component 1303 may be configured to generate a detection signal DET<1:2> generated by the level detector 1305, that is, a first detection signal DET <1> and the second detection signal DET <2> When entering the protection mode, operation information OPI and execution information PEI are generated, the operation information OPI is related to the operation of entering the protection mode, and the execution information PEI indicates whether the second protection operation has been completed. Further, the protection operation component 1303 can store the operation information OPI and the execution information PEI in the first internal storage device 1301 as event information EVEN.

[0085] The operation information OPI may represent all information that can be collected and is related to the operation of entering the protection mode. <1> The deactivation and second detection signal DET <2> When the protection operation component 1303 enters the protection mode due to the first detection signal DETQ, the operation information OPI may include information indicating that the level change of the first power supply voltage VCC is normal and the level change of the second power supply voltage VCCQ is abnormal. <1> is enabled for a period of time and then disabled and the second detection signal DET <2> When the protection mode is entered by being enabled and then continuously maintained in the enabled state, the operation information OPI may include information indicating the following situation: an error of an instantaneous change in the level of the first power supply voltage VCC has occurred, and the level change of the second power supply voltage VCCQ is abnormal. The protection operation component 1303 may be based on the first detection signal DET <1> and the second detection signal DET <2> To generate the operation information OPI. Therefore, the operation information OPI can indicate the first detection signal DET <1> Whether it has been enabled and the second detection signal DET <2> Whether it has been enabled.

[0086] In some embodiments, the execution information PEI may be information indicating that the execution of the second protection operation of fixing each of the plurality of interfaces 10 to the set logic value when entering the protection mode has been normally performed. That is, entering the protection mode indicates a state in which at least one of the first power supply voltage VCC and the second power supply voltage VCCQ has undergone an abnormal level change. Therefore, it cannot be guaranteed that the second protection operation of fixing each of the plurality of interfaces 10 to the set logic value in response to the logic fixed signal (LFS) transmitted from the protection operation component 1303 has been normally performed. For example, even if the protection operation component 1303 has transmitted the logic fixed signal (LFS) to each of the plurality of interfaces 10, each of the plurality of interfaces 10 may not be fixed to the set logic value due to an abnormal change in the level of the second power supply voltage VCCQ, which is the operating voltage of the plurality of interfaces 10. Therefore, the execution information PEI may indicate whether each of the plurality of interfaces 10 has been fixed to the set logic value.

[0087] In some embodiments, the controller 130 may further include a buffer 1306 for buffering signals to be transmitted to the memory device 150 through the plurality of interfaces 10. The protection operation component 1303 may generate a logic value of the signal buffered by the buffer 1306 as snapshot information SNAP when entering the protection mode, and store the snapshot information SNAP in the first internal storage device 1301.

[0088] For example, the time to enter the protection mode may be the time when the signal buffered by the buffer 1306 is being transmitted to the memory device 150 while being carried on the plurality of interfaces 10. In this case, the snapshot information SNAP may include the logic value of the signal carried on each of the plurality of interfaces 10. For another example, the time to enter the protection mode may be before the signal buffered by the buffer 1306 is carried on the plurality of interfaces 10. In this case, the snapshot information SNAP may include the logic value of the signal to be carried on each of the plurality of interfaces 10, which is different from the signal carried on each of the plurality of interfaces 10.

[0089] In some embodiments, the plurality of interfaces 10 for connecting between the controller 130 and the memory device 150 may include a command interface C_I / F, an address interface A_I / F, and a data interface D_I / F.

[0090] The command interface C_I / F may be a transmission path through which the controller 130 generates a command signal for controlling the operation of the memory device 150 and transmits the command signal to the memory device 150. For example, the controller 130 may generate a write command signal, a read command signal, an erase command signal, etc., transmit the generated command signal to the memory device 150, and use the command interface C_I / F as a path for transmitting such command signals. For reference, a "CE" node included in the command interface C_I / F may indicate a "chip enable" node, a "WE / RE" node included in the command interface C_I / F may indicate a "write enable / read enable" node, and various types of command signals transmitted from the controller 130 to the memory device 150 may be classified by a logical combination of signals carried on each of the "CE" node and the "WE / RE" node. As an example, Figure 2 It is shown that only a “CE” node and a “WE / RE” node are included in the command interface C_I / F, but any other types of nodes may be included in the command interface C_I / F according to the type or design specification of the memory device 150 .

[0091] The address interface A_I / F may be a transmission path of an address signal transmitted from the controller 130 to the memory device 150 in order to select some of the storage areas in the memory device 150 and perform a command operation. For example, the controller 130 may transmit an address signal to the memory device 150 together with a write command signal, a read command signal, an erase command signal, etc. to specify a storage area in the memory device 150 where a command operation is performed, and use the address interface A_I / F as a path for transmitting the address signal. As an example, Figure 2It is shown that only one node ADDR is included in the address interface A_I / F, but one or more nodes may be included in the address interface A_I / F. The number of nodes to be included in the address interface A_I / F may depend on the type of the memory device 150 and its design specifications.

[0092] The data interface D_I / F may be a transmission path through which data is transmitted between the controller 130 and the memory device 150. For example, the controller 130 may transmit write data together with a write command signal to the memory device 150. In addition, the memory device 150 may perform a read operation in response to a read command signal received from the controller 130, and then transmit read data obtained by performing the read operation to the controller 130. The data interface D_I / F may be used as a path for transmitting write data and read data. As an example, Figure 2 It is shown that only one node DATA is included in the data interface D_I / F, but one or more nodes may be included in the data interface D_I / F. The number of nodes to be included in the data interface D_I / F may depend on the type of the memory device 150 and its design specifications.

[0093] Reference Figure 5 , it can be assumed that the level change of at least one of the first power supply voltage VCC and the second power supply voltage VCCQ drops below the minimum level REF_MIN of the corresponding reference level range <1> or REF_MIN <2> (S10). Therefore, the level detector 1305 may enable the first detection signal DET <1> and the second detection signal DET <2> Therefore, the protection operation component 1303 can respond to the enabled first detection signal DET <1> and / or the second detection signal DET <2> And enter the protection mode. In addition, as described above, the protection operation component 1303 can perform a first protection operation when entering the protection mode, and the first protection operation generates event information EVEN and snapshot information SNAP, and stores the event information EVEN and snapshot information SNAP in the first internal storage device 1301. In addition, the protection operation component 1303 can perform a second protection operation when entering the protection mode, and the second protection operation fixes each of the multiple interfaces 10 to a set logical value. The first protection operation and the second protection operation can be started simultaneously when entering the protection mode. Figure 5 In the example shown, it can be seen that operation S30 (ie, the first protection operation) of generating and storing snapshot information SNAP in the first internal storage device 1301 and steps S21 to S23 of the second protection operation start simultaneously.

[0094] In the following, reference is made to Figure 2 and Figure 5The second protection operations S21 to S23 performed by the protection operation component 1303 are described in detail.

[0095] As described above, the plurality of interfaces 10 may include a command interface C_I / F, an address interface A_I / F, and a data interface D_I / F. The protection operation component 1303 may perform a second protection operation when entering a protection mode, the second protection operation fixing the logic value of the command interface C_I / F to a first logic value to stop the operation of the memory device 150 (S21). That is, the command interface C_I / F may be fixed to the first logic value in response to a logic fix signal (LFS) received from the protection operation component 1303 when entering the protection mode. Fixing the command interface C_I / F to the first logic value may indicate that a command signal for stopping the operation of the memory device 150 is controlled to be transmitted to the memory device 150 while being carried on the command interface C_I / F. Figure 5 In the example shown, the operation of fixing the "CE" node in the command interface C_I / F to logic "high" and fixing the "WE / RE" node to logic "low" when entering the protection mode may be an operation of fixing the command interface C_I / F to a first logic value. In some embodiments, stopping the operation of the memory device 150 may indicate a state in which the memory device 150 does not perform any operation, for example, indicating that when the memory device 150 is performing a write operation, the execution of the write operation is immediately stopped.

[0096] In addition, the protection operation component 1303 can perform a second protection operation when entering the protection mode, and the second protection operation fixes the logic value of the data interface D_I / F to a second logic value (S22). That is, the data interface D_I / F can be fixed to the second logic value in response to a logic fix signal (LFS) received from the protection operation component 1303 when entering the protection mode. Fixing the data interface D_I / F to the second logic value can mean fixing the logic value of the signal carried on the data interface D_I / F to a logic "high" or a logic "low". Figure 5 In the example shown, the operation of fixing one or more “DATA” nodes included in the data interface D_I / F to logic “high” when entering the protection mode may be an operation of fixing the data interface D_I / F to a second logic value.

[0097] In addition, the protection operation component 1303 can perform a second protection operation when entering the protection mode, which fixes the logic value of the address interface A_I / F to a third logic value, which basically prevents the memory device 150 from being accessed (S23). That is, the address interface A_I / F can be fixed to the third logic value in response to a logic fix signal (LFS) received from the protection operation component 1303 when entering the protection mode. Fixing the address interface A_I / F to the third logic value can mean that any storage area in the memory device 150 is controlled not to be selected and inaccessible (out of range) by the value of the address signal carried on the address interface A_I / F. Figure 5 In the example shown, this may be the following operation: all "ADDR" nodes in the address interface A_I / F are fixed to logic "high" so that the values ​​of the address signals transmitted to the memory device 150 through the address interface A_I / F when entering the protection mode are all "0xF". In some embodiments, controlling any storage area in the memory device 150 to be inaccessible (out of range) by the value of the address signal carried on the address interface A_I / F may mean that the address interface A_I / F carries the value of the address signal that substantially prevents any storage area in the memory device 150 from being selected. For example, assuming that the memory device 150 includes a storage area of ​​1GB, when the address interface A_I / F carries the value of the address signal for selecting a storage area corresponding to 2GB, the memory device 150 cannot select the storage area in response to the corresponding address. Therefore, the storage area cannot be accessed normally.

[0098] Re-reference Figure 2 , the recovery operation component 1304 can enter the recovery mode by receiving the recovery code RVCD from the second internal storage device 1302 in response to exiting the protection mode. In addition, in the state of entering the recovery mode, the recovery operation component 1304 can receive event information EVEN and snapshot information SNAP from the first internal storage device 1301, and perform a recovery operation on the memory device 150.

[0099] Specifically, the protection operation component 1303 may respond to the first detection signal DET <1> and the second detection signal DET <2> The protection mode is exited by deactivating both, a protection mode exit signal PMEX indicating exit from the protection mode is generated, and the protection mode exit signal PMEX is transmitted to the recovery operation component 1304 .

[0100] Therefore, in response to the protection mode exit signal PMEX generated by the protection operation component 1303, the recovery operation component 1304 can enter the recovery mode by receiving the recovery code RVCD from the second internal storage device 1302. Subsequently, in the recovery mode, the recovery operation component 1304 can perform a recovery operation in response to the event information EVEN and the snapshot information SNAP. The recovery operation may include a classification operation and an error correction operation. The classification operation may include classifying, i.e., identifying, data stored in the memory device 150 in which the probability of an error occurring is higher than a set reference probability. The error correction operation may include correcting errors occurring in the data identified by the classification operation.

[0101] The principle is as follows, where the recovery operation component 1304 can perform classification operations through event information EVEN and snapshot information SNAP.

[0102] As described above, the event information EVEN may include operation information OPI and execution information PEI.

[0103] The operation information OPI may represent all information that can be collected and is related to the operation of entering the protection mode. Therefore, the recovery operation component 1304 may determine the reason for entering the protection mode through the operation information OPI. In some embodiments, by determining which voltage level of the first power supply voltage VCC and the second power supply voltage VCCQ changes abnormally to cause the entry into the protection mode, it may be determined whether there is a high probability of an error occurring in the controller 130 and the memory device 150, or whether it is likely that an unexpected signal is transmitted through the multiple interfaces 10. When the protection mode has been entered due to an abnormal fluctuation in the level of the first power supply voltage VCC, it is likely that an error has occurred in the operation being performed in the controller 130 and the memory device 150 using the first power supply voltage VCC as an operating voltage. On the other hand, when the protection mode has been entered due to an abnormal change in the level of the second power supply voltage VCCQ, it is likely that the signals carried on the multiple interfaces 10 using the second power supply voltage VCCQ as an operating voltage may represent an unexpected logic value.

[0104] In some embodiments, the execution information PEI may indicate whether the second protection operation of fixing each of the plurality of interfaces 10 to the set logic value has been normally performed when entering the protection mode. Therefore, the recovery operation component 1304 may determine whether the second protection operation has been normally performed through the execution information PEI. When it is determined that the second protection operation has been normally performed when entering the protection mode, the possibility that the signals carried on the plurality of interfaces 10 will affect the operation of the memory device 150 may be greatly reduced. On the other hand, when it is determined that the second protection operation has not been normally performed when entering the protection mode, the possibility that the signals carried on the plurality of interfaces 10 will greatly affect the operation of the memory device 150 may increase.

[0105] In some embodiments, the snapshot information SNAP may include the logic values ​​of the signals carried or to be carried on the plurality of interfaces 10. Therefore, the recovery operation component 1304 may determine the operation being performed or to be performed by the memory device 150 through the snapshot information SNAP. In particular, the recovery operation component 1304 may determine the command operation being performed or to be performed by the memory device 150 through the logic value of the command signal in the snapshot information SNAP. Similarly, the recovery operation component 1304 may determine which storage area of ​​the memory device 150 is performing or will perform the command operation through the logic value of the address signal in the snapshot information SNAP.

[0106] In this way, the recovery operation component 1304 can perform a classification operation through the event information EVEN and the snapshot information SNAP, and the classification operation classifies the data stored in the memory device 150, in which the probability of an error occurring is higher than the set reference probability. After performing the classification operation, the recovery operation component 1304 can perform an error correction operation, which corrects the error occurring in the data identified by the classification operation. The error correction operation may include: an operation of confirming whether an error has actually occurred in the data identified by the classification operation; and an operation of correcting the error when an error has occurred. The operation of correcting the error may be successful or may not be successful. The error correction operation of the recovery operation component 1304 can be performed according to known techniques, for example, according to an error correction technique using coded modulation such as: low-density parity check (LDPC) code, Bose-Chadhouli-Hokungum (BCH) code, turbo code, Reed-Solomon code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM) and block coded modulation (BCM); however, any suitable error correction technique can be used. Furthermore, the recovery operations component 1304 may include any circuit, module, system, or means for performing error correction.

[0107] Figure 3is a diagram illustrating another example of a characteristic operation of the memory system 110 according to an embodiment.

[0108] Figure 3 The following configuration is shown: the memory system 110 generates four power supply voltages VCC1, VCCQ1, VCC2, and VCCQ2 in response to two power supply voltages VCC and VCCQ input from an external source, and then uses the four power supply voltages VCC1, VCCQ1, VCC2, and VCCQ2 as operating voltages. That is, Figure 2 The memory system 110 and Figure 3 The main difference in configuration between the memory systems 110 in FIG. 1 is the number of power supply voltages used as operating voltages. Figure 3 When configuring and operating the memory system 110 in FIG. 1 , this description focuses on the configuration and operation of the memory system 110 in FIG. Figure 2 The differences in the memory system 110.

[0109] Reference Figure 3 , the memory system 110 may include a voltage generator 160 that receives a first power voltage VCC and a second power voltage VCCQ from an external source and generates a third power voltage VCC1, a fourth power voltage VCC2, a fifth power voltage VCCQ1, and a sixth power voltage VCCQ2.

[0110] Specifically, the voltage generator 160 may receive the first power supply voltage VCC and generate a third power supply voltage VCC1, which targets a third reference level and may be used as an operating voltage of the controller 130 in the memory system 110. In addition, the voltage generator 160 may receive the first power supply voltage VCC and generate a fourth power supply voltage VCC2, which targets a fourth reference level and may be used as an operating voltage of the memory device 150 in the memory system 110. In addition, the voltage generator 160 may receive the second power supply voltage VCCQ and generate a fifth power supply voltage VCCQ1, which targets a fifth reference level higher than the third reference level and may be used as an operating voltage of a circuit in the controller 130 for driving a plurality of interfaces 10 for transmitting signals between the memory device 150 and the controller 130. In addition, the voltage generator 160 can receive the second power supply voltage VCCQ and generate a sixth power supply voltage VCCQ2, which targets a sixth reference level higher than the fourth reference level and can be used as an operating voltage of a circuit in the memory device 150 for driving a plurality of interfaces 10 for transmitting signals between the memory device 150 and the controller 130.

[0111] Therefore, each of the first internal storage device 1301, the second internal storage device 1302, and the protection operation component 1303 in the controller 130 can receive the third power supply voltage VCC1 and use the third power supply voltage VCC1 as an operation voltage. In addition, the circuit for driving the plurality of interfaces 10 for connecting between the controller 130 and the memory device 150 in the memory device 150 can receive the fifth power supply voltage VCCQ1 and use the fifth power supply voltage VCCQ1 as an operation voltage. In addition, the memory device 150 can receive the fourth power supply voltage VCC2 and use the fourth power supply voltage VCC2 as an operation voltage. In addition, the circuit for driving the plurality of interfaces 10 for connecting between the memory device 150 and the controller 130 in the memory device 150 can receive the sixth power supply voltage VCCQ2 and use the sixth power supply voltage VCCQ2 as an operation voltage.

[0112] The level detector 1305 in the controller 130 can detect whether the level change of the third power supply voltage VCC1 exceeds the set third reference level range, and generate a third detection signal DET corresponding to the detection result. <3> In addition, the level detector 1305 can detect whether the level change of the fourth power supply voltage VCC2 exceeds the set fourth reference level range, and generate a fourth detection signal DET corresponding to the detection result. <4> In addition, the level detector 1305 can detect whether the level change of the fifth power supply voltage VCCQ1 exceeds the set fifth reference level range, and generate a fifth detection signal DET corresponding to the detection result. <5> In addition, the level detector 1305 can detect whether the level change of the sixth power supply voltage VCCQ2 exceeds the set sixth reference level range, and generate a sixth detection signal DET corresponding to the detection result. <6> .

[0113] More specifically, refer to Figure 3 and Figure 5 Preferably, the third power supply voltage VCC1 substantially maintains the third reference level REF_TARGET <3> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply, and the voltage level of the third power supply voltage VCC1 may fluctuate. The third reference level range may be composed of a maximum third reference level REF_MAX <3> and the minimum third reference level REF_MIN <3> To define, the REF_MAX <3> and REF_MIN <3> Each distance in REF_MAX <3> and REF_MIN <3> The third reference level REF_TARGET in the middle <3> There is a set level difference.

[0114] In addition, preferably, the fourth power supply voltage VCC2 substantially maintains the fourth reference level REF_TARGET <4> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply, and the voltage level of the fourth power supply voltage VCC2 may fluctuate. The fourth reference level range may be composed of a maximum fourth reference level REF_MAX <4> and the minimum fourth reference level REF_MIN <4> To define, the REF_MAX <4> and REF_MIN <4> Each distance in REF_MAX <4> and REF_MIN <4> The fourth reference level REF_TARGET in the middle <4> There is a set level difference.

[0115] In addition, preferably, the fifth power supply voltage VCCQ1 substantially maintains the fifth reference level REF_TARGET <5> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply, and the voltage level of the fifth power supply voltage VCCQ1 may fluctuate. The fifth reference level range may be composed of a maximum fifth reference level REF_MAX <5> and the minimum fifth reference level REF_MIN <5> To define, the REF_MAX <5> and REF_MIN <5> Each distance in REF_MAX <5> and REF_MIN <5> The fifth reference level REF_TARGET in the middle <5> There is a set level difference.

[0116] In addition, preferably, the sixth power supply voltage VCCQ2 substantially maintains the sixth reference level REF_TARGET <6> , but this may not be achieved due to various reasons such as noise, static electricity and unstable power supply, and the voltage level of the sixth power supply voltage VCCQ2 may fluctuate. The sixth reference level range may be composed of a maximum sixth reference level REF_MAX <6> and the minimum sixth reference level REF_MIN <6> To define, the REF_MAX <6> and REF_MIN <6> Each distance in REF_MAX <6> and REF_MIN <6> The sixth reference level REF_TARGET in the middle <6> There is a set level difference.

[0117] As an example, Figure 5The third reference level REF_TARGET is shown <3> , fourth reference level REF_TARGET <4> , fifth reference level REF_TARGET <5> and the sixth reference level REF_TARGET <6> has substantially the same level, but the fifth reference level REF_TARGET <5> Can be higher than the third reference level REF_TARGET <3> , the sixth reference level REF_TARGET <6> Can be higher than the fourth reference level REF_TARGET <4> Because it is assumed that the fifth reference level REF_TARGET <5> Higher than the third reference level REF_TARGET <3> , so the minimum fifth reference level REF_MIN <5> Can be higher, equal to or lower than the maximum third reference level REF_MAX <3> Similarly, since it is assumed that the sixth reference level REF_TARGET <6> Higher than the fourth reference level REF_TARGET <4> , so the minimum sixth reference level REF_MIN <6> It can be higher, equal to or lower than the maximum fourth reference level REF_MAX <4> In addition, the third reference level REF_TARGET <3> and the fourth reference level REF_TARGET <4> can have substantially the same level or different levels. Similarly, the fifth reference level REF_TARGET <5> and the sixth reference level REF_TARGET <6> They may have substantially the same level or different levels.

[0118] To ensure stable operation of the memory system 110, it is important that any variation in the level of the third power supply voltage VCC1 does not exceed the third reference level range. It is also important that any variation in the level of the fourth power supply voltage VCC2 does not exceed the fourth reference level range. It is also important that any variation in the level of the fifth power supply voltage VCCQ1 does not exceed the fifth reference level range. It is also important that any variation in the level of the sixth power supply voltage VCCQ2 does not exceed the sixth reference level range.

[0119] That is, when the third reference level REF_TARGET <3> The target third power supply voltage VCC1 has a level at the maximum third reference level REF_MAX <3> and the minimum third reference level REF_MIN <3> , it can be seen that the controller 130 using the third power supply voltage VCC1 as the operating voltage operates stably. However, when the level of the third power supply voltage VCC1 rises to exceed the maximum third reference level REF_MAX <3> or falls below the minimum third reference level REF_MIN <3> When the controller 130 uses the third power supply voltage VCC1 as an operating voltage, it may not be able to stably operate.

[0120] When the fourth reference level REF_TARGET <4> The target fourth power supply voltage VCC2 has a level at the maximum fourth reference level REF_MAX <4> and the minimum fourth reference level REF_MIN <4> , it can be seen that the memory device 150 using the fourth power supply voltage VCC2 as the operating voltage operates stably. However, when the level of the fourth power supply voltage VCC2 rises to exceed the maximum fourth reference level REF_MAX <4> or drops below the minimum fourth reference level REF_MIN <4> When the fourth power supply voltage VCC2 is used as the operating voltage, the memory device 150 may not be stably operated.

[0121] Similarly, when the fifth reference level REF_TARGET <5> The level of the fifth power supply voltage VCCQ1 is at the maximum fifth reference level REF_MAX <5> and the minimum fifth reference level REF_MIN <5> , it can be seen that the circuit for driving the plurality of interfaces 10 using the fifth power supply voltage VCCQ1 as an operating voltage in the controller 130 operates stably. However, when the level of the fifth power supply voltage VCCQ1 rises to exceed the maximum fifth reference level REF_MAX <5> or falls below the minimum fifth reference level REF_MIN <5> When the fifth power supply voltage VCCQ1 is used as an operating voltage, a circuit for driving the plurality of interfaces 10 in the controller 130 may not be stably operated.

[0122] When the sixth reference level REF_TARGET <6> The level of the sixth power supply voltage VCCQ2 is at the maximum sixth reference level REF_MAX <6> and the minimum sixth reference level REF_MIN <6> , it can be seen that the circuit for driving the plurality of interfaces 10 using the sixth power supply voltage VCCQ2 as an operating voltage in the memory device 150 operates stably. However, when the level of the sixth power supply voltage VCCQ2 rises to exceed the maximum sixth reference level REF_MAX <6> or falls below the minimum sixth reference level REF_MIN <6> When the sixth power supply voltage VCCQ2 is used as an operating voltage, a circuit for driving the plurality of interfaces 10 in the memory device 150 may not be stably operated.

[0123] When the level change of the third power supply voltage VCC1 exceeds the third reference level range, that is, when the level change of the third power supply voltage VCC1 rises to exceed the maximum third reference level REF_MAX <3> or falls below the minimum third reference level REF_MIN <3> When the level detector 1305 can enable the third detection signal DET <3> When the level variation of the third power supply voltage VCC1 does not exceed the third reference level range, that is, when the level variation of the third power supply voltage VCC1 only rises to the maximum third reference level REF_MAX <3> Or just drop to the minimum third reference level REF_MIN <3> When the level detector 1305 can disable the third detection signal DET <3> .

[0124] When the level variation of the fourth power supply voltage VCC2 exceeds the fourth reference level range, that is, when the level variation of the fourth power supply voltage VCC2 rises to exceed the maximum fourth reference level REF_MAX <4> or drops below the minimum fourth reference level REF_MIN <4> When the level detector 1305 can enable the fourth detection signal DET <4> When the level variation of the fourth power supply voltage VCC2 does not exceed the fourth reference level range, that is, when the level variation of the fourth power supply voltage VCC2 only rises to the maximum fourth reference level REF_MAX <4> Or just drop to the minimum fourth reference level REF_MIN <4> When the level detector 1305 can disable the fourth detection signal DET <4> .

[0125] When the level variation of the fifth power supply voltage VCCQ1 exceeds the fifth reference level range, that is, when the level variation of the fifth power supply voltage VCCQ1 rises to exceed the maximum fifth reference level REF_MAX <5> or falls below the minimum fifth reference level REF_MIN <5> When the level detector 1305 can enable the fifth detection signal DET <5> When the level variation of the fifth power supply voltage VCCQ1 does not exceed the fifth reference level range, that is, when the level variation of the fifth power supply voltage VCCQ1 only rises to the maximum fifth reference level REF_MAX <5> Or just drop to the minimum fifth reference level REF_MIN <5> When the level detector 1305 can disable the fifth detection signal DET <5> .

[0126] When the level variation of the sixth power supply voltage VCCQ2 exceeds the sixth reference level range, that is, when the level variation of the sixth power supply voltage VCCQ2 rises to exceed the maximum sixth reference level REF_MAX <6> or falls below the minimum sixth reference level REF_MIN <6> When the level detector 1305 can enable the sixth detection signal DET <6> When the level variation of the sixth power supply voltage VCCQ2 does not exceed the sixth reference level range, that is, when the level variation of the sixth power supply voltage VCCQ2 only rises to the maximum sixth reference level REF_MAX <6> Or just drop to the minimum sixth reference level REF_MIN <6> When the level detector 1305 can disable the sixth detection signal DET <6> .

[0127] Re-reference Figure 3 , the protection operation component 1303 may respond to the third detection signal DET generated by the level detector 1305 <3> , the fourth detection signal DET <4> , the fifth detection signal DET <5> and the sixth detection signal DET <6> That is, the protection operation component 1303 can respond to the third detection signal DET <3> , the fourth detection signal DET <4> , the fifth detection signal DET <5> and the sixth detection signal DET <6> In addition, the protection operation component 1303 can respond to all the third detection signals DET generated by the level detector 1305. <3> , the fourth detection signal DET <4> , the fifth detection signal DET <5> and the sixth detection signal DET <6> Exit protection mode by deactivating the

[0128] Furthermore, the protection operation component 1303 may perform a first protection operation upon entering the protection mode, the first protection operation generating event information EVEN regarding the state of the memory system 110 and generating a current logic value of each of the plurality of interfaces 10 as snapshot information SNAP, and storing the event information EVEN and the snapshot information SNAP in the first internal storage device 1301. Furthermore, the protection operation component 1303 may perform a second protection operation upon entering the protection mode, the second protection operation fixing each of the plurality of interfaces 10 to a set logic value.

[0129] Can be Figure 3 The first protection operation and the second protection operation performed by the protection operation component 1303 in Figure 2 The first protection operation and the second protection operation performed by the protection operation component 1303 in the embodiment are substantially the same. The difference may be that the protection operation component 1303 responds to the third detection signal DET <3> , the fourth detection signal DET <4> , the fifth detection signal DET <5> and the sixth detection signal DET <6> And generate operation information OPI. In other words, Figure 3 The protection operation component 1303 in the embodiment may generate a third detection signal DET indicating <3> Whether it has been enabled, the fourth detection signal DET <4> Has it been enabled, the fifth detection signal DET <5> Whether it has been enabled and the sixth detection signal DET <6> Whether the operational information OPI has been enabled.

[0130] As mentioned above, Figure 3 The protection operation component 1303 in the embodiment uses the third detection signal DET when generating the operation information OPI. <3> , the fourth detection signal DET <4> , the fifth detection signal DET <5> and the sixth detection signal DET <6> Therefore, when determining the reason for entering the protection mode through the operation information OPI, Figure 3 The recovery operation component 1304 in Figure 2 The recovery operation component 1304 in the controller 1300 determines the cause in more detail. In some embodiments, by determining which voltage level among the third power supply voltage VCC1, the fourth power supply voltage VCC2, the fifth power supply voltage VCCQ1, and the sixth power supply voltage VCCQ2 fluctuates abnormally to cause the entry into the protection mode, it can be determined whether there is a high probability of an error occurring in the controller 130 or the memory device 150, whether it is likely that an unexpected signal is transmitted through a circuit for allowing the controller 130 to drive a signal among the multiple interfaces 10, or whether it is likely that an unexpected signal is transmitted through a circuit for allowing the memory device 150 to drive a signal among the multiple interfaces 10.

[0131] Figure 4 is a diagram illustrating another example of a characteristic operation of the memory system 110 according to an embodiment.

[0132] Reference Figure 4 , the memory system 110 can receive four power supply voltages VCC3, VCCQ3, VCC4, and VCCQ4, that is, the seventh power supply voltage VCC3, the eighth power supply voltage VCC4, the ninth power supply voltage VCCQ3, and the tenth power supply voltage VCCQ4 from an external source, and use them as operating voltages. That is, Figure 3 The memory system 110 and Figure 4 The main difference in configuration between the memory systems 110 in FIG. 1 is the number of power supply voltages input from the external source.

[0133] Figure 3The memory system 110 in the embodiment includes a configuration in which a third power supply voltage VCC1, a fourth power supply voltage VCC2, a fifth power supply voltage VCCQ1, and a sixth power supply voltage VCCQ2 are generated in response to a first power supply voltage VCC and a second power supply voltage VCCQ input from an external source, and the third power supply voltage VCC1, the fourth power supply voltage VCC2, the fifth power supply voltage VCCQ1, and the sixth power supply voltage VCCQ2 are used as operating voltages. On the other hand, Figure 4 The memory system 110 in EMBODIMENT 1 includes a configuration in which a seventh power supply voltage VCC3 , an eighth power supply voltage VCC4 , a ninth power supply voltage VCCQ3 , and a tenth power supply voltage VCCQ4 input from an external source are used as operation voltages.

[0134] In conclusion, Figure 3 The memory system 110 in the embodiment needs to include a voltage generator 160 in the memory system 110 so as to generate a third power supply voltage VCC1, a fourth power supply voltage VCC2, a fifth power supply voltage VCCQ1, and a sixth power supply voltage VCCQ2 in response to a first power supply voltage VCC and a second power supply voltage VCCQ input from an external source. On the other hand, because Figure 4 The memory system 110 in the embodiment directly receives the seventh power supply voltage VCC3, the eighth power supply voltage VCC4, the ninth power supply voltage VCCQ3 and the tenth power supply voltage VCCQ4 used as the operating voltage from the external source, so the memory system 110 does not need such as Figure 3 Components of the voltage generator 160 in.

[0135] also, Figure 3 The memory system 110 in the embodiment is configured to generate a third power supply voltage VCC1 and a fourth power supply voltage VCC2 in response to a first power supply voltage VCC input from an external source, and to generate a fifth power supply voltage VCCQ1 and a sixth power supply voltage VCCQ2 in response to a second power supply voltage VCCQ. Therefore, when the level of the first power supply voltage VCC changes abnormally, the levels of the third power supply voltage VCC1 and the fourth power supply voltage VCC2 may also change abnormally. Similarly, when the level of the second power supply voltage VCCQ changes abnormally, the levels of the fifth power supply voltage VCCQ1 and the sixth power supply voltage VCCQ2 may also change abnormally.

[0136] on the other hand, Figure 4 The memory system 110 in FIG. 1 directly receives the seventh power supply voltage VCC3, the eighth power supply voltage VCC4, the ninth power supply voltage VCCQ3, and the tenth power supply voltage VCCQ4 used as operating voltages from an external source. Therefore, the levels of the seventh power supply voltage VCC3, the eighth power supply voltage VCC4, the ninth power supply voltage VCCQ3, and the tenth power supply voltage VCCQ4 vary independently. Figure 4In the case of the memory system 110 in FIG. 1 , there is a low probability that the levels of two or more specific power supply voltages will abnormally change at the same time.

[0137] As described above, according to an embodiment of the present invention, when the level of the power supply voltage VCC supplied to the memory system 110 changes so that it exceeds the reference level range, a protection operation for ensuring the reliability of the memory device can be performed in combination with hardware, and then when the level of the externally supplied power supply voltage is stable, a recovery operation for ensuring the reliability of the memory device can be performed in combination with software. Therefore, even when the level of the power supply voltage supplied to the memory system 110 deviates from the reference level range, the operational stability of the memory system 110 can be ensured.

[0138] While various embodiments have been shown and described, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A memory system, comprising: Memory device; as well as a controller operably coupled to the memory device via a plurality of interfaces, The controller comprises: A first internal storage device having a volatile characteristic; a second internal storage device having a non-volatile characteristic and storing a recovery code; A level detector, detecting whether the level change of the power supply voltage exceeds the reference level range, and generating a detection signal corresponding to the detection result; a protection operation component that determines entry into and exit from a protection mode in response to the detection signal, and performs a first protection operation upon entry into the protection mode, the first protection operation generating event information about a state of the memory system, generating a logic value of each of the plurality of interfaces as snapshot information, and storing the event information and the snapshot information in the first internal storage device, and the protection operation component further performing a second protection operation that fixes each of the plurality of interfaces to a set logic value; and a recovery operation component that receives the recovery code from the second internal storage device in response to the memory system exiting the protection mode, enters a recovery mode, receives the event information and the snapshot information from the first internal storage device, and performs a recovery operation on the memory device, The protection operation component generates operation information and execution information when entering the protection mode in response to the detection signal, and stores the operation information and the execution information in the first internal storage device as the event information, the operation information is related to the operation of entering the protection mode, and the execution information indicates whether the second protection operation has been completed.

2. The memory system of claim 1 , wherein the controller further comprises: a buffer for buffering signals to be transmitted to the memory device through the plurality of interfaces, The protection operation component generates a logic value of a signal buffered by the buffer as the snapshot information when entering the protection mode, and stores the snapshot information in the first internal storage device.

3. The memory system according to claim 2, wherein the recovery operation component identifies data having an error probability higher than a reference probability among the data stored in the memory device in response to the event information and the snapshot information in the recovery mode, and performs an error correction operation on the identified data.

4. The memory system of claim 3, wherein the power supply voltage comprises: a first power supply voltage targeting a first reference level and serving as an operating voltage for the controller and the memory device; as well as The second power supply voltage targets a second reference level and is used as an operation voltage for the plurality of interfaces, the second reference level being greater than the first reference level.

5. The memory system according to claim 4, wherein the reference level range includes a first reference level range in which the first reference level is an intermediate level and a second reference level range in which the second reference level is an intermediate level, and wherein the level detector enables a first detection signal in the detection signals when the first power supply voltage exceeds a maximum level of the first reference level range or drops below a minimum level of the first reference level range, and A second detection signal among the detection signals is enabled when the second power supply voltage exceeds a maximum level of the second reference level range or drops below a minimum level of the second reference level range.

6. The memory system of claim 5, wherein the protection operation component enters the protection mode in response to enabling of at least one of the first detection signal and the second detection signal, and exits the protection mode in response to disabling of both the first detection signal and the second detection signal. 7 . The memory system of claim 6 , wherein the protection operation component generates the operation information, the operation information indicating whether the first detection signal has been enabled and whether the second detection signal has been enabled.

8. The memory system according to claim 4, further comprising: a voltage generator receiving the first power supply voltage and generating a third power supply voltage, the third power supply voltage targeting a third reference level and serving as an operating voltage of the controller; receiving the first power supply voltage and generating a fourth power supply voltage, the fourth power supply voltage targeting a fourth reference level and serving as an operating voltage for the memory device; receiving the second power supply voltage and generating a fifth power supply voltage, the fifth power supply voltage targeting a fifth reference level and serving as an operating voltage of a circuit driving the plurality of interfaces in the controller, the fifth reference level being greater than the third reference level; The second power supply voltage is received and a sixth power supply voltage is generated, the sixth power supply voltage targeting a sixth reference level and used as an operating voltage of a circuit driving the plurality of interfaces in the memory device, the sixth reference level being greater than the fourth reference level.

9. The memory system according to claim 8, wherein the reference level ranges include a third reference level range in which the third reference level is an intermediate level, a fourth reference level range in which the fourth reference level is an intermediate level, a fifth reference level range in which the fifth reference level is an intermediate level, and a sixth reference level range in which the sixth reference level is an intermediate level, and wherein the level detector enables the third detection signal in the detection signal when the third power supply voltage exceeds the maximum level of the third reference level range or drops below the minimum level of the third reference level range, When the fourth power supply voltage exceeds the maximum level of the fourth reference level range or drops below the minimum level of the fourth reference level range, enabling the fourth detection signal in the detection signal, When the fifth power supply voltage exceeds the maximum level of the fifth reference level range or drops below the minimum level of the fifth reference level range, enabling the fifth detection signal in the detection signal, and When the sixth power supply voltage exceeds a maximum level of the sixth reference level range or drops below a minimum level of the sixth reference level range, a sixth detection signal among the detection signals is enabled.

10. The memory system according to claim 9, wherein the protection operation component enters the protection mode in response to the activation of any one of the third detection signal to the sixth detection signal, and exits the protection mode in response to the deactivation of all of the third detection signal to the sixth detection signal.

11. The memory system of claim 10 , wherein the protection operation component generates the operation information, the operation information indicating whether the third detection signal has been enabled, whether the fourth detection signal has been enabled, whether the fifth detection signal has been enabled, and whether the sixth detection signal has been enabled.

12. The memory system of claim 3, wherein the power supply voltage comprises: a seventh power supply voltage targeting a seventh reference level and serving as an operating voltage for the controller; an eighth power supply voltage targeting an eighth reference level and serving as an operating voltage of the memory device; a ninth power supply voltage, targeting a ninth reference level and used as an operating voltage of a circuit in the controller driving the plurality of interfaces, the ninth reference level being greater than the seventh reference level; as well as A tenth power supply voltage targets a tenth reference level and is used as an operating voltage of a circuit driving the plurality of interfaces in the memory device, the tenth reference level being greater than the eighth reference level.

13. The memory system according to claim 12, wherein the reference level ranges include a seventh reference level range in which the seventh reference level is an intermediate level, an eighth reference level range in which the eighth reference level is an intermediate level, a ninth reference level range in which the ninth reference level is an intermediate level, and a tenth reference level range in which the tenth reference level is an intermediate level, and The level detector enables a seventh detection signal in the detection signal when the seventh power supply voltage exceeds a maximum level of the seventh reference level range or drops below a minimum level of the seventh reference level range, When the eighth power supply voltage exceeds the maximum level of the eighth reference level range or drops below the minimum level of the eighth reference level range, enabling the eighth detection signal in the detection signal; When the ninth power supply voltage exceeds the maximum level of the ninth reference level range or drops below the minimum level of the ninth reference level range, a ninth detection signal in the detection signal is enabled, and When the tenth power supply voltage exceeds a maximum level of the tenth reference level range or drops below a minimum level of the tenth reference level range, a tenth detection signal among the detection signals is enabled.

14. The memory system of claim 13, wherein the protection operation component enters the protection mode in response to enabling of any one of the seventh to tenth detection signals, and exits the protection mode in response to disabling of all of the seventh to tenth detection signals.

15. The memory system of claim 14, wherein the protection operation component generates the operation information, the operation information indicating whether the seventh detection signal has been enabled, whether the eighth detection signal has been enabled, whether the ninth detection signal has been enabled, and whether the tenth detection signal has been enabled.

16. The memory system according to claim 1, wherein the plurality of interfaces include a command interface, an address interface, and a data interface, and The protection operation component performs the second protection operation when entering the protection mode, and the second protection operation fixes the logic value of the command interface to a first logic value to stop the operation of the memory device, fixes the logic value of the data interface to a second logic value, and fixes the logic value of the address interface to a third logic value to prevent the memory device from being accessed. 17 . The memory system of claim 1 , wherein the protection operation component starts the first protection operation and the second protection operation simultaneously when entering the protection mode.

18. A memory system comprising: Memory device; a controller including a volatile storage device and a non-volatile storage device storing a recovery code; as well as a plurality of interfaces between the controller and the memory device, The controller: detecting whether a first voltage and a second voltage exceed respective reference level ranges, the first voltage operating the controller and the memory device, and the second voltage operating the plurality of interfaces; When it is detected that one of the first voltage and the second voltage exceeds a corresponding reference level range, a protection mode is entered to store event information and snapshot information in the volatile storage device, and each of the plurality of interfaces is fixed to a set logic value, the event information is associated with the protection mode, and the snapshot information is associated with the plurality of interfaces; and in response to the memory system exiting the protection mode and entering a recovery mode, receiving the recovery code from the non-volatile memory device and receiving the event information and the snapshot information from the volatile memory device, selecting at least one data item among the data items stored in the memory device using the recovery code, the event information and the snapshot information, and performing an error correction operation on the selected at least one data item, When entering the protection mode, operation information and execution information are generated and stored in the volatile storage device as the event information, the operation information is related to the operation of entering the protection mode, and the execution information indicates whether each of the multiple interfaces has been fixed to the set logical value.

Images