Chip packaging structure and packaging method

Abstract

The application provides a chip packaging structure and a packaging method, wherein the chip packaging structure comprises at least two wafer-level chips stacked; the wafer-level chip comprises a substrate and a GaN epitaxial layer grown on the upper surface of the substrate, a plurality of signal connection pads and a plurality of grounding pads are arranged on the GaN epitaxial layer, a plurality of signal lead-out pads corresponding to the signal connection pads and a plurality of grounding lead-out pads corresponding to the grounding pads are arranged on the lower surface of the substrate; the signal lead-out pads of the wafer-level chip on the upper layer are bonded with the signal connection pads of the wafer-level chip on the adjacent lower layer, and the grounding lead-out pads of the wafer-level chip on the upper layer are bonded with the grounding pads of the wafer-level chip on the adjacent lower layer. The wafer-level chips are stacked into one by the GaN process and the wafer-level bonding technology, the wafer-level packaging of the GaN monolithic microwave integrated circuit is realized, and the integration of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing processes, and in particular to a chip packaging structure and a packaging method. Background Art

[0002] With the development of high-density and high-integration semiconductor technology, device size is constantly decreasing, while the amount of chip signal transmission is also increasing, and the number of pins is gradually increasing. Wafer-level bonding technology has become the mainstream development direction in the field of chip packaging and integration.

[0003] Wafer-level chip bonding technology involves stacking and interconnecting chips in a three-dimensional structure, thereby optimizing circuit connections. This technology offers advantages in achieving multifunctional chip integration, reducing signal transmission and power consumption, and improving chip heat dissipation. Wide-bandgap semiconductor GaN, with its wide bandgap, high thermal conductivity, high breakdown field strength, and high electron saturation drift velocity, holds broad market application prospects in power device manufacturing.

[0004] However, wafer-level bonding of GaN chips is still not possible at present. How to achieve wafer-level bonding of GaN chips and thus improve the integration of chips has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The embodiments of the present invention provide a chip packaging structure and packaging method to solve the problem that GaN chips cannot achieve wafer-level bonding.

[0006] In a first aspect, an embodiment of the present invention provides a chip packaging structure, comprising at least two stacked wafer-level chips; wherein the wafer-level chip comprises: a substrate, and a GaN epitaxial layer grown on the upper surface of the substrate, a plurality of signal connection pads and a plurality of ground pads provided on the GaN epitaxial layer, and a signal lead-out pad electrically connected to the signal connection pads and a ground lead-out pad electrically connected to the ground pads provided on the lower surface of the substrate;

[0007] The signal lead-out points of the wafer-level chip on the upper layer are bonded to the signal connection points of the wafer-level chip on the adjacent lower layer, and the ground lead-out points of the wafer-level chip on the upper layer correspond to and are bonded to the ground points of the wafer-level chip on the adjacent lower layer.

[0008] In a possible implementation, a through hole corresponding to the grounding pressure point and / or the signal connection pressure point is etched on the lower surface of the substrate, and a metal plating layer is provided in the through hole;

[0009] The signal connection point is electrically connected to the signal lead-out point through the metal plating layer, and the grounding point is electrically connected to the grounding lead-out point through the metal plating layer.

[0010] In a possible implementation, the signal lead-out pads of the wafer-level chip located in the upper layer are connected to the signal connection pads of the wafer-level chip located in the adjacent lower layer by gold-gold bonding.

[0011] In a possible implementation, a through hole corresponding to the grounding pressure point is etched on the lower surface of the substrate of the wafer-level chip at the bottom layer, and a metal plating layer provided in the through hole covers the lower surface of the substrate.

[0012] In a possible implementation, the epitaxial layer of the uppermost wafer-level chip is further covered with a SiN passivation layer, and the SiN passivation layer exposes the signal connection pads and the ground pads.

[0013] In a possible implementation, the method includes a first wafer-level chip and a second wafer-level chip that are stacked;

[0014] The first wafer-level chip includes: a first substrate, a first epitaxial layer located on an upper surface of the first substrate, a plurality of first signal connection pads and a plurality of first ground pads located on the first epitaxial layer, and a first signal lead-out pad located on a lower surface of the first substrate and electrically connected to the first signal connection pads and a first ground lead-out pad connected to the first ground pads;

[0015] The second wafer-level chip includes: a second substrate, a second epitaxial layer located on an upper surface of the second substrate, a plurality of second signal connection pads and a plurality of second grounding pads located on the second epitaxial layer, and a metal plating layer located on a lower surface of the second substrate, the metal plating layer being electrically connected to the plurality of second grounding pads;

[0016] The first signal lead-out pressure point is bonded to the second signal connection pressure point, and the first ground lead-out pressure point is bonded to the second ground pressure point.

[0017] The chip packaging structure provided by an embodiment of the present invention extends the signal connection points and grounding points of the upper wafer-level chip to the back of the wafer, and then forms the signal lead-out points and grounding lead-out points of the chip on the back of the wafer. Signal connection points and grounding points are formed on the front of the adjacent lower wafer-level chip. Two adjacent wafer-level chips are bonded together via the signal lead-out points and the grounding points, thereby achieving bonding between multiple wafer-level chips.

[0018] In a second aspect, an embodiment of the present invention provides a chip packaging method, comprising the following steps:

[0019] providing a first substrate and a second substrate;

[0020] Growing a first GaN epitaxial layer on the upper surface of the first substrate, and fabricating supporting devices and corresponding multiple first signal connection voltage points and multiple first grounding voltage points on the first GaN epitaxial layer; growing a second GaN epitaxial layer on the upper surface of the second substrate, and fabricating supporting devices and corresponding multiple second signal connection voltage points and multiple second grounding voltage points on the second GaN epitaxial layer;

[0021] Using a through-hole process and an electroplating process, the first signal connection pad and the first ground pad are led out to the lower surface of the first substrate to form a first signal lead-out pad and a first ground lead-out pad; using a gold-gold bonding process, the first signal lead-out pad is bonded to the second signal connection pad, and the first ground lead-out pad is bonded to the second ground pad;

[0022] The second grounding voltage point is led out to the lower surface of the second substrate to form a metal plating layer.

[0023] In one possible implementation, the first signal connection point and the first ground connection point are led out to the lower surface of the first substrate using a through-hole process and an electroplating process to form a first signal lead-out point and a first ground lead-out point, specifically comprising the following steps:

[0024] thinning the lower surface of the first substrate to a predetermined thickness;

[0025] Etching a predetermined area of ​​the lower surface of the thinned first substrate until the etching reaches the corresponding first signal connection pressure point and the first ground pressure point to form a through hole;

[0026] sputtering a seed layer on the through hole and the lower surface of the first substrate, and forming a first metal layer on the seed layer by electroplating;

[0027] Using a photolithography process on the lower surface of the first substrate, an isolation region is formed between the first ground lead-out pad and the first signal lead-out pad;

[0028] Corroding the metal in the isolation area on the lower surface of the first substrate to remove the metal in the isolation area, thereby isolating the first ground lead-out pressure point from the first signal lead-out pressure point;

[0029] The first ground lead-out pressure point and the first signal lead-out pressure point are thickened by using photolithography and evaporation processes.

[0030] In a possible implementation, the step of leading the second grounding pressure point to the lower surface of the second substrate to form a metal plating layer specifically includes the following steps:

[0031] thinning the lower surface of the second substrate to a predetermined thickness;

[0032] Etching a predetermined area of ​​the lower surface of the thinned second substrate until the etching reaches the second grounding pressure point to form a through hole;

[0033] A seed layer is sputtered on the through hole and the lower surface of the second substrate, and a metal plating layer is formed on the seed layer by electroplating.

[0034] In a possible implementation, the preset thickness is 70 μm±5 μm;

[0035] and / or the thickness of the seed layer is 5000 angstroms ± 300 angstroms;

[0036] And / or the thickness of the first metal layer and the metal plating layer are both 5 μm±1 μm.

[0037] The chip packaging method provided by an embodiment of the present invention first arranges devices, supporting signal connection points, and ground connection points on a first GaN epitaxial layer and a second GaN epitaxial layer, respectively. Then, the two wafer-level chips are stacked into one by using GaN process and wafer-level bonding technology, thereby realizing wafer-level packaging of GaN monolithic microwave integrated circuits, improving chip integration, and reducing signal transmission and loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 1 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present invention;

[0040] Figure 2-Figure 6 It is a structural schematic diagram of a chip packaging method provided by an embodiment of the present invention.

[0041] In the figure, 10 is a first substrate, 11 is a first GaN epitaxial layer, 12 is a first grounding pressure point, 13 is a first signal connection pressure point, 14 is a passivation layer, 15 is a first metal layer, 16 is a first grounding lead pressure point, and 17 is a first signal lead pressure point.

[0042] 20 - second substrate, 21 - second GaN epitaxial layer, 22 - second grounding pad, 23 - second signal connection pad, 24 - metal plating layer. DETAILED DESCRIPTION

[0043] To help those skilled in the art better understand this solution, the following will clearly describe the technical solutions in the embodiments of this solution in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of this solution, not all of it. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of this solution.

[0044] Throughout the specification, claims, and accompanying figures of this solution, the term "including" and any variations thereof mean "including, but not limited to," and are intended to cover non-exclusive inclusions and are not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish between different objects, not to describe a specific order.

[0045] At present, in the process of preparing wafer-level chips using GaN epitaxial layers, it is still impossible to achieve stacked packaging of multiple GaN monolithic microwave integrated circuit wafer-level chips, which restricts the speed of continuous development of chips towards high integration.

[0046] In order to solve the above technical problems, the implementation of the present invention is described in detail below with reference to the accompanying drawings:

[0047] An embodiment of the present invention provides a chip packaging structure, comprising at least two wafer-level chips stacked together. The wafer-level chip comprises: a substrate, a GaN epitaxial layer, a plurality of signal connection points, a plurality of grounding points, a signal lead-out point, and a grounding lead-out point. Specifically, a GaN epitaxial layer is grown on the upper surface of the substrate, a plurality of signal connection points and a plurality of grounding points are arranged on the GaN epitaxial layer, and a signal lead-out point electrically connected to the signal connection points and a grounding lead-out point connected to the grounding point are provided on the lower surface of the substrate. Among them, the signal lead-out points of the wafer-level chip located in the upper layer are bonded to the signal connection points of the wafer-level chip located in the adjacent lower layer, and the grounding lead-out points of the wafer-level chip located in the upper layer correspond to and are bonded to the grounding points of the wafer-level chip located in the adjacent lower layer.

[0048] In some embodiments, a through hole corresponding to the grounding pressure point and / or the signal connection pressure point is etched on the lower surface of the substrate, and a metal plating is provided in the through hole; wherein the signal connection pressure point is electrically connected to the signal lead-out pressure point through the metal plating, and the grounding pressure point is electrically connected to the grounding lead-out pressure point through the metal plating.

[0049] Specifically, multiple signal connection points and multiple grounding points can be provided on the GaN epitaxial layer. The number of signal connection points and grounding points is set according to the actual use requirements of the wafer-level chip. Some or all of the signal connection points can be led out to the lower surface of the substrate to form signal lead-out points. Multiple grounding points can also be led out to the lower surface of the substrate to form ground lead-out points as needed.

[0050] In some embodiments, the signal lead-out pads of the wafer-level chip on the upper layer are connected to the signal connection pads of the wafer-level chip on the adjacent lower layer by gold-gold bonding.

[0051] Specifically, the signal lead-out pressure points of the upper wafer-level chip are connected to the signal connection pressure points of the adjacent lower wafer-level chip through a gold-gold bonding process, thereby transmitting the signal of the upper wafer-level chip to the lower wafer-level chip, thereby reducing transmission loss.

[0052] In some embodiments, to improve the anti-interference performance and electrostatic field impact of stacked wafer-level chips, a through-hole corresponding to a grounding point is etched on the lower surface of the substrate of the bottommost wafer-level chip. A metal coating is provided within the through-hole and covers the lower surface of the substrate. As a result, the lower surface of the substrate of the bottommost chip in the stack is covered with a layer of metal coating, which is electrically connected to the grounding point, ensuring the normal operation of the entire chip.

[0053] In some embodiments, according to actual usage requirements, in addition to preparing ground lead-out pressure points, some signal lead-out pressure points may also be provided on the lower surface of the substrate of the bottommost wafer-level chip.

[0054] In some embodiments, in order to protect the stacked wafer-level chips, a SiN passivation layer is also covered on the upper surface epitaxial layer of the topmost wafer-level chip. The SiN passivation layer exposes the signal connection voltage points and the ground voltage points, thereby protecting the outer surface of the device and ensuring that the device can work normally.

[0055] Specifically, such as Figure 1 As shown, the present invention provides a packaging structure of two wafer-level chips, including a first wafer-level chip and a second wafer-level chip stacked together. Specifically, the first wafer-level chip includes a first substrate 10, a first GaN epitaxial layer 11 located on the upper surface of the first substrate 10, a plurality of first signal connection points 13 and a plurality of first grounding points 12 located on the first GaN epitaxial layer 11, and a first signal lead-out point 17 located on the lower surface of the first substrate 10 and electrically connected to the first signal connection point 13 and a first grounding lead-out point 16 connected to the first grounding point 12. In order to protect the upper surface of the first wafer-level chip, a passivation layer 14 is also provided.

[0056] The second wafer-level chip includes a second substrate 20, a second GaN epitaxial layer 21 located on the upper surface of the second substrate 20, a plurality of second signal connection points 23 and a plurality of second grounding points 22 located on the second GaN epitaxial layer 21, and a metal plating layer 24 located on the lower surface of the second substrate 20, wherein the metal plating layer 24 is electrically connected to the plurality of second grounding points 23.

[0057] Furthermore, the first signal lead pad 17 is bonded to the second signal connection pad 23. The first ground lead pad 16 is bonded to the second ground pad 22. This achieves the integrated packaging of two wafer-level chips, improves the chip integration, and reduces signal transmission loss.

[0058] Through-hole technology is used to extend multiple first signal connection pads 13 and multiple first ground pads 12 on the upper surface of the upper wafer-level chip to the backside of the wafer-level chip. Metal lead pads (first signal lead pads 17 and first ground lead pads 16) are then added to the backside of the wafer-level chip. Thickened signal metal pads (second signal connection pads 23 and second ground pads 22) are added to the frontside of the lower wafer-level chip. The two wafer-level chips are stacked together through GaN wafer-level bonding, achieving wafer-level packaging of GaN monolithic microwave integrated circuits. This is a new chip-level packaging system that achieves high-density chip integration, improves the degree of chip integration, and reduces signal transmission loss.

[0059] The chip packaging structure provided by the present invention leads the signal connection points and grounding points of the upper wafer-level chip to the back of the wafer, and then forms the signal lead-out points and grounding lead-out points of the chip on the back of the wafer. The signal lead-out points and grounding lead-out points are formed on the front of the adjacent lower wafer-level chip. Two adjacent wafer-level chips are bonded together through the signal lead-out points and the ground lead-out points, thereby achieving bonding between multiple wafer-level chips.

[0060] On the other hand, the embodiment of the present invention also provides a chip packaging method, please refer to Figures 2 to 6 , providing a first substrate 10 and a second substrate 20.

[0061] like Figure 2 As shown, a first GaN epitaxial layer 11 is grown on the upper surface of the first substrate 10, and supporting devices and corresponding multiple first signal connection pads 13 and multiple first grounding pads 12 are fabricated on the first GaN epitaxial layer 11. To protect the devices on the upper surface, a passivation layer 14 may also be formed on the upper surface. The passivation layer exposes the multiple first signal connection pads 13 and multiple first grounding pads 12 on the device surface.

[0062] like Figure 4As shown, a second GaN epitaxial layer 21 is grown on the upper surface of the second substrate 20, and a corresponding device is fabricated on the second GaN epitaxial layer 21, and a plurality of second signal connection pads 23 and a plurality of second ground pads 22 are formed.

[0063] Then, as shown, the first signal connection pads 13 and the first ground pads 12 are led out to the lower surface of the first substrate 10 by using a via process and an electroplating process to form first signal leading-out pads 17 and first ground leading-out pads 16. The first signal leading-out pads 13 are bonded to the second signal connection pads 23, and the first ground leading-out pads 12 are bonded to the second ground pads 22 by using a gold-to-gold bonding process. Figure 5

[0064] Finally, the second ground pads 22 are led out to the lower surface of the second substrate 20 to form a metal plating layer 24.

[0065] In some embodiments, as shown, the first signal connection pads 13 and the first ground pads 12 are led out to the lower surface of the first substrate 10 to form the first signal leading-out pads 17 and the first ground leading-out pads 16, which specifically include the following steps: Figure 3

[0066] First, the lower surface of the first substrate 10 is thinned to a preset thickness. The preset thickness can be 70 μm ± 5 μm. Then, a preset region of the thinned lower surface of the first substrate 10 is etched until the first signal connection pads 13 and the first ground pads 12 are reached to form vias. The preset region refers to a region of the lower surface of the first substrate 10 corresponding to the first signal connection pads 13 and the first ground pads 12.

[0067] Then, a seed layer is sputtered on the vias and the lower surface of the first substrate 10 by using a deep-hole sputtering process, and a first metal layer 15 is formed on the seed layer by using a deep-hole electroplating process. The isolation region between the first signal leading-out pads 17 and the first ground leading-out pads 16 is defined by using a photolithography process on the back surface of the first substrate 10, and then etching is performed to remove the first metal layer 15 of the isolation region to achieve isolation between the first signal leading-out pads 17 and the first ground leading-out pads 16. The thickness of the seed layer can be 5000 A ± 300 A, and the thickness of the first metal layer can be 5 μm ± 1 μm.

[0068] Finally, the first signal leading-out pads 17 and the first ground leading-out pads 16 are thickened by using a photolithography process and an evaporation process to complete the fabrication of the first signal leading-out pads 17 and the first ground leading-out pads 16 on the lower surface of the first wafer-level chip.

[0069] In some embodiments, the second ground pads 22 are led out to the lower surface of the second substrate to form a metal plating layer 24, as shown in​​ Figure 6 As shown, the specific steps include:

[0070] Specifically, first, the lower surface of the second substrate 20 is thinned to a preset thickness, wherein the preset thickness may be 70 μm±5 μm.

[0071] Then, a predetermined area on the lower surface of the thinned second substrate 20 is etched until the etching reaches the grounding pressure point to form a through hole. The predetermined area is the area on the lower surface of the second substrate 20 corresponding to the second grounding pressure point 22 .

[0072] Finally, a seed layer is sputtered on the through hole and the lower surface of the second substrate 20, and a metal plating layer 24 is electroplated on the seed layer. The thickness of the seed layer can be 5000 angstroms ± 300 angstroms, and the thickness of the metal plating layer can be 5 μm ± 1 μm.

[0073] The chip packaging method provided by the present invention first arranges the components, along with supporting signal and ground connection pads, on a first GaN epitaxial layer and a second GaN epitaxial layer. Then, utilizing GaN processing and wafer-level bonding technology, the two wafer-level chips are stacked together, thereby achieving wafer-level packaging of GaN monolithic microwave integrated circuits, improving chip integration and reducing signal transmission and loss.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A chip packaging method, characterized in that: The following steps are involved: providing a first substrate and a second substrate; Growing a first GaN epitaxial layer on the upper surface of the first substrate, and fabricating supporting devices and corresponding multiple first signal connection voltage points and multiple first grounding voltage points on the first GaN epitaxial layer; growing a second GaN epitaxial layer on the upper surface of the second substrate, and fabricating supporting devices and corresponding multiple second signal connection voltage points and multiple second grounding voltage points on the second GaN epitaxial layer; Leading the first signal connection pressure point and the first ground pressure point to the lower surface of the first substrate to form a first signal lead-out pressure point and a first ground lead-out pressure point specifically includes the following steps: thinning the lower surface of the first substrate to a predetermined thickness; Etching a predetermined area of ​​the lower surface of the thinned first substrate until the etching reaches the corresponding first signal connection pressure point and the first ground pressure point to form a through hole; sputtering a seed layer on the through hole and the lower surface of the first substrate, and forming a first metal layer on the seed layer by electroplating; Using a photolithography process on the lower surface of the first substrate, an isolation region is formed between the first ground lead-out pad and the first signal lead-out pad; Corroding the metal in the isolation area on the lower surface of the first substrate to remove the metal in the isolation area, thereby isolating the first ground lead-out pressure point from the first signal lead-out pressure point; Using photolithography and evaporation processes, thickening the first ground lead-out pressure point and the first signal lead-out pressure point; Bonding the first signal lead-out pad to the second signal connection pad, and bonding the first ground lead-out pad to the second ground pad using a gold-gold bonding process; Leading the second grounding pressure point to the lower surface of the second substrate to form a metal plating layer specifically includes the following steps: thinning the lower surface of the second substrate to a predetermined thickness; Etching a predetermined area of ​​the lower surface of the thinned second substrate until the etching reaches the second grounding pressure point to form a through hole; A seed layer is sputtered on the through hole and the lower surface of the second substrate, and a metal plating layer is formed on the seed layer by electroplating.

2. The chip packaging method according to claim 1, wherein: The preset thickness is 70 μm ± 5 μm; and / or the thickness of the seed layer is 5000 angstroms ± 300 angstroms; And / or the thickness of the first metal layer and the metal plating layer are both 5 μm±1 μm.

3. A chip packaging structure, characterized in that: The chip packaging structure is prepared based on the chip packaging method according to claim 1 or 2, and the chip packaging structure includes at least two stacked wafer-level chips; wherein the wafer-level chip includes: a substrate, and a GaN epitaxial layer grown on the upper surface of the substrate, a plurality of signal connection pressure points and a plurality of ground pressure points are provided on the GaN epitaxial layer, and a signal lead-out pressure point electrically connected to the signal connection pressure point and a ground lead-out pressure point electrically connected to the ground pressure point are provided on the lower surface of the substrate; The signal lead-out points of the wafer-level chip on the upper layer are bonded to the signal connection points of the wafer-level chip on the adjacent lower layer, and the ground lead-out points of the wafer-level chip on the upper layer correspond to and are bonded to the ground points of the wafer-level chip on the adjacent lower layer.

4. The chip packaging structure according to claim 3, wherein: A through hole corresponding to the grounding pressure point and / or the signal connection pressure point is etched on the lower surface of the substrate, and a metal plating layer is provided in the through hole; The signal connection point is electrically connected to the signal lead-out point through the metal plating layer, and the grounding point is electrically connected to the grounding lead-out point through the metal plating layer.

5. The chip packaging structure according to claim 3 or 4, characterized in that: The signal lead-out pressure points of the wafer-level chip located on the upper layer are connected to the signal connection pressure points of the wafer-level chip located on the adjacent lower layer through gold-gold bonding.

6. The chip packaging structure according to claim 4, wherein: A through hole corresponding to the grounding pressure point is etched on the lower surface of the substrate of the wafer-level chip located at the bottom layer, and a metal plating layer arranged in the through hole covers the lower surface of the substrate.

7. The chip packaging structure according to claim 3, wherein: The GaN epitaxial layer of the wafer-level chip located on the top layer is further covered with a SiN passivation layer, and the SiN passivation layer exposes the signal connection voltage point and the ground voltage point.

8. The chip packaging structure according to claim 3, wherein: comprising a first wafer-level chip and a second wafer-level chip arranged in a stack; The first wafer-level chip includes: a first substrate, a first GaN epitaxial layer located on an upper surface of the first substrate, a plurality of first signal connection pads and a plurality of first ground pads located on the first GaN epitaxial layer, and a first signal lead-out pad located on a lower surface of the first substrate and electrically connected to the first signal connection pads and a first ground lead-out pad connected to the first ground pads. The second wafer-level chip includes: a second substrate, a second GaN epitaxial layer located on an upper surface of the second substrate, a plurality of second signal connection pads and a plurality of second grounding pads located on the second GaN epitaxial layer, and a metal plating layer located on a lower surface of the second substrate, the metal plating layer being electrically connected to the plurality of second grounding pads; The first signal lead-out pressure point is bonded to the second signal connection pressure point, and the first ground lead-out pressure point is bonded to the second ground pressure point.

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