Three-dimensional packaging structure of an on-chip integrated filter and its packaging method

Abstract

The present invention discloses a three-dimensional packaging structure of an on-chip integrated filter, which includes an upper packaging board and a lower packaging board stacked, and an on-chip integrated filter disposed on the upper surface of the lower packaging board. When integrating the system, the present invention integrates the filter at the same time, and the integrated filter process is compatible with the interposer process, and can be processed and formed at one time, simplifying the integration process, realizing three-dimensional integrated packaging, and solving the problems of poor packaging integration consistency and difficulty in miniaturization of traditional radio frequency systems.

Description

Technical Field

[0001] The present invention relates to, and specifically relates to a three-dimensional packaging structure and a packaging method for an on-chip integrated filter. Background Art

[0002] The filter structure is an indispensable part of an electronic system. Under the background of miniaturization and small size of electronic systems, the application and development of microsystem technology have put forward new requirements for the system integration method. For the key structure filter among them, not only good performance and small size are required, but also it must be compatible with microsystem integration packaging technology in terms of size, material, packaging, etc., and it is easy to be integrated with the microsystem. In traditional integrated packaging methods in radio frequency electronic systems, they are mainly based on LTCC (low temperature co-fired ceramic) or other laminated plates. For the integration of filters, surface mount technology is mostly used for assembly, and it is difficult to meet the requirements of miniaturization in terms of accuracy, size, and integration. Summary of the Invention

[0003] Aiming at the above deficiencies in the prior art, the present invention provides a three-dimensional packaging structure and a packaging method for an on-chip integrated filter.

[0004] In order to achieve the above invention purpose, the technical solution adopted by the present invention is as follows:

[0005] In the first aspect, the present invention proposes a three-dimensional packaging structure for an on-chip integrated filter, including an upper packaging board and a lower packaging board stacked, and an on-chip integrated filter disposed on the upper surface of the lower packaging board;

[0006] The lower packaging board includes a first silicon substrate, a first metal wiring layer disposed on the upper surface of the first silicon substrate, and a second metal wiring layer disposed on the lower surface of the first silicon substrate. The first metal wiring layer includes an on-chip integrated filter graphic structure;

[0007] The upper packaging board includes a second silicon substrate, a third metal wiring layer disposed on the upper surface of the second silicon substrate, and a fourth metal wiring layer disposed on the lower surface of the second silicon substrate. The fourth metal wiring layer includes an on-chip integrated filter graphic structure and is bonded to the first metal wiring layer to form a double-layer on-chip integrated filter.

[0008] Further, the lower packaging board further includes a first integrated chip integrated on the first silicon substrate or the first metal wiring layer by an on-chip integration or heterogeneous integration method;

[0009] The lower packaging board is partially bonded to the fourth metal wiring layer of the upper packaging board through the on-chip integrated filter graphic structure of the first metal wiring layer to form a double-layer on-chip integrated filter.

[0010] Further, the lower encapsulation board further includes a first integrated chip integrated on the first silicon substrate or the first metal wiring layer by means of on-chip integration or heterogeneous integration;

[0011] The upper encapsulation board further includes a second integrated chip integrated on the second silicon substrate or the fourth metal wiring layer by means of on-chip integration or heterogeneous integration;

[0012] The lower encapsulation board and the fourth metal wiring layer of the upper encapsulation board are integrally bonded and connected through the first metal wiring layer to form a double-layer on-chip integrated filter.

[0013] Further, the on-chip integrated filter graphic structure includes a resonant unit composed of a plurality of symmetrically arranged resonant microstrip lines, and an input microstrip line and an output microstrip line respectively connected to the resonant unit. One end of each of the plurality of resonant microstrip lines is grounded through a TSV via.

[0014] Further, the lower encapsulation board further includes a micro-bump structure for connecting other substrates provided on the second metal wiring layer.

[0015] Further, the lower encapsulation board further includes TSV vias provided on the first silicon substrate and metallized vias on the inner walls of the TSV vias.

[0016] Further, the upper encapsulation board further includes a micro-bump structure for connecting other substrates provided on the third metal wiring layer.

[0017] Further, the upper encapsulation board further includes TSV vias provided on the second silicon substrate and metallized vias on the inner walls of the TSV vias.

[0018] In a second aspect, the present invention also proposes a packaging method for a three-dimensional packaging structure of an on-chip integrated filter, including the following steps:

[0019] S1. Select a silicon substrate;

[0020] S2. Etch large TSV holes on the back surface of the silicon substrate;

[0021] S3. Etch small TSV holes on the front surface of the silicon substrate to form TSV vias;

[0022] S4. Perform RCA standard cleaning on the silicon substrate, and then use a high-temperature thermal oxidation process to form an insulating layer on the surface of the silicon substrate;

[0023] S5. Sputter an adhesion layer and a seed layer on the upper and lower surfaces of the silicon substrate layer, then lithographically pattern the structure on the upper surface, and electroplate metal on the upper and lower surfaces of the silicon substrate layer and in the TSV vias. After removing the glue, perform wet etching to remove the adhesion layer and the seed layer to form a metal wiring layer and metallized vias including the on-chip integrated filter graphic structure;

[0024] S6. Pattern electroplating is performed on the metal wiring layer on the lower surface of the silicon substrate layer to form a micro bump structure;

[0025] S7. An integrated chip is bonded or soldered on the silicon substrate or the metal wiring layer on its upper surface to fabricate a lower encapsulation board;

[0026] S8. Steps S1 to S7 are repeated to fabricate an upper encapsulation board, and local etching is performed according to preset requirements;

[0027] S9. The lower encapsulation board and the upper encapsulation board are bonded together using a bonding process to obtain a three-dimensional packaging structure of the on-chip integrated filter.

[0028] The present invention has the following beneficial effects:

[0029] 1. Simple processing integration and easy 3D integration: The process of integrating the filter on the silicon substrate is the same as the substrate process, without the need to add additional process steps. The silicon substrate is a mainstream 3D integration material, which can not only integrate silicon-based chips on the chip, but also has good compatibility with gallium arsenide chips, making it very suitable for system packaging integration including filter structures.

[0030] 2. High precision and good consistency: This integration method realizes the integrated fabrication of the packaging substrate and the filter using MEMS technology and advanced semiconductor technology. The minimum line width dimension can reach the order of less than 10 mm, the line width accuracy is within 2 mm, and the control accuracy of component parameters is high, with good consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of a single-layer stacked structure of the three-dimensional packaging structure of the on-chip integrated filter of the present invention;

[0032] Figure 2 Schematic diagram of a double-layer stacked structure of the three-dimensional packaging structure of the on-chip integrated filter of the present invention;

[0033] Figure 3 Schematic diagram of the on-chip integrated filter structure of the present invention;

[0034] Figure 4 Schematic diagram of the on-chip integrated filter model of the present invention;

[0035] Figure 5 Schematic diagram of the design result of the on-chip integrated filter of the present invention;

[0036] Figure 6 Schematic diagram of the layout design of the silicon substrate of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0037] The specific embodiments of the present invention will be described below to facilitate those skilled in the art of the present technology to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art of the present technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are within the scope of protection.

[0038] With the improvement of integration, there is a further requirement for reducing the volume of filters in the system while meeting the performance requirements. Multilayer filters have emerged accordingly. The present invention provides a three-dimensional packaging structure for integrating filters on a silicon or glass substrate, which is naturally compatible with chips in terms of size, material, process, etc., and can make full use of diverse materials, larger structures, and the free space of available process choices. Naturally, it becomes the preferred technology for three-dimensional integrated microsystem packaging based on interposer. Compared with traditional integration methods, it has outstanding advantages in terms of size, line width accuracy, compatibility, performance, quality, etc. The integrated packaging method integrates the filter during system integration, and the integrated filter process is compatible with the interposer process, and can be processed in one step, simplifying the integration process, realizing three-dimensional integrated packaging, and solving the problems of poor consistency in traditional RF system packaging integration and difficulty in miniaturization.

[0039] As Figure 1 and Figure 2 shown, an embodiment of the present invention provides a three-dimensional packaging structure for an on-chip integrated filter, including an upper packaging board and a lower packaging board stacked, and an on-chip integrated filter disposed on the upper surface of the lower packaging board;

[0040] The lower packaging board includes a first silicon substrate, a first metal wiring layer disposed on the upper surface of the first silicon substrate, and a second metal wiring layer disposed on the lower surface. The first metal wiring layer includes an on-chip integrated filter graphic structure;

[0041] The upper packaging board includes a second silicon substrate, a third metal wiring layer disposed on the upper surface of the second silicon substrate, and a fourth metal wiring layer disposed on the lower surface. The fourth metal wiring layer includes an on-chip integrated filter graphic structure and is bonded to the first metal wiring layer to form a double-layer on-chip integrated filter.

[0042] In an optional embodiment of the present invention, the present invention uses MEMS process and semiconductor process to etch an on-chip integrated filter graphic structure and necessary connection structures on the first metal wiring layer on the upper surface of the lower packaging board, and uses MEMS process and semiconductor process to etch the same on-chip integrated filter graphic structure and necessary connection structures on the fourth metal wiring layer on the lower surface of the upper packaging board.

[0043] In the present invention, the upper encapsulation board and the lower encapsulation board can adopt two stacking structures: single-layer stacking and double-layer stacking.

[0044] As Figure 1 shown, when adopting the single-layer stacking structure, the lower encapsulation board integrates the first integrated chip on the first silicon substrate or the first metal wiring layer by means of on-chip integration or heterogeneous integration, while the upper encapsulation board does not provide an integration space for the integrated chip, and directly bonds and connects the lower encapsulation board to a part of the fourth metal wiring layer of the upper encapsulation board through the on-chip integrated filter graphic structure of the first metal wiring layer to form an on-chip integrated stripline filter with a double-layer structure.

[0045] As Figure 2 shown, when adopting the double-layer stacking structure, the lower encapsulation board integrates the first integrated chip on the first silicon substrate or the first metal wiring layer by means of on-chip integration or heterogeneous integration. At the same time, the upper encapsulation board integrates the second integrated chip on the second silicon substrate or the fourth metal wiring layer by means of on-chip integration or heterogeneous integration, and integrally bonds and connects the lower encapsulation board to the fourth metal wiring layer of the upper encapsulation board, so that the on-chip integrated filter graphic structure of the first metal wiring layer of the lower encapsulation board and the corresponding area of the fourth metal wiring layer of the upper encapsulation board form an on-chip integrated stripline filter with a double-layer structure, and the formed three-dimensional packaging structure can have two chips, namely the first integrated chip and the second integrated chip.

[0046] In the present invention, an on-chip integrated filter graphic structure is etched and formed on the first metal wiring layer of the lower encapsulation board respectively, and the same on-chip integrated filter graphic structure is etched and formed on the fourth metal wiring layer of the upper encapsulation board, and the same on-chip integrated filter graphic structures on the lower encapsulation board and the upper encapsulation board are bonded and connected to form an on-chip integrated stripline filter with a double-layer structure. Compared with the conventional technology of mounting a microstrip line filter on a single-layer substrate, the present invention can realize the efficient transmission of TEM waves, and can ensure less signal leakage during the transmission process, improve the transmission efficiency and transmission quality of the signal; at the same time, corresponding ground planes are etched on the first metal wiring layer of the lower encapsulation board and the fourth metal wiring layer of the upper encapsulation board in the present invention, so that the on-chip integrated stripline filter with a double-layer structure in the present invention can have better out-of-band rejection performance.

[0047] In the present invention, a three-dimensional packaging structure is formed by bonding the upper and lower encapsulation boards. On the one hand, it can ensure the construction of the on-chip integrated stripline filter with a double-layer structure, and at the same time, it will not increase redundant processes, and has the advantages of good compatibility and high flexibility; on the other hand, while improving the overall performance of the three-dimensional packaging structure, the present invention can also realize three-dimensional integrated packaging with multi-layer stacking, thereby solving the problems of poor packaging integration consistency and difficulty in miniaturization of traditional radio frequency systems.

[0048] The above-mentioned first silicon substrate and / or second silicon substrate adopt common silicon substrates. If applied to high-frequency systems, high-resistance silicon substrates are used.

[0049] The above-mentioned integrated chips can be integrated on-chip according to system requirements or integrated through heterogeneous integration. For example, due to the compatibility of material processes, the silicon substrate of a COMS chip can be directly replaced with a processed COMS wafer. For gallium arsenide chips and gallium nitride chips, heterogeneous integration can be adopted.

[0050] In an alternative embodiment of the present invention, as Figure 3 and Figure 4 shown, the on-chip integrated filter is specifically an on-chip integrated stripline filter, and its corresponding on-chip integrated filter graphic structure is realized by a single-layer metal wiring layer RDL. The grounding part can also be realized by TSV, and specifically includes a resonant unit composed of multiple symmetrically arranged resonant microstrip lines, and an input microstrip line and an output microstrip line respectively connected to the resonant unit. One ends of the multiple resonant microstrip lines are all grounded through TSV vias.

[0051] The on-chip integrated filter in the present invention is compatible with the three-dimensional integration process of the interposer and can be realized by vertically stacking silicon substrates. Structurally, it can be made into two to multiple layers, further reducing the area of the filter and thus reducing the area of the entire package structure. Figure 2 It is a stripline structure composed of two silicon substrates, and its wiring process is the same as that of the substrate surface wiring layer. The upper substrate is realized by metal layer bonding and is compatible with the three-dimensional stacking process of the substrate. At the same time, the system's three-dimensional integration can be realized by stacking the single-layer substrate upward or downward.

[0052] The key point of the three-dimensional package structure of the present invention is the on-chip integrated stripline filter. Since the process of the filter is completely compatible with the process of the package interposer, one-time forming processing integration can be achieved, simplifying the process steps and ensuring the consistency of the system.

[0053] In an alternative embodiment of the present invention, the present invention respectively sets micro-bump structures for connecting other substrates on the second metal wiring layer of the lower package board and / or the third metal wiring layer of the upper package board. The micro-bump structures are signal-connected to the upper and lower silicon substrates by welding, and the bottom can also be directly interconnected with the external substrate by welding.

[0054] In an alternative embodiment of the present invention, the present invention respectively sets TSV vias and metallized vias on the inner wall of the TSV vias on the first silicon substrate of the lower package board and / or the second silicon substrate of the upper package board. The function of the metallized via is to connect the upper-layer signal and the lower-layer signal on the silicon substrate itself.

[0055] Based on the above three-dimensional packaging structure, the present invention also proposes a packaging method for the three-dimensional packaging structure of an on-chip integrated filter, including the following steps:

[0056] S1. Select a silicon substrate;

[0057] Specifically, the substrate can be a silicon substrate, a high-resistance silicon substrate, or a COMS substrate;

[0058] S2. Etch large TSV holes on the back surface of the silicon substrate;

[0059] S3. Etch small TSV holes on the front surface of the silicon substrate to form TSV vias;

[0060] S4. Perform RCA standard cleaning on the silicon substrate, and then use a high-temperature thermal oxidation process to form an insulating layer on the surface of the silicon substrate;

[0061] Specifically, first perform RCA standard cleaning on the silicon substrate to remove residual impurities and avoid contaminating the high-resistance silicon substrate during the high-temperature process; then use a high-temperature thermal oxidation process to form a dense SiO2 insulating layer with a thickness of 100 nm on the surface of the high-resistance silicon wafer;

[0062] S5. Sputter an adhesion layer and a seed layer on the upper and lower surfaces of the silicon substrate layer, then lithographically pattern the structure on the upper surface, and electroplate metal on the upper and lower surfaces of the silicon substrate layer and in the TSV vias. After removing the photoresist, perform wet etching to remove the adhesion layer and the seed layer, forming a metal wiring layer and metallized vias including the on-chip integrated filter patterned structure;

[0063] Specifically, first sputter an adhesion layer and a seed layer with thicknesses of 200 nm of Ti and 2 μm of Cu respectively on the upper and lower surfaces of the silicon substrate layer; then lithographically pattern the structure on the upper surface of the silicon substrate layer, and electroplate Cu with a thickness of 5 - 6 μm on the upper and lower surfaces of the silicon substrate layer and in the TSV vias. After removing the photoresist, perform wet etching to remove the adhesion layer and the seed layer, forming a metal wiring layer including the on-chip integrated filter patterned structure and metallized vias on the inner wall of the TSV vias; finally, perform electroless nickel plating and gold plating on the Cu surface with a thickness of 50 nm;

[0064] S6. Perform patterned electroplating on the metal wiring layer on the lower surface of the silicon substrate layer to form a micro-bump structure;

[0065] Specifically, under the protection of a photoresist mask, pattern electroplate tin on the copper micro-bonding pads to form micro-bumps;

[0066] S7. Bond or weld an integrated chip on the silicon substrate or the metal wiring layer on its upper surface to fabricate a lower-layer packaging board;

[0067] Specifically, if a COMS substrate is selected, since the COMS substrate contains a chip, this step can be omitted.

[0068] S8. Repeat steps S1 to S7 to fabricate the upper encapsulation board and perform local etching according to preset requirements;

[0069] S9. Adopt a bonding process to bond the lower encapsulation board and the upper encapsulation board to obtain a three-dimensional encapsulation structure of the on-chip integrated filter.

[0070] Next, perform simulation design on the filter. Since the system frequency is relatively high, a high-resistance silicon substrate is selected here. Taking the design of a 6 - 7 GHz interdigital filter as an example, the material parameters are determined by the encapsulation structure, and the parameters are as follows:

[0071]

[0072] Complete the filter modeling according to the material parameters as Figure 5 shown, and simulate important parameters: the spacing and size of the resonators until the index requirements are met. The resonant unit pattern of the filter is composed of RDL on the substrate, and the grounded part in the resonant unit is realized by TSV.

[0073] The filter design result is as Figure 6 shown.

[0074] Draw the completed filter structure into a layout, which is on the same layout as the wiring layer on the silicon substrate, and complete the design of the integrated filter on the encapsulation adapter board, as shown in the figure.

[0075] Complete the filter, chip arrangement, and complete the layout design of the silicon substrate.

[0076] Specific embodiments are applied in the present invention to elaborate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0077] Those of ordinary skill in the art will realize that the embodiments described here are for helping readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention according to the technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A three-dimensional packaging structure of an on-chip integrated filter, characterized in that It includes an upper encapsulation board and a lower encapsulation board arranged in a stacked manner, and an on-chip integrated filter disposed on the upper surface of the lower encapsulation board; The lower encapsulation board includes a first silicon substrate, a first metal wiring layer disposed on the upper surface of the first silicon substrate, and a second metal wiring layer disposed on the lower surface. The first metal wiring layer includes an on-chip integrated filter graphic structure; The upper encapsulation board includes a second silicon substrate, a third metal wiring layer disposed on the upper surface of the second silicon substrate, and a fourth metal wiring layer disposed on the lower surface. The fourth metal wiring layer includes an on-chip integrated filter graphic structure and is directly bonded to the on-chip integrated filter graphic structure of the first metal wiring layer to form a double-layer on-chip integrated filter; The on-chip integrated filter graphic structure includes a resonant unit composed of a plurality of symmetrically arranged resonant microstrip lines, and an input microstrip line and an output microstrip line respectively connected to the resonant unit. One ends of the plurality of resonant microstrip lines are all grounded through TSV vias.

2. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, wherein, The lower encapsulation board further includes a first integrated chip integrated on the first silicon substrate or the first metal wiring layer in an on-chip integration or heterogeneous integration manner; The lower encapsulation board is partially bonded to the fourth metal wiring layer of the upper encapsulation board through the on-chip integrated filter graphic structure of the first metal wiring layer to form a double-layer on-chip integrated filter.

3. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, wherein The lower encapsulation board further includes a first integrated chip integrated on the first silicon substrate or the first metal wiring layer in an on-chip integration or heterogeneous integration manner; The upper encapsulation board further includes a second integrated chip integrated on the second silicon substrate or the fourth metal wiring layer in an on-chip integration or heterogeneous integration manner; The lower encapsulation board is integrally bonded to the fourth metal wiring layer of the upper encapsulation board through the first metal wiring layer to form a double-layer on-chip integrated filter.

4. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, wherein The lower encapsulation board further includes a micro-bump structure disposed on the second metal wiring layer for connecting other substrates.

5. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, characterized in that, The lower encapsulation board further includes TSV vias disposed on the first silicon substrate and metallized vias on the inner walls of the TSV vias.

6. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, characterized in that The upper encapsulation board further includes a micro-bump structure disposed on the third metal wiring layer for connecting other substrates.

7. The three-dimensional packaging structure of the on-chip integrated filter according to claim 1, characterized in that The upper encapsulation board further includes TSV vias disposed on the second silicon substrate and metallized vias on the inner walls of the TSV vias.

8. A packaging method for a three-dimensional packaging structure of an on-chip integrated filter, characterized in that, It includes the following steps: S1. Select a silicon substrate; S2. Etch large TSV holes on the back surface of the silicon substrate; S3. Etch small TSV holes on the front surface of the silicon substrate to form TSV vias; S4. Perform RCA standard cleaning on the silicon substrate, and then form an insulating layer on the surface of the silicon substrate by using a high-temperature thermal oxidation process; S5. Sputter an adhesion layer and a seed layer on the upper and lower surfaces of the silicon substrate layer, then lithographically pattern the structure on the upper surface, and electroplate metal on the upper and lower surfaces of the silicon substrate layer and in the TSV vias. After removing the photoresist, perform wet etching to remove the adhesion layer and the seed layer to form a metal wiring layer and metallized vias including an on-chip integrated filter graphic structure; S6. Perform patterned electroplating on the metal wiring layer on the lower surface of the silicon substrate layer to form a micro-bump structure; S7. Bond or weld an integrated chip on a silicon substrate or a metal wiring layer on its upper surface to fabricate a lower encapsulation board and an upper encapsulation board, and perform local etching according to preset requirements; S8. Adopt a bonding process to directly bond and connect the on-chip integrated filter graphic structure of the lower encapsulation board and the on-chip integrated filter graphic structure of the upper encapsulation board to obtain a three-dimensional encapsulation structure of the on-chip integrated filter.

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