Image sensor and method for forming the same

Abstract

The present invention relates to an image sensor having a photodiode surrounded by a backside deep trench isolation (BDTI) structure, and a related forming method. In some embodiments, a plurality of pixel regions are provided within an image sensing die and each includes a photodiode configured to convert radiation into an electrical signal. The photodiode includes a photodiode doping pillar having a first doping type, and the photodiode doping pillar is surrounded by a photodiode doping layer having a second doping type different from the first doping type. The BDTI structure is provided between adjacent pixel regions and extends from a backside of the image sensor die to a position within the photodiode doping layer. The BDTI structure includes a doping liner having the second doping type and a dielectric fill layer. The doping liner lines sidewall surfaces of the dielectric fill layer.

Description

Technical Field

[0001] Embodiments of the present application relate to an image sensor and a method of forming the same. Background Art

[0002] Many modern electronic devices include optical imaging devices (e.g., digital cameras) that use image sensors. An image sensor may include a pixel sensor array and support logic. The pixel sensors measure incident radiation (e.g., light) and convert it into digital data, and the support logic aids in reading the measurements. One type of image sensor is a backside-illuminated (BSI) image sensor device. A BSI image sensor device is used to sense the amount of light projected onto the back side of a substrate (opposite the front side of the substrate on which an interconnect structure including multiple metal and dielectric layers is built). Compared to a frontside-illuminated (FSI) image sensor device, the BSI image sensor device provides reduced destructive interference. Summary of the Invention

[0003] Some embodiments of the present application provide an image sensor, including: an image sensing die having a front side and a back side opposite the front side; a plurality of pixel regions disposed within the image sensing die and each including a photodiode configured to convert radiation entering from the back side of the image sensor die into an electrical signal, the photodiode including a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type; and a backside deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending from the back side of the image sensor die to a position within the photodiode doping layer; wherein the backside deep trench isolation structure includes a doping pad having the second doping type and a dielectric fill layer, the doping pad lining sidewall surfaces of the dielectric fill layer.

[0004] Some other embodiments of the present application provide a method of forming an image sensor, including: forming photodiodes for a plurality of pixel regions from a front side of an image sensing die, the photodiodes including photodiode doping columns having a first doping type, the photodiode doping columns being surrounded by a photodiode doping layer having a second doping type different from the first doping type; forming doped isolation wells from the front side of the image sensing die by injecting dopants into the photodiode doping layer through a plurality of implantation processes; forming a gate structure and a metallization stack on the front side of the image sensing die, wherein the metallization stack includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers; bonding the image sensing die to a logic die from the front side of the image sensing die, wherein the logic die includes logic devices; forming deep trenches between adjacent pixel regions by etching from a back side of the image sensing; forming a doped liner, wherein the second doping type lines sidewall surfaces of the deep trenches; and forming a dielectric fill layer filling an interior space of the deep trenches to form a backside deep trench isolation (BDTI) structure.

[0005] Some further embodiments of the present application provide an integrated circuit, including: an image sensing die having a plurality of pixel regions, each including a photodiode configured to convert radiation entering the image sensing die from a back side into an electrical signal, the photodiode including a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type; a backside deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending from a back side of the image sensing die to a position within the photodiode doping layer, wherein the BDTI structure includes a doped liner having the second doping type and a dielectric fill layer, the doped liner lining sidewall surfaces of the dielectric fill layer; a doped isolation well having the second doping type, disposed between the adjacent pixel regions and extending from a front side of the image sensing die opposite to the back side to a position within the photodiode doping layer; a metallization stack disposed on the front side and including a plurality of metal interconnect layers disposed within an interlayer dielectric layer; and a logic die bonded to the front side of the image sensing die, the logic die including logic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0007] Figure 1A cross-sectional view of some embodiments of a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor having a photodiode surrounded by a backside deep trench isolation (BDTI) structure with a doped pad is shown.

[0008] Figure 2 A cross-sectional view of some other embodiments of an image sensor is shown, the image sensor including a photodiode surrounded by a BDTI structure with a doped pad.

[0009] Figure 3 A cross-sectional view of some other embodiments of an image sensor is shown, the image sensor including a photodiode surrounded by a BDTI structure with a doped pad.

[0010] Figure 4 A cross-sectional view of some embodiments of an integrated chip is shown, the integrated chip including an image sensing die and a logic die bonded together, wherein the image sensing die has a photodiode surrounded by a BDTI structure with a doped pad.

[0011] Figure 5A A schematic view of an image sensor is shown, the image sensor including a photodiode isolated by a deep isolation well and a BDTI structure without a doped pad.

[0012] Figure 5B A schematic view of some embodiments of an image sensor is shown, the image sensor including a photodiode isolated by a shallow isolation well and a BDTI structure with a doped pad.

[0013] Figures 6 to 20 A cross-sectional view of some embodiments is shown, the cross-sectional view showing a method of forming an image sensor having a photodiode surrounded by a BDTI structure with a conformal doped layer.

[0014] Figure 21 A flowchart of some embodiments of a method of forming an image sensor having a photodiode surrounded by a BDTI structure with a conformal doped layer is shown. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components may be formed between the first and second components so that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] Integrated circuit (IC) technology is constantly improving. Such improvements generally involve reducing the geometric dimensions of devices to achieve lower manufacturing costs, higher device integration densities, higher speeds, and better performance. Due to device scaling, pixel sensors of image sensors have smaller sizes and are closer to each other. Improved electrical and optical isolation between adjacent pixels of an image sensor is needed to reduce high-light spillover and crosstalk. Dielectric trenches and implanted wells can be fabricated as isolation structures to isolate image sensor pixels. An image sensor manufacturing process includes an implantation process of forming a deep implanted well of a certain depth through a photodiode as an isolation wall. However, in addition to manufacturing complexity, these implantation processes also include thick photoresist layers that reduce exposure resolution. For example, if the critical dimension is less than 0.2 μm, it is difficult to achieve precise lithography processes using a photoresist layer greater than 3 μm. Moreover, in order to form a deep implanted well of a certain depth through a photodiode, as the implantation process continues, the width of the deep implanted well increases. Therefore, due to the presence of the deep implanted well, the area of the photodiode decreases. The reduced photodiode area results in a reduced amount of charge that the photodiode can accommodate, and thus the full well capacity of the photodiode decreases and is limited by the implantation profile, which has a negative impact on the performance of the image sensor.

[0018] In view of the above, the present invention relates to an image sensor and a related forming method. The image sensor includes a backside deep trench isolation (BDTI) structure having a doped liner. In some embodiments, the image sensor has a plurality of pixel regions disposed within an image sensing die. The pixel regions each have a photodiode configured to convert radiation into an electrical signal. The photodiode includes a photodiode doping column having a first doping type, and the photodiode doping column is surrounded by a substrate having a second doping type different from the first doping type. The BDTI structure is disposed between adjacent pixel regions and extends from the backside of the image sensing die to a position within the photodiode doping layer. The BDTI structure includes a doped liner having the second doping type and a dielectric fill layer. The doped liner lines the sidewall surfaces of the deep trench, and the dielectric fill layer fills the interior space of the deep trench. Since the BDTI structure serves as a depth depletion and isolation structure between adjacent pixels, a deep implantation is not required. Therefore, the implantation process from the front side of the substrate does not need to extend as deep as before to serve as an isolation and depletion structure, and thus can be performed in a shorter time and simplified. Additionally, since the time for performing the implantation process is shorter than before, the width of the doped region on the front side of the substrate is narrower. Accordingly, the lateral area of each photodiode can be enlarged, where the boundary between the photodiodes is narrower, and more pixels can be arranged in a specific chip area, thereby improving the exposure resolution. Additionally, as described above, since the BDTI structure having a doped liner can be narrower than a deep implantation well, the effective photodiode area can be enlarged, and the full well capacity of the photodiode can be increased.

[0019] The doped liner can be formed by various techniques. In some embodiments, the doped liner is formed by an enhanced plasma doping process, where a protective layer first lines the bottom and sidewall surfaces of the deep trench between adjacent pixel regions. The protective layer helps to avoid damage from direct implantation and obtain a more uniform thickness, a smoother surface, and a lower surface concentration of the doped liner. Accordingly, the surface of the doped liner has fewer defects, and the dark current of the image sensor device can be significantly improved. The protective layer is then removed, and a low temperature annealing is performed after the plasma doping process for dopant activation. As an example for non-limiting purposes, the annealing temperature can be in the range from 250 °C to about 500 °C. In some alternative embodiments, the doped liner is formed by a low temperature epitaxial process, followed by a laser or microwave annealing process for dopant activation. More details of the method for forming the doped liner are described in conjunction with Figures 13 to 15 discussion.

[0020] Figure 1FIG. 100 is a cross-sectional view showing some embodiments of an image sensor having a photodiode surrounded by a BDTI structure with a conformal photodiode doping layer. The image sensing die 134 has a front side 122 and a back side 124. The image sensing die 134 includes a plurality of pixel regions that may be arranged in an array including rows and / or columns, such as Figure 1 the pixel regions 103a, 103b shown. The pixel regions 103a, 103b each include a photodiode 104 configured to convert incident radiation or incident light 120 (e.g., photons) into an electrical signal. In some embodiments, the photodiode 104 includes a first region, such as a photodiode doping pillar 104a having a first doping type (e.g., p-type doping by a dopant such as boron, aluminum, indium, etc.), and an adjacent second region, such as a photodiode doping layer 128 having a second doping type different from the first doping type (e.g., n-type doping by a dopant such as phosphorus, arsenic, antimony, etc.).

[0021] A BDTI structure 111 is disposed between adjacent pixel regions 103a, 103b and isolates the adjacent pixel regions 103a, 103b. The BDTI structure 111 may extend from the back side 124 of the image sensing die 134 to a position within the photodiode doping layer 128. In some embodiments, the BDTI structure 111 includes a doped liner 114 having a first doping type (e.g., p-type doping) and a dielectric fill layer 112. The doped liner 114 lines the sidewall surfaces of the deep trenches of the photodiode doping layer 128, and the dielectric fill layer 112 fills the remaining space of the deep trenches. The doped liner 114 may include silicon or other semiconductor materials doped with boron or other p-type dopants, or be made of silicon or other semiconductor materials doped with boron or other p-type dopants. The dielectric fill layer 112 may be made of silicon dioxide, silicon nitride, and / or other suitable dielectric materials. In some embodiments, the depth range of the BDTI structure 111 may be between about 1.5 μm and about 5 μm. The lateral dimension range of the BDTI structure 111 may be between about 0.1 μm and about 0.3 μm. The lateral dimension of the BDTI structure 111 should be sufficient to form a doped liner 114 and other layers (e.g., as described below in connection with Figures 13 to 16 ). In some embodiments, the dopant concentration of the doped liner 114 may be in the range between about 5E17 atoms / cm 3 to about 1E19 atoms / cm 3 . The thickness of the doped liner 114 may be in the range between about 4 nm and about 20 nm. The uniformity of the doped liner 114 from top to bottom is greater than 90%. The surface concentration of the doped liner 114 is less than 1E19 / cm 2。The surface roughness of the doped liner 114 is also improved. In some embodiments, the more uniform thickness, smoother surface, and lower surface concentration of the doped liner 114 are produced by an enhanced plasma doping process with a protective layer. More details of the method for forming the doped liner are described in conjunction with Figures 13 to 15 discussed.

[0022] In some embodiments, a doped isolation well 110 is also disposed between adjacent pixel regions 103a, 103b and isolates the adjacent pixel regions 103a, 103b, extending from the front side 122 of the image sensor die 134 to a position within the photodiode doping layer 128. The doped isolation well 110 may have a first doping type (e.g., p-type doping). The doped isolation well 110 may be vertically aligned with the BDTI structure 111 (e.g., sharing a common centerline 126). In some embodiments, the bottom of the BDTI structure 111 may be disposed within the recessed top surface of the doped isolation well 110, as Figure 1 shown. In this case, the doped isolation well 110 may reach a depth less than half or even less than 1 / 4 of the BDTI structure 111. In some alternative embodiments, the doped isolation well 110 may be separated from the BDTI structure 111 by the photodiode doping layer 128, as Figure 2 shown. By forming a shallower doped isolation well 110, the width of the isolation well 110 is narrower because the time for performing the implantation process for the isolation well is shorter than before. Therefore, the lateral area of each photodiode can be enlarged, the boundary therebetween is narrower, and more pixels can be arranged in a specific chip area, thereby improving the exposure resolution. In addition, the area of the photodiode can be enlarged, and the full well capacity of the photodiode can be increased. More explanations related to the shallow doped isolation well can be associated with the following Figures 5A to 5B associated. The BDTI structure 111 and the doped isolation well 110 together serve as the isolation of the pixel regions 103a, 103b, thereby reducing crosstalk and high-light spillover between the pixel regions 103a, 103b. Since the BDTI structure 111 and the doped isolation well 110 provide additional p-type dopants to the photodiode 104, the BDTI structure 111 and the doped isolation well 110 also jointly promote the depletion of the photodiode 104 during operation, thereby increasing the full well capacity.

[0023] In some embodiments, a plurality of color filters 116 are disposed above the backside 124 of the image sensor die 134. The plurality of color filters 116 are each configured to transmit incident radiation or incident light 120 of a specific wavelength. For example, a first color filter (e.g., a red color filter) may transmit light having a wavelength within a first range, while a second color filter may transmit light having a wavelength within a second range different from the first range. In some embodiments, the plurality of color filters 116 may be disposed within a grid structure that covers the photodiodes 104. In some embodiments, the grid structure may include a stacked grid having a metal frame surrounded by a dielectric material. In some embodiments, the dielectric material layer and the stacked grid may have the same dielectric material (e.g., silicon dioxide (SiO2)).

[0024] A plurality of microlenses 118 are disposed above the plurality of color filters 116. The respective microlenses 118 are laterally aligned with the color filters 116 and are located above the pixel regions 103a, 103b. In some embodiments, the plurality of microlenses 118 have a substantially flat bottom surface adjacent to the plurality of color filters 116 and a curved upper surface. The curved upper surface is configured to focus the incident radiation or incident light 120 (e.g., light toward the underlying pixel regions 103a, 103b). During operation of the image sensor, the incident radiation or incident light 120 is focused by the microlenses 118 onto the underlying pixel regions 103a, 103b. When the incident radiation or incident light having sufficient energy hits the photodiode 104, it generates an electron-hole pair that produces a photocurrent. It should be noted that although the microlenses 118 are shown as being fixed to the image sensor in Figure 1 , it should be understood that the image sensor may not include microlenses and the microlenses may be attached to the image sensor at a later separate manufacturing activity.

[0025] Figure 2Cross-sectional view 200 showing some additional embodiments of an image sensor, the image sensor including a photodiode 104 surrounded by a BDTI structure 111 having a doped liner 114. As described above, in some embodiments, the doped isolation well 110 may be separated from the BDTI structure 111 by the photodiode doping layer 128. In some embodiments, the BDTI structure 111 further includes a high-k dielectric liner 113 disposed between the doped liner 114 and the dielectric fill layer 112 and separating the doped liner 114 from the dielectric fill layer 112. The high-k dielectric liner 113 may be a conformal layer. The high-k dielectric liner 113 may include, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), tantalum oxide (Ta2O5), or hafnium tantalum oxide (HfTaO). Other suitable high-k dielectric materials are also within the scope of the present invention. In some embodiments, the thickness of the high-k dielectric liner 113 may range between about 30 nm and about 100 nm and may be made of a composite of various high-k dielectric materials. The doped liner 114, the high-k dielectric liner 113, and the dielectric fill layer 112 may extend laterally along the backside 124 of the image sensor die 134. Figure 2 The image sensor shown in Figure 2 may be an intermediate structure, and the doped liner 114, the high-k dielectric liner 113, and the dielectric fill layer 112 may or may not be subjected to a planarization process, thereby altering the top surfaces of the layers.

[0026] In some embodiments, the floating diffusion well 204 is disposed between adjacent pixel regions 103a, 103b from the front side 122 of the image sensor die 134 to a position within the photodiode doping layer 128. The transfer gate 202 is disposed above the photodiode doping layer 128 at a lateral position between the photodiode 104 and the floating diffusion well 204. During operation, the transfer gate 202 controls the charge transfer from the photodiode 104 to the floating diffusion well 204. If the charge level in the floating diffusion well 204 is high enough, a source follower transistor (not shown) is activated and the charge is selectively output according to the operation of a row select transistor (not shown) for addressing. A reset transistor (not shown) may be used to reset the photodiode 104 between exposure cycles.

[0027] Figure 3 Cross-sectional view 300 showing some additional embodiments of an image sensor, the image sensor including a photodiode 104 surrounded by a BDTI structure 111 having a doped liner 114. In addition to the similar components shown and described above for Figure 1 and Figure 2 shown and described, in some embodiments, as Figure 3As shown, a shallow trench isolation (STI) structure 302 is disposed between adjacent pixel regions 103a, 103b from the front side 122 of the image sensor die 134 to a position within the photodiode doping layer. The STI structure 302 and the BDTI structure 111 may be vertically aligned (e.g., sharing a common centerline 304, which may or may not share a centerline with the doped isolation well 110). In some embodiments, the doped isolation well 110 extends from the front side 122 of the image sensor die 134 into the photodiode doping layer 128 and surrounds the position of the STI structure 302. The doped isolation well 110 may separate the STI structure 302 from the photodiode doping layer 128 and / or the BDTI structure 111. It should be understood that Figure 1 and Figure 2 the components shown and described above may be incorporated into embodiments associated with Figure 3 For example, although Figure 3 shows the doped isolation well 110 separated from the BDTI structure 111 by the photodiode doping layer, the doped isolation well 110 may reach an upper portion similar to the Figure 1 shown BDTI structure 111. In this case, the STI structure 302 may be in contact with or separated from the BDTI structure 111. The BDTI structure 111, the doped isolation well 110, and the STI structure 302 together serve as isolation for the pixel regions 103a, 103b, thereby reducing crosstalk and high-light spillover between the pixel regions 103a, 103b. The doped pad 114 of the BDTI structure 111 and the doped isolation well 110 also jointly facilitate the depletion of the photodiode 104 during operation, thereby increasing the full well capacity.

[0028] Figure 4 FIG. 400 shows a cross-sectional view of some embodiments of an integrated chip that includes an image sensor die 134 and a logic die 136 bonded together, wherein the image sensor die 134 has a photodiode 104 surrounded by a BDTI structure 111 having a doped pad 114. In some embodiments, the image sensor die 134 may have an upper surface that is Figures 1 to 3Structures shown and described in association. The image sensor die 134 may also include a composite grid 406 disposed on the substrate 102' between adjacent pixel regions 103a, 103b. The composite grid 406 may include a metal layer 402 and a dielectric layer 404 stacked on each other at the back side 124 of the image sensor die 134. The dielectric pads 408 line the sidewalls and the top of the composite grid 406. The metal layer 402 may be one or more layers of tungsten, copper, aluminum copper, or titanium nitride or consist of one or more layers of tungsten, copper, aluminum copper, or titanium nitride. The thickness range of the metal layer 402 may be between about 100 nm and about 500 nm. The dielectric layer 404 may be one or more layers of silicon dioxide, silicon nitride, or a combination thereof or consist of one or more layers of silicon dioxide, silicon nitride, or a combination thereof. The thickness range of the dielectric layer 404 may be between about 200 nm and about 800 nm. The dielectric pad 408 may be an oxide such as silicon dioxide or consist of an oxide such as silicon dioxide. The thickness range of the dielectric pad 408 may be between about 5 nm and about 50 nm. Other suitable metal materials are also within the scope of the present invention. The metallization stack 108 may be disposed on the front side 122 of the image sensor die 134. The metallization stack 108 includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric (ILD) layers 106. The ILD layer 106 may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0029] The logic die 136 may include logic devices 142 disposed above a substrate 140. The logic die 136 may also include a metallization stack 144 disposed within an ILD layer 146 that covers the logic devices 142. The image sensor die 134 and the logic die 136 may be face-to-face, face-to-back, or back-to-back bonded. As an example for non-limiting purposes, Figure 4 a face-to-face bonding structure is shown, in which a pair of intermediate bonding dielectric layers 138, 148 and bonding pads 150, 152 are disposed between the image sensor die 134 and the logic die 136 and bond to the metallization stacks 108, 144, respectively. In some embodiments, the bonding process may include a fusion bonding or an eutectic bonding process.

[0030] Figure 5AFIG. 500a shows a schematic simulation diagram of an image sensing die 134', which includes a photodiode 104' isolated by a BDTI structure 111' and a deep isolation well 110'. The BDTI structure 111' extends from the back side 124 of the image sensing die 134', and the deep isolation well 110' extends from the front side 122 of the image sensing die 134'. The BDTI structure 111' may not have a doped pad. The deep isolation well 110' extends vertically to a deep low position and reaches the BDTI structure 111'. The deep isolation well 110' may penetrate half or even more than 3 / 4 of the depth of the BDTI structure 111'. The photodiode 104' extends from the front side 122 and may be read by a transfer gate 202, as described in connection with Figure 2 As described. The deep isolation well 110' may be formed by implantation and provides isolation for the photodiode 104'. However, due to its depth requirement, it is difficult to form the deep isolation well 110'. The implantation process involves a thick photoresist layer, which reduces the exposure resolution. Moreover, due to the presence of the deep isolation well 110', the photodiode area of the photodiode 104' is reduced, and the full well capacity of the deep isolation well 110' is limited by the implantation profile, which adversely affects the performance of the image sensing die 134'.

[0031] Figure 5B FIG. 500b shows a schematic simulation diagram of an improved image sensing die 134, which includes a photodiode 104 isolated by a BDTI structure 111 having a doped pad 114 extending from the back side 124 and a doped isolation well 110 extending from the front side. The doped isolation well 110 may be shallowly implanted. In some embodiments, similar to as shown in Figure 2 As shown, the doped isolation well 110 is vertically separated from the BDTI structure 111. In some alternative embodiments, the doped isolation well 110 reaches the upper part of the BDTI structure 111, similar to as shown in Figure 1 As shown. In this case, the doped isolation well 110 may reach a depth less than half or even less than 1 / 4 of the BDTI structure 111. By forming a shallower doped isolation well 110, the exposure resolution is improved and the implantation process is simplified. In addition, the photodiode area can be enlarged and the full well capacity of the photodiode is increased. For comparison purposes, Figure 5A The deep isolation well 110' and the resulting narrower photodiode 104' of Figure 5B are reproduced on Figure 5A The photodiode area of the photodiode 104 is approximately 5% to 15% larger than that of the photodiode 104' of the image sensing die 134' of Figure 5A The full well capacity of the photodiode 104 is approximately 10% larger than that of the photodiode 104' of the image sensing die 134' of

[0032] Figures 6 to 20 Some embodiments of cross-sectional views 600-2000 are shown, which illustrate a method of forming an image sensor having a photodiode surrounded by a BDTI structure with doped pads. Although doping types are provided as examples for different doped regions, it should be understood that reverse doping types can be used for these doped regions to implement a reverse image sensor device structure.

[0033] As Figure 6 shown in cross-sectional view 600 of [], a substrate 102' is provided for the image sensing die 134. In various embodiments, the substrate 102' can include any type of semiconductor body (e.g., silicon / germanium / CMOS body, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith. For example, a pixel array deep p-type well 132 can be formed on the processing substrate 102. The processing substrate 102 can be a highly doped p-type substrate layer or consist of a highly doped p-type substrate layer. A pixel array deep n-type well 130 can be formed on the pixel array deep p-type well 132. The pixel array deep n-type well 130 and the pixel array deep p-type well 132 can be formed by an implantation process. In some embodiments, a photodiode doping layer 128 is formed as an upper portion of the substrate 102'. The photodiode doping layer 128 can be formed by a p-type epitaxial process. In some embodiments, a plurality of shallow trench isolation (STI) structures 302 are formed at the boundary from the front side 122 of the image sensing die 134 to a position within the photodiode doping layer 128 and / or between adjacent pixel regions 103a, 103b. One or more STI structures 302 can be formed by selectively etching the front side 122 of the image sensing die 134 to form shallow trenches and then forming oxides within the shallow trenches.

[0034] As Figure 7 shown in cross-sectional view 700 of [], dopant species are implanted into the photodiode doping layer 128 to form doped regions. A plurality of photodiode doping columns 104a are formed by implanting an n-type dopant species within the pixel regions 103a, 103b, respectively. A plurality of doped isolation wells 110 can be formed by implanting a p-type dopant species into the photodiode doping layer 128 between adjacent pixel regions 103a, 103b. The plurality of doped isolation wells 110 can be formed from the front side 122 of the image sensing die 134 to a position deeper than the STI structures 302. The doped isolation wells 110 can be centered with respect to the STI structures 302, respectively. In some embodiments, the photodiode doping layer 128 can be selectively implanted according to a patterned mask layer (not shown) including photoresist.

[0035] As Figure 8As shown in the cross-sectional view 800, the transfer gate 202 is formed above the front side 122 of the image sensor die 134. The transfer gate 202 can be formed by depositing a gate dielectric film and a gate electrode film above the substrate 102'. Subsequently, the gate dielectric film and the gate electrode film are patterned to form a gate dielectric layer and a gate electrode. Sidewall spacers can be formed on the outer sidewalls of the gate electrode. In some embodiments, the sidewall spacers can be formed by depositing nitride onto the front side 122 of the image sensor die 134 and selectively etching the nitride to form the sidewall spacers. As Figure 7 shown, an implantation process is performed within the front side 122 of the image sensor die 134 to form the floating diffusion wells 204 along one side of the transfer gate 202 or opposite sides of a pair of transfer gates 202.

[0036] As Figure 9 shown in the cross-sectional view 900, the metallization stack 108 can be formed from the front side 122 of the image sensor die 134. In some embodiments, the metallization stack 108 can be formed by forming an ILD layer 106 including one or more ILD materials above the front side 122 of the image sensor die 134. Subsequently, the ILD layer 106 is etched to form vias and / or metal trenches. Then the vias and / or metal trenches are filled with a conductive material to form a plurality of metal interconnect vias 506 and metal lines 508. In some embodiments, the ILD layer 106 can be deposited by physical vapor deposition techniques (e.g., PVD, CVD, etc.). The plurality of metal interconnect layers can be formed using deposition processes and / or plating processes (e.g., electroplating, electroless plating, etc.). In various embodiments, the plurality of metal interconnect layers can include, for example, tungsten, copper, or aluminum copper.

[0037] As Figure 10 shown in the cross-sectional view 1000, the image sensor die 134 can then be bonded to one or more other dies. For example, the image sensor die 134 can be bonded to a logic die 136 that is to have a logic device 142. The image sensor die 134 and the logic die 136 can be bonded face-to-face, face-to-back, or back-to-back. For example, the bonding process can use a pair of intermediate bonding dielectric layers 138, 148 and bonding pads 150, 152 to bond the metallization stacks 108, 144 of the image sensor die 134 and the logic die 136. The bonding process can include a fusion bonding or a eutectic bonding process. The bonding process can also include a composite bonding process that includes a metal-to-metal bonding of the bonding pads 150, 152 and a dielectric-to-dielectric bonding of the intermediate bonding dielectric layers 138, 148. An annealing process can be performed after the composite bonding process and can be performed, for example, at a temperature in the range of about 250°C to about 450°C for a time in the range of about 0.5 hours to about 4 hours.

[0038] As Figure 11As shown in the cross-sectional view 1100, the image sensing die 134 is thinned on the back side 124 opposite the front side 122. The thinning process can partially or completely remove the processing substrate 102 (see Figure 10 ), and allows radiation to pass through the back side 124 of the image sensing die 134 to reach the photodiode 104. The substrate 102' can be thinned by etching the back side 124 of the image sensing die 134. Optionally, the substrate 102' can be thinned by mechanically grinding the back side 124 of the image sensing die 134. As an example for non-limiting purposes, the substrate 102' can first be ground to a thickness range of about 17 μm to about 45 μm. Then, an aggressive wet etch can be applied to further thin the substrate 102'. Examples of the etchant can include HF / nitric acid / acetic acid (HNA). Then a chemical mechanical process and a tetramethylammonium hydroxide (TMAH) wet etch can be subsequently performed to further thin the thickness range between about 2.8 μm and about 7.2 μm, so that radiation can pass through the back side 124 of the image sensing die 134 to reach the photodiode 104.

[0039] As Figure 12 shown in the cross-sectional view 1200, the substrate 102' is selectively etched to form deep trenches 1202 in the back side 124 of the image sensing die 134 that laterally separate the photodiodes 104. In some embodiments, the substrate 102' can be etched by forming a mask layer on the back side 124 of the image sensing die 134. Then the substrate 102' is exposed to the etchant in the areas not covered by the mask layer. The etchant etches the substrate 102' to form deep trenches 1202 that extend into the substrate 102'. In various embodiments, the mask layer can include a photoresist or a nitride (e.g., SiN) patterned using a lithography process. The mask layer can also include an ALD or plasma enhanced CVD oxide layer with a thickness range between about 200 angstroms to about 1000 angstroms . In various embodiments, the etchant can include a dry etchant having an etching chemistry (including fluorine species (e.g., CF4, CHF3, C4F8, etc.)) or a wet etchant (e.g., hydrofluoric acid (HF) or tetramethylammonium hydroxide (TMAH)). The depth range of the deep trenches 1202 can be between about 1.5 μm and about 5 μm. The critical dimension can be in the range between about 0.1 μm and about 0.3 μm. In some embodiments, the deep trenches 1202 are formed to vertically extend into the doped isolation well 110 and create a recessed bottom surface for the doped isolation well 110.

[0040] Figures 13 to 15 Some embodiments of a method for forming a doped pad 114 using an enhanced plasma doping process with a protective layer are shown (see Figure 14 or Figure 15 ).

[0041] As shown Figure 13 in cross-sectional view 1300 of FIG., a protective layer 1302 is formed along the sidewalls of the deep trench 1202. In some embodiments, the protective layer 1302 comprises or is made of a dielectric material, such as silicon dioxide, silicon nitride, or a combination thereof. The protective layer 1302 may also comprise or be made of a photoresist material. The protective layer 1302 may be made by a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). As an example for non-limiting purposes, the protective layer 1302 may be made by an ALD process in a temperature range of about 250 °C to about 350 °C to form a dielectric layer having a thickness in the range of about 1 nm to about 10 nm.

[0042] As shown Figure 14 in cross-sectional view 1400 of FIG., a doped liner 114 is formed under the protective layer 1302. The doped liner 114 may be formed by a plasma doping process. As an example for non-limiting purposes, the process gas may include boron trifluoride (BF3), diborane (B2H6), helium (He), argon (Ar), or other suitable gases. The dose concentration of the dopant gas (e.g., BF3, B2H6, etc.) may be in the range of about 1E14 atoms / cm 2 to about 2E17 atoms / cm 2 , the energy may be in the range of about 1 keV to about 12 keV, and the flow rate may be in the range of about 50 sccm to about 150 sccm. The plasma doping process may be performed at a pressure in the range of about 6 mtorr to about 18 mtorr and at a plasma power in the range of about 600 W to about 800 W. The dopant concentration of the doped liner 114 may be in the range of about 5E17 atoms / cm 3 to about 1E19 atoms / cm 3 . By using a plasma doping process to form the doped liner 114 with the protective layer 1302 in place, the dopant concentration of the doped liner 114 can be made larger and the thickness or junction depth can be made smaller compared to other forming methods such as implantation. The thickness of the doped liner 114 can be better controlled by controlling the thickness of the protective layer 1302.

[0043] As shown Figure 15 in cross-sectional view 1500 of FIG., after the doped liner 114 is formed, the protective layer 1302 is removed. As an example for non-limiting purposes, the removal process may be performed by wet etching with hydrofluoric acid (HF) for the dielectric material or a plasma etching process with oxygen, followed by wet stripping of the photoresist material.

[0044] The above combination Figures 13 to 15The described enhanced plasma doping process provides an improved conformal doping layer with a more uniform thickness, uniform doping concentration, smoother surface, and lower surface concentration by using the protective layer 1302. In some embodiments, the uniformity from the top to the bottom of the doping liner 114 is greater than 90%, which is an improvement over the uniformity of the doping layer formed without the protective layer. In some embodiments, the surface roughness can be reduced compared to the surface roughness of the doping layer formed without the protective layer. The surface concentration can be reduced from 1E22 to 1E19 / cm 2 , or less than 1E20 / cm 2 . Additionally, the doping profile can be better controlled by adjusting the thickness of the protective layer 1302. A thicker protective layer 1302 can help form a thinner doping liner 114, such as less than 20 nm or less than 5 nm. As a result, the dark current of the image sensor device formed by the enhanced plasma doping process can be reduced by about 74% compared to other methods without using the protective layer.

[0045] As an alternative to the above-described enhanced plasma doping process, the doping liner 114 can also be formed by a low-temperature epitaxial growth process (e.g., an epitaxial growth process with a temperature below 500 °C). As an example for non-limiting purposes, the process gas can include silane (SiH4), dichlorosilane (DCS or H2SiCl2), B2H6, hydrogen gas (H2), or other suitable gases. The epitaxial growth process can be performed at a temperature in the range of about 400 °C to about 480 °C and at a pressure in the range of about 4 Torr to about 200 Torr to form an epitaxial doped layer with a thickness in the range of about 4 nm to about 20 nm as the doping liner 114. The dopant concentration of the doping liner 114 can be in the range of about 5E16 atoms / cm 3 to about 5E18 atoms / cm 3 . In some alternative embodiments, the doping liner 114 can be formed by atomic layer deposition process or other suitable techniques without forming and removing the protective layer 1302. Both the enhanced plasma doping process and the low-temperature epitaxial process will result in better uniformity than conventional beamline implantation techniques, which suffer from the shadow effect of three-dimensional structures and cannot achieve the desired uniformity.

[0046] Then, after the doping liner 114 is formed, using the combination Figures 13 to 15For the described enhanced plasma doping process or the aforementioned low-temperature epitaxial growth process, a dopant activation process is performed. In some embodiments, the dopant activation process includes or is a microwave annealing process. As an example for non-limiting purposes, the annealing gas may include nitrogen or hydrogen with a flow rate in the range between about 1 slm and about 20 slm. The annealing power may be in the range between about 3000 W and about 8000 W. The annealing time may be in the range between about 1 minute and about 20 minutes. In some alternative embodiments, the dopant activation process includes or is a microwave annealing process. As an example for non-limiting purposes, annealing may use a green laser with an energy density range between about 0.3 J and about 3 J, and a time range between about 10 nanoseconds and about 100 nanoseconds. The wafer stage temperature may reach a range between about 250 °C and about 500 °C. The dopant activation process is beneficial for low thermal budget products, especially compared to other methods, such as the thermal drive-in process after a deposition process, which either cannot provide sufficient junction depth or is not acceptable for low thermal budget products due to high-temperature junction drive-in and annealing for damage recovery and dopant activation.

[0047] As Figure 16 shown in the cross-sectional view 1600 of , the deep trench 1202 is then filled with a dielectric material. In some embodiments, a high-k dielectric liner 113 is formed on the doped liner 114 within the deep trench 1202. The high-k dielectric liner 113 can be formed by deposition techniques and can include aluminum oxide (AlO), hafnium oxide (HfO), tantalum oxide (TaO), or other dielectric materials with a dielectric constant greater than that of silicon dioxide. The doped liner 114 and the high-k dielectric liner 113 line the sidewalls and bottom surface of the deep trench 1202. In some embodiments, the doped liner 114 and the high-k dielectric liner 113 may extend above the backside 124 of the image sensor die 134 between the deep trenches 1202. A dielectric fill layer 112 is formed to fill the remaining portion of the deep trench 1202. In some embodiments, a planarization process is performed after forming the dielectric fill layer 112 to form a flat surface extending along the upper surfaces of the high-k dielectric liner 113 and the dielectric fill layer 112. In some embodiments, the high-k dielectric liner 113 and the dielectric fill layer 112 can be deposited using physical vapor deposition techniques or chemical vapor deposition techniques. As a result, the BDTI structure 111 is formed in the substrate 102’, extending from the backside 124 to a position within the photodiode doping layer 128. The BDTI structure 111 is formed between adjacent pixel regions 103a, 103b and isolates them.

[0048] Figures 17 to 19 Some embodiments of a method of forming a composite grid 406 are shown, which is formed to surround an opening 1802 above the photodiode doping column 104a (see Figure 18 ). As Figure 17As shown in the cross-sectional view 1700, the metal layer 402 and the dielectric layer 404 are stacked over the substrate 102' along the backside 124 of the image sensor die 134. The metal layer 402 may be one or more layers of tungsten, copper, aluminum copper, or titanium nitride or composed of one or more layers of tungsten, copper, aluminum copper, or titanium nitride. Other suitable metal materials are also within the scope of the present invention. The dielectric layer 404 may be one or more layers of silicon dioxide, silicon nitride, or a combination thereof or composed of one or more layers of silicon dioxide, silicon nitride, or a combination thereof. The dielectric layer 404 may be used as a hard mask layer. As Figure 18 As shown in the cross-sectional view 1800, the metal layer 402 and the dielectric layer 404 are etched to form a composite grid 406. The opening 1802 may be centered with respect to the photodiode doping column 104a such that the composite grid 406 is disposed around and between the photodiode doping columns 104a. Optionally, the opening 1802 may be laterally shifted or offset from the photodiode doping column 104a in at least one direction such that the composite grid 406 is at least partially over the photodiode doping column 104a. As Figure 19 As shown in the cross-sectional view 1900, a dielectric liner 408 is formed to line the sidewalls and the top of the composite grid 406 and to line the opening 1802. Generally, conformal deposition techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are used to form the dielectric liner 408. The dielectric liner 408 may be formed of an oxide, such as silicon dioxide, for example.

[0049] As Figure 19 shown, a color filter 116 corresponding to the pixel sensor is formed in the opening 1802 of the corresponding pixel sensor. The color filter layer is formed of a material that allows light of the corresponding color to pass through while blocking light of other colors. Additionally, the color filter 116 may be formed with a designated color. For example, the color filter 116 may optionally be formed with the designated colors of red, green, and blue. The color filter 116 may be formed with an upper surface that is aligned with the upper surface of the composite grid 406. The color filter 116 may be laterally shifted or offset from the photodiode doping column 104a of the corresponding pixel sensor in at least one direction. Depending on the degree of the shift or offset, the color filter 116 may partially fill the opening of the corresponding pixel sensor and may partially fill the opening of a pixel sensor adjacent to the corresponding pixel sensor. Optionally, the color filter 116 may be symmetric about a vertical axis that is centered with respect to the photodiode of the corresponding pixel sensor.

[0050] The process for forming the color filter 116 may include, for each different color of the color assignment, forming a color filter layer and patterning the color filter layer. The color filter layer may be planarized after being formed. Patterning may be performed by forming a patterned photoresist layer over the color filter layer, applying an etchant to the color filter layer according to the pattern of the photoresist layer, and removing the patterned photoresist layer.

[0051] AsFigure 20 As shown, a microlens 118 corresponding to a pixel sensor is formed above a color filter 116 of the corresponding pixel sensor. In some embodiments, multiple microlenses may be formed by depositing microlens material (e.g., by a spin coating method or a deposition process) above multiple color filters. A microlens template having a curved upper surface is patterned above the microlens material. In some embodiments, the microlens template may include a photoresist material exposed with a distributed exposure dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed and baked to form a rounded shape. The microlens 118 is then formed by selectively etching the microlens material according to the microlens template.

[0052] Figure 21 A flowchart of some embodiments of a method of forming an image sensor 2100 is shown, the image sensor having a photodiode surrounded by a BDTI structure with a conformal doping layer.

[0053] Although the disclosed method 2100 is illustrated and described herein in terms of a series of operations or events, it should be understood that it is not limited to the order of the operations or events shown. For example, some operations may occur in a different order and / or concurrently with other operations or events than those shown and / or described herein. Additionally, not all illustrated operations are required to implement one or more aspects or embodiments described herein. Further, one or more of the operations described herein may be performed in one or more separate operations and / or phases.

[0054] In operation 2102, a substrate is prepared for the image sensor. A photodiode and doped isolation wells are formed from the front side of the image sensor. In some embodiments, an epitaxial layer is formed above the processing wafer as the photodiode doping layer, and the photodiode doping pillars and / or doped isolation wells may be formed by implanting a dopant species into the front side of the image sensing die. The doped isolation wells may be formed by selective implantation to form multiple columns extending into the photodiode doping layer. In some embodiments, shallow trench isolation regions may be formed in the front side of the image sensing die by selectively etching the substrate to form shallow trenches and then forming a dielectric (e.g., oxide) within the shallow trenches. Figures 6 to 7 A cross-sectional view corresponding to some embodiments corresponding to operation 2102 is shown.

[0055] In operation 2104, a transfer gate is formed from the front side of the substrate. A metallization stack is formed above the transfer gate on the front side of the substrate. Figures 8 to 9 A cross-sectional view corresponding to some embodiments corresponding to operation 2104 is shown.

[0056] In operation 2106, in some embodiments, an image sensor is bonded to one or more other dies, such as a logic die or other image sensing dies. Figure 10 A cross-sectional view corresponding to some embodiments corresponding to operation 2106 is shown.

[0057] In operation 2108, the substrate is thinned for further processing. The processing substrate can be partially or completely removed from the backside of the substrate. Then, the substrate is selectively etched to form deep trenches that are located between adjacent sensing pixel regions and extend into the substrate. The deep trenches can have a centerline aligned with the centerline of the doped isolation wells and / or shallow trench isolation regions. Figures 11 to 12 A cross-sectional view corresponding to some embodiments corresponding to operation 2108 is shown.

[0058] In operation 2110, a doped liner is formed along the sidewalls and bottom of the deep trenches. In some embodiments, the doped liner can be formed by an epitaxial process. The epitaxial process can be performed at a relatively low temperature. In some alternative embodiments, the doped liner can be formed by an enhanced plasma doping process with a protective layer in place. Operations 2112 to 2116 illustrate an example of the enhanced plasma doping process. In operation 2112, a protective layer is formed on the sidewalls and bottom surfaces of the deep trenches. Figure 13 A cross-sectional view corresponding to some embodiments corresponding to operation 2112 is shown. In operation 2114, a plasma doping process is performed to form a doped liner between the protective layer and the substrate within the deep trenches. Figure 14 A cross-sectional view corresponding to some embodiments corresponding to operation 2114 is shown. In operation 2116, after the plasma doping process, the protective layer is removed from the deep trenches. Figure 15 A cross-sectional view corresponding to some embodiments corresponding to operation 2116 is shown.

[0059] In operation 2118, the remaining space of the deep trenches is filled with a dielectric material. A high-k dielectric liner is formed within the deep trenches on top of the doped liner. Figure 16 A cross-sectional view corresponding to some embodiments corresponding to operation 2118 is shown.

[0060] In operation 2120, an anti-reflection layer and a composite grid are formed from the backside of the substrate. Figures 17 to 18 A cross-sectional view corresponding to some embodiments corresponding to operation 2120 is shown.

[0061] In operation 2122, a color filter and a microlens are formed above the backside of the semiconductor substrate. Figures 19 to 20 A cross-sectional view corresponding to some embodiments corresponding to operation 2122 is shown.

[0062] Accordingly, the present invention relates to an image sensor having a photodiode surrounded by a BDTI structure, and a related forming method. The BDTI structure includes a doped liner lining sidewall surfaces of a deep trench and a dielectric layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure serving as a doped well and an isolation structure, the implantation process from the front side of the substrate is simplified, thereby reducing the exposure resolution, the full well capacity of the photodiode, and high light spillover and crosstalk.

[0063] In some embodiments, the present invention relates to an image sensor. The image sensor includes an image sensing die having a front side and a back side opposite the front side. A plurality of pixel regions are disposed within the image sensing die and each includes a photodiode configured to convert radiation entering from the back side of the image sensor die into an electrical signal. The photodiode includes a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type. A BDTI structure is disposed between adjacent pixel regions and extends from the back side of the image sensor die to a position within the photodiode doping layer. The BDTI structure includes a doped liner having the second doping type and a dielectric fill layer, the doped liner lining sidewall surfaces of the dielectric fill layer.

[0064] In some embodiments, the image sensor further includes: a doped isolation well having the second doping type, disposed between the adjacent pixel regions and extending from the front side of the image sensing die to a position within the photodiode doping layer. In some embodiments, the doped isolation well is vertically aligned with the back side deep trench isolation structure. In some embodiments, the doped isolation well is separated from the back side deep trench isolation structure by the photodiode doping layer. In some embodiments, the doped isolation well and the back side deep trench isolation structure intersect within the photodiode doping layer. In some embodiments, a bottom of the back side deep trench isolation structure is disposed within a recessed top surface of the doped isolation well. In some embodiments, the back side deep trench isolation structure further includes a high-k dielectric liner disposed between the doped liner and the dielectric fill layer. In some embodiments, the image sensor further includes: a shallow trench isolation (STI) structure, disposed between the adjacent pixel regions from the front side of the image sensing die to a position within the photodiode doping layer; wherein, the shallow trench isolation structure and the back side deep trench isolation structure are vertically aligned. In some embodiments, the doped liner and the dielectric fill layer of the back side deep trench isolation structure extend laterally along the back side of the image sensing die. In some embodiments, a thickness of the doped liner of the back side deep trench isolation structure is less than 5 nm. In some embodiments, a surface concentration of the doped liner of the back side deep trench isolation structure is less than 1E19 / cm2 。In some embodiments, the uniformity of the doped liner of the backside deep trench isolation structure from top to bottom is greater than 90%. In some embodiments, the doping concentration of the doped liner of the backside deep trench isolation structure is in the range of 5E17 atoms / cm 3 to 1E19 atoms / cm 3 . In some embodiments, the image sensor further includes: a floating diffusion well disposed between adjacent pixel regions at a position from the front side of the image sensing die to within the photodiode doping layer; and a transfer gate disposed on the front side of the image sensing die at a lateral position between the photodiode and the floating diffusion well. In some embodiments, the image sensor further includes: a metallization stack disposed on the front side of the image sensing die and including a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers. In some embodiments, the image sensor further includes: a logic die bonded to the image sensing die from the front side of the image sensing die; wherein the logic die includes logic devices.

[0065] In some alternative embodiments, the present invention relates to a method of forming an image sensor. The method includes forming photodiodes for a plurality of pixel regions from the front side of an image sensing die. The photodiodes include a photodiode doping column having a first doping type surrounded by a photodiode doping layer having a second doping type different from the first doping type. A doped isolation well is formed from the front side of the image sensing die by injecting dopants into the photodiode doping layer through a plurality of implantation processes. A gate structure and a metallization stack are formed on the front side of the image sensing die. The metallization stack includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers. The image sensing die is bonded to a logic die from the front side of the image sensing die. The logic die includes logic devices. Deep trenches are formed between adjacent pixel regions by etching from the backside of the image sensing. A doped liner having the second doping type is formed as a lining on the sidewall surfaces of the deep trenches. A dielectric fill layer fills the interior space of the deep trenches to form a BDTI structure.

[0066] In some embodiments, forming the doped liner includes: forming a protective layer lining the deep trenches; performing a plasma doping process; removing the protective layer; and performing an annealing process. In some embodiments, the doped liner is formed by an epitaxial process at a temperature below 500 °C and a subsequent annealing process.

[0067] In yet other embodiments, the present invention relates to an integrated circuit. The integrated circuit includes an image sensor die having a plurality of pixel regions, each of the pixel regions including a photodiode configured to convert radiation entering the image sensor die from a backside into an electrical signal. The photodiode includes a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type. A BDTI structure is disposed between adjacent pixel regions and extends from the backside of the image sensor die to a position within the photodiode doping layer. The BDTI structure includes a doping pad having the second doping type and a dielectric fill layer. The doping pad lines a sidewall surface of a deep trench and the dielectric fill layer fills an interior space of the deep trench. A doping isolation well having the second doping type is disposed between adjacent pixel regions and extends from a front side of the image sensor die opposite the backside to a position within the photodiode doping layer. A metallization stack is disposed on the front side and includes a plurality of metal interconnect layers disposed within an interlayer dielectric layer. A logic die is bonded to the front side of the image sensor die. The logic die includes logic devices.

[0068] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. An image sensor, comprising: An image sensing die having a front side and a back side opposite to the front side; A plurality of pixel regions disposed within the image sensing die and each including a photodiode configured to convert radiation entering from the back side of the image sensor die into an electrical signal, the photodiode including a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type; And A backside deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending from the back side of the image sensor die to a position within the photodiode doping layer; A shallow trench isolation (STI) structure disposed between the adjacent pixel regions from the front side of the image sensing die to a position within the photodiode doping layer; A doped isolation well having the second doping type and surrounding the shallow trench isolation structure; A first deep well having the first doping type and disposed on a first surface of the photodiode doping layer adjacent to the back side of the image sensing die; A second deep well having the second doping type and disposed on the first deep well, wherein the backside deep trench isolation structure includes a doped liner and a dielectric fill layer having the second doping type, the doped liner lining a sidewall surface of the dielectric fill layer; Wherein the first deep well and the second deep well are located between the photodiode doping layer and the doped liner of the backside deep trench isolation structure.

2. The image sensor according to claim 1, wherein: The doped isolation well is disposed between the adjacent pixel regions and extends from the front side of the image sensing die to a position within the photodiode doping layer.

3. The image sensor according to claim 2, wherein, The doped isolation well is vertically aligned with the backside deep trench isolation structure.

4. The image sensor according to claim 2, wherein The doped isolation well is separated from the backside deep trench isolation structure by the photodiode doping layer.

5. The image sensor according to claim 2, wherein, The doped isolation well and the backside deep trench isolation structure intersect within the photodiode doping layer.

6. The image sensor according to claim 5, wherein, A bottom of the backside deep trench isolation structure is disposed within a recessed top surface of the doped isolation well.

7. The image sensor according to claim 1, wherein, The backside deep trench isolation structure further includes a high-k dielectric liner disposed between the doped liner and the dielectric fill layer.

8. The image sensor according to claim 1, Among them, The shallow trench isolation structure and the backside deep trench isolation structure are vertically aligned.

9. The image sensor according to claim 1, wherein, The doped liner and the dielectric fill layer of the backside deep trench isolation structure extend laterally along the back side of the image sensing die.

10. The image sensor according to claim 1, wherein, The thickness of the doped liner of the backside deep trench isolation structure is less than 5 nm.

11. The image sensor according to claim 1, wherein, The surface concentration of the doped liner of the dorsal deep trench isolation structure is less than 1E19 / cm 2 .

12. The image sensor according to claim 1, wherein, The uniformity of the doped liner of the backside deep trench isolation structure from top to bottom is greater than 90%.

13. The image sensor according to claim 1, wherein, The doping concentration of the doped pad of the dorsal deep trench isolation structure is in the range of 5E17 atoms / cm 3 to 1E19 atoms / cm 3 .

14. The image sensor according to claim 1, further comprising: A floating diffusion well disposed between the adjacent pixel regions from the front side of the image sensing die to a position within the photodiode doping layer; And A transfer gate disposed on the front side of the image sensor die at a lateral position between the photodiode and the floating diffusion well.

15. The image sensor according to claim 1, further comprising: A metallization stack disposed on the front side of the image sensor die and including a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers.

16. The image sensor according to claim 1, further comprising: A logic die bonded to the image sensor die from the front side of the image sensor die; Wherein, the logic die includes logic devices.

17. A method of forming an image sensor, comprising: Forming photodiodes for a plurality of pixel regions from the front side of an image sensor die, the photodiodes including photodiode doping columns having a first doping type, the photodiode doping columns being surrounded by a photodiode doping layer having a second doping type different from the first doping type; Forming a first deep well having the first doping type on a first side of the photodiode doping layer adjacent to the back side of the image sensor die; Forming a second deep well having the second doping type on the first deep well; Forming a shallow trench isolation structure from the front side of the image sensor die to a position within the photodiode doping layer; Forming a doped isolation well from the front side of the image sensor die by injecting dopants into the photodiode doping layer through a plurality of implantation processes, wherein the doped isolation well surrounds the shallow trench isolation structure; Forming a gate structure and a metallization stack on the front side of the image sensor die, wherein the metallization stack includes a plurality of metal interconnect layers disposed within one or more interlayer dielectric layers, Bonding the image sensor die to a logic die from the front side of the image sensor die, wherein the logic die includes logic devices; Forming deep trenches between adjacent pixel regions by etching from the back side of the image sensor; Forming a doped liner, wherein the second doping type lines the sidewall surfaces of the deep trenches, wherein the first deep well and the second deep well are located between the photodiode doping layer and the doped liner; and Forming a dielectric fill layer filling the interior space of the deep trenches to form a backside deep trench isolation (BDTI) structure.

18. The method according to claim 17, wherein, Forming the doped liner includes: Forming a protective layer lining the deep trenches; Performing a plasma doping process; Removing the protective layer; and Performing an annealing process.

19. The method according to claim 17, wherein, The doped liner is formed by an epitaxial process at a temperature below 500 °C and a subsequent annealing process.

20. An integrated circuit, comprising: An image sensor die having a plurality of pixel regions, each including a photodiode configured to convert radiation entering the image sensor die from the back side into an electrical signal, the photodiode including a photodiode doping column having a first doping type, the photodiode doping column being surrounded by a photodiode doping layer having a second doping type different from the first doping type; A backside deep trench isolation (BDTI) structure is disposed between adjacent pixel regions and extends from the backside of the image sensor die to a location within the photodiode doped layer, wherein the backside deep trench isolation structure includes a doped liner having the second doping type and a dielectric fill layer, and the doped liner lines the sidewall surfaces of the dielectric fill layer; A shallow trench isolation (STI) structure is disposed between the adjacent pixel regions from the front side of the image sensor die to a location within the photodiode doped layer; a doped isolation well having the second doping type is disposed between the adjacent pixel regions and extends from the front side of the image sensor die opposite to the backside to a location within the photodiode doped layer, and the doped isolation well surrounds the shallow trench isolation structure; A first deep well having the first doping type is disposed on a first surface of the photodiode doped layer adjacent to the backside of the image sensor die; A second deep well having the second doping type is disposed on the first deep well; A metallization stack is disposed on the front side and includes a plurality of metal interconnect layers disposed within an interlayer dielectric layer; and A logic die is bonded to the front side of the image sensor die, and the logic die includes logic devices, wherein the first deep well and the second deep well are located between the photodiode doped layer and the doped liner of the backside deep trench isolation structure.

Images