A Current Domain Read Successive Approximation Analog-to-Digital Converter Structure for RRAM

Abstract

The present invention discloses a current-domain reading successive approximation analog-to-digital converter structure for RRAM, including a first signal input terminal CLK, a second signal input terminal I cell , a third signal input terminal I ref , a current-mode comparator with input pairs of transistors, a successive approximation logic circuit for synchronous timing, a switch logic circuit, an overlap logic module, an i-bit register, and a first delay module. This structure can achieve high-precision data reading and has a relatively low cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of memristors, and relates to a current-domain read successive approximation analog-to-digital converter structure for RRAM. Background Art

[0002] In traditional computing architectures, storage has always been a limited and scarce resource. As the number of computing units increases, the bandwidth and size of the memory available to each unit will gradually decrease. With the advent of the era of artificial intelligence, this contradiction has become even more prominent. In many AI inference operations, more than 90% of the computing resources are consumed in the process of data transfer. The bandwidth from the inside to the outside of the chip and the on-chip cache space limit the computing efficiency. Therefore, in the industry and academia, more and more people believe that the integration of memory and computing is the future trend, which can well solve the "memory wall" problem. The memristor (RRAM) can directly perform full-precision matrix convolution operations (multiplication and addition operations) within the storage unit, enabling the integration of memory and computing and eliminating the "memory wall", avoiding the bottleneck of data transmission back and forth between the arithmetic logic unit (ALU) and the memory, thereby significantly reducing power consumption and improving computing efficiency. However, since the data reading of the memristor (RRAM) consumes a large amount of power, it brings more difficulties to the data processing of the memristor (RRAM).

[0003] In recent years, the main traditional implementation method for data reading of the memristor (RRAM) is to complete the current-voltage conversion through a transimpedance amplifier (TIA), and then convert the analog voltage value into a digital quantity through a voltage-mode analog-to-digital converter (VADC). However, this implementation method requires a transimpedance amplifier (TIA) with a large input swing for current-voltage conversion and a high-precision analog-to-digital converter (ADC) for reading. The introduction of a transimpedance amplifier (TIA) with a large input swing consumes a large amount of power, occupies a large amount of chip area, reduces linearity, and has a high cost. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above-mentioned disadvantages of the prior art, and provide a current-domain read successive approximation analog-to-digital converter structure for RRAM, which can achieve high-precision data reading and has a low cost.

[0005] To achieve the above object, the current-domain read successive approximation analog-to-digital converter structure for RRAM described in the present invention includes a first signal input terminal CLK, a second signal input terminal I cell , a third signal input terminal I ref , a current-mode comparator with input pairs of transistors, a successive approximation logic circuit with synchronous timing, a switch logic circuit, an overlapping logic module, an i-bit register, and a first delay module;

[0006] The first signal input terminal CLK is connected to one end of the first delay module, and the other end of the first delay module, the second signal input terminal I cell and the third signal input terminal I ref are connected to the input terminal of the current-mode comparator with an input pair of transistors. The first signal input terminal CLK is connected to the input terminal of the main inverter. The output terminal of the main inverter and the output terminal of the current-mode comparator with an input pair of transistors are connected to one end of the synchronous sequential successive approximation logic circuit. The other end of the synchronous sequential successive approximation logic circuit is respectively connected to one end of the switch logic circuit and one end of the i-bit register. The other end of the switch logic circuit is connected to one end of the overlapping logic module. The other end of the overlapping logic module is connected to the input terminal of the current-mode comparator with an input pair of transistors.

[0007] The current-mode comparator with an input pair of transistors includes a transmission gate switch, a first precharge transistor, a first latch pair of transistors, a second precharge transistor, a first drain switch, a second drain switch, a third drain switch, a fourth drain switch, a first MOS capacitor, a second MOS capacitor, a first buffer, and a second buffer;

[0008] The first signal input terminal is connected to the transmission gate switch, the gates of the first precharge transistor and the second precharge transistor. The second signal input terminal is connected to one end of the first drain switch. The third signal input terminal is connected to one end of the fourth drain switch. The gate of the first drain switch and the second drain switch are connected to one end of the first MOS capacitor. The gates of the third drain switch and the fourth drain switch are connected to one end of the second MOS capacitor. One end of the second drain switch and one end of the transmission gate switch are connected to the first buffer. The other end of the transmission gate switch is connected to the drain of the first precharge transistor, the drain of the first latch pair of transistors, and the gate of the second latch pair of transistors. The other end of the third drain switch is connected to one end of the transmission gate switch and the second buffer. The other end of the transmission gate switch is connected to the drain of the second precharge transistor, the drain of the second latch pair of transistors, and the gate of the first latch pair of transistors. The other ends of the first drain switch, the second drain switch, the third drain switch, and the fourth drain switch, the other end of the second MOS capacitor, and the other end of the first MOS capacitor are connected.

[0009] The current mirror ratios of the first drain switch are 2 0 : 2 1 : ……: 2 i .

[0010] The current mirror ratios of the second drain switch are 2 i : 2 i-1 : ……: 2 0 .

[0011] The current mirror ratios of the third drain switch and the fourth drain switch are 2 0 : 2 1 : ……: 2 i : 2 i .

[0012] The synchronous sequential successive approximation logic circuit includes i + 1 first D flip - flops, i second D flip - flops, a first sub - inverter, a second sub - inverter, an AND gate, and an AND gate;

[0013] The Q pin of the previous first D flip - flop is connected to the D pin of the next first D flip - flop. The D pin of the first flip - flop is connected to the power supply VDD. The input terminal of the first sub - inverter, the CLK pins of each first D flip - flop are connected to the output terminal of the main inverter. The output terminal of the first sub - inverter and the Q pin of the first first D flip - flop are connected to the input terminals of the first AND gate. The output terminal of the first AND gate is connected to the switch logic circuit. The Set pins of each first flip - flop and the Set pins of each second flip - flop are connected to the Q pin of the i - th first flip - flop. The Q pin of the (k + 1) - th first flip - flop is connected to the CLK pin of the k - th second flip - flop. The D pins of each second flip - flop are connected to the output terminal of the current - mode comparator with input pairs. The Q pins of each second flip - flop are connected to the switch logic circuit and an i - bit register. The input terminal of the second sub - inverter is connected to the CLK pin of the (i - 1) - th first flip - flop. The input terminals of the second AND gate are connected to the output terminal of the second sub - inverter and the CLK pin of the i - th second flip - flop. The output terminal of the second AND gate is connected to the i - bit register.

[0014] The present invention has the following beneficial effects:

[0015] When the current - domain reading successive approximation analog - to - digital converter structure for RRAM of the present invention is in specific operation, it cancels the conversion of the current signal in the intermediate stage into a voltage signal (I - V), and at the same time cancels the sample - and - hold circuit (SHA), reducing the hardware overhead, improving the conversion speed, and reducing the power consumption. The current - mode comparator with input pairs generates a control signal through overlapping logic to only switch the switches to complete the successive approximation of the reference current, and avoids the long settling time of the current from zero to the target value, greatly increasing the speed of the analog - to - digital converter (ADC). The synchronous sequential successive approximation logic circuit enables each clock signal of the circuit to be directly controlled externally, having good process - voltage - temperature (PVT) stability. The entire circuit is controlled by an enable signal (EN), which can solve the problem of uncertain circuit node voltages during circuit startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural schematic diagram of the present invention;

[0017] Figure 2 is the main topology diagram of the current-mode comparator 1 with input pair transistors;

[0018] Figure 3 is the topology diagram of the set / reset latch of the current-mode comparator 1 with input pair transistors;

[0019] Figure 4 is the topology diagram of the successive approximation logic circuit 2 for synchronous timing;

[0020] Figure 5 is the topology diagram of the switch logic circuit 3 and the overlap logic module 4;

[0021] Figure 6 is the topology diagram of the switch logic circuit 3.

[0022] Among them, 1 is the current-mode comparator with input pair transistors, 2 is the successive approximation logic circuit for synchronous timing, 3 is the switch logic circuit, 4 is the overlap logic module, 5 is the i-bit register, and 6 is the delay module. Detailed implementation manners

[0023] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the scope of the present invention disclosure. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts disclosed in the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0024] The structural schematic diagrams according to the disclosed embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0025] Refer to Figure 1 , the current-domain read successive approximation analog-to-digital converter structure for RRAM described in the present invention includes a first signal input terminal CLK, a second signal input terminal I cell , a third signal input terminal I ref, a current-mode comparator with input pairs 1, a successive approximation logic circuit with synchronous timing 2, a switching logic circuit 3, an overlapping logic module 4, an i-bit register 5, and a first delay module 6. Among them, the first signal input terminal CLK is connected to one end of the first delay module 6, and the other end of the first delay module 6, the second signal input terminal I cell and the third signal input terminal I ref are connected to the input terminal of the current-mode comparator 1 with input pairs. The first signal input terminal CLK is connected to the input terminal of the main inverter. The output terminal of the main inverter and the output terminal of the current-mode comparator 1 with input pairs are connected to one end of the successive approximation logic circuit 2 with synchronous timing. The other end of the successive approximation logic circuit 2 with synchronous timing is respectively connected to one end of the switching logic circuit 3 and one end of the i-bit register 5. The other end of the switching logic circuit 3 is connected to one end of the overlapping logic module 4. The other end of the overlapping logic module 4 is connected to the input terminal of the current-mode comparator 1 with input pairs.

[0026] To solve the speed and accuracy problems caused by the current mirror switching of the current-mode SAR ADC, refer to Figure 2 , the current-mode comparator 1 with input pairs includes a transmission gate switch, a first pre-charge transistor M P2 , a first latch pair transistor M P0 , a second pre-charge transistor M P3 , a first drain switch M N2 —M Ni+1 , a second drain switch M Ni+2 —M N2i+1 , a third drain switch M N2i+2 —M N3i+2 , a fourth drain switch M N3i+3 , a first MOS capacitor C0, a second MOS capacitor C1, a first buffer B1, and a second buffer B2;

[0027] The first signal input terminal CLK is connected to the transmission gate switch, the gates of the first pre-charge transistor M P2 and the second pre-charge transistor M P3 . The second signal input terminal I cell is connected to one end of the first drain switch M N2 —M Ni+1 . The third signal input terminal I ref is connected to one end of the fourth drain switch M N3i+3 . The gates of the first drain switch M N2 —M Ni+1 and the second drain switch M Ni+2 —M N2i+1 are connected to one end of the first MOS capacitor C0. The third drain switch M N2i+2 —MN3i+2 The gate and the fourth drain switch M N3i+3 The gate is connected to one end of the second MOS capacitor C1, and the second drain switch M Ni+2 —M N2i+1 One end and one end of the transmission gate switch are connected to the first buffer B1, and the other end of the transmission gate switch is connected to the drain of the first pre-charge transistor M P2 The drain of, the first latch pair transistor M P0 The drain of and the second latch pair transistor M P1 The gate is connected, and the third drain switch M N2i+2 —M N3i+2 The other end is connected to one end of the transmission gate switch and the second buffer B2, and the other end of the transmission gate switch is connected to the drain of the second pre-charge transistor M P3 The drain of, the second latch pair transistor M P1 The drain of and the first latch pair transistor M P0 The gate is connected, and the first drain switch M N2 —M Ni+1 The other end, the second drain switch M Ni+2 —M N2i+1 The other end, the third drain switch M N2i+2 —M N3i+2 The other end and the fourth drain switch M N3i+3 The other end, the other end of the second MOS capacitor C1 and the other end of the first MOS capacitor C0 are connected.

[0028] Among them, the current mirror ratios of the first drain switch M N2 —M Ni+1 are respectively 2 0 : 2 1 : ……: 2 i The current mirror ratios of the second drain switch M Ni+2 —M N2i+1 are respectively 2 i : 2 i-1 : ……: 2 0 The current mirror ratios of the third drain switch M N2i+2 —M N3i+2 and the fourth drain switch M N3i+3 are respectively 2 0 : 2 1 : ……: 2 i : 2 i .

[0029] Reference Figure 3, in order to latch the output voltages V1 and V2 of the current-mode comparator 1 with input pairs of transistors, an SR latch is added. Among them, the output terminals of the first buffer B1 and the second buffer B2 are connected to the input terminal of the SR latch. The output terminal of the SR latch serves as the output terminal COMP of the current-mode comparator 1 with input pairs of transistors and is connected to the successive approximation logic circuit 2 of the synchronous timing. The specific structure of the SR latch is as Figure 3 shown.

[0030] Reference Figure 4 , in order to accurately generate clock overlap, a design of a synchronous logic clock circuit is adopted. The successive approximation logic circuit 2 of the synchronous timing includes i + 1 first D flip-flops, i second D flip-flops, a first sub-inverter I 01 , a second sub-inverter I 11 , an AND gate A0 and an AND gate A1;

[0031] The Q pin of the previous first D flip-flop is connected to the D pin of the next first D flip-flop. The D pin of the first flip-flop is connected to the power supply VDD. The input terminal of the first sub-inverter I 01 , the CLK pins of each first D flip-flop are connected to the output terminal of the main inverter. The output terminal of the first sub-inverter I 01 and the Q pin of the first first D flip-flop are connected to the input terminals of the first AND gate A0. The output terminal of the first AND gate A0 is connected to the switch logic circuit 3. The Set pins of each first flip-flop and the Set pins of each second flip-flop are connected to the Q pin of the i-th first flip-flop. The Q pin of the (k + 1)-th first flip-flop is connected to the CLK pin of the k-th second flip-flop. The D pins of each second flip-flop are connected to the output terminal of the current-mode comparator 1 with input pairs of transistors. The Q pins of each second flip-flop are connected to the switch logic circuit 3 and the i-bit register 5. The input terminal of the second sub-inverter I 11 is connected to the CLK pin of the (i - 1)-th first flip-flop. The input terminals of the second AND gate A1 are connected to the output terminal of the second sub-inverter I 11 and the CLK pin of the i-th second flip-flop. The output terminal of the second AND gate A1 is connected to the i-bit register 5.

[0032] In order to generate the switching signal of the current mirror array, the present invention performs logical combination on the output signals of the successive approximation logic circuit 2 of the synchronous timing. The specific schematic diagram is as Figure 5 shown. The switch logic circuit 3 and the overlap logic module 4 include inverters I1, I2,..., I 2i , S<0> switch logic circuit K1, S<1> switch logic circuit K2,..., S Switch logic circuit K i , the 2i - 1 output signals Sample, CSW0, CSW1, ……, CSWi - 2, RSW0, RSW1, ……, RSWi - 2 of the synchronous sequential successive approximation logic circuit 2 are sequentially connected to the input terminals of the inverters I1, I2, ……, I 2i , the two output signals CSW0 and RSW0 of the synchronous sequential successive approximation logic circuit 2, the output terminals of the inverters I1, I2, ……, I i+1 are connected to one end of the S<0> switch logic circuit K1, the other end of the S<0> switch logic circuit K1 is connected to the current - type comparator 1 with input pair transistors, the three output signals CSWj - 1, CSWj and RSWj of the synchronous sequential successive approximation logic circuit 2, the inverters I1, I j+1 , I j+2 , I i+j+1 's output terminals are connected to S <j>Switch logic circuit K j+1 is connected to one end, S <j>Switch logic circuit K j+1 The other end is connected to the current-mode comparator 1 with input pair transistors. The output signals CSWi-2, inverters I1, I of the successive approximation logic circuit 2 with synchronous timing i The output end is connected to S Switch logic circuit K i is connected to one end, S Switch logic circuit K i The other end is connected to the current-mode comparator 1 with input pair transistors.

[0033] To generate the overlap of the current mirror control signal, refer to Figure 6 The S<0> switch logic circuit K1 includes a first NAND gate W1, a second NAND gate W2, a third NAND gate W3, a fourth NAND gate W4, a second delay module L0, and an OR gate O1; the output terminals nSample and nCSW0 of the inverter are connected to one end of the first NAND gate W1, the output terminals nSample of the inverter, and two output signals CSW0 and RSW0 of the synchronous sequential successive approximation logic circuit 2 are connected to one end of the second NAND gate W2, the output terminals nSample, nRSW0 of the inverter, and an output signal CSW0 of the synchronous sequential successive approximation logic circuit 2 are connected to one end of the third NAND gate W3, the other end of the third NAND gate W3 is connected to one end of the OR gate O1, the output terminals nSample of the inverter, the other end of the first NAND gate W1, and the other end of the second NAND gate W2 are connected to one end of the fourth NAND gate W4, the other end of the fourth NAND gate W4 is connected to one end of the second delay module L0 and the input terminal of the OR gate O1, the other end of the second delay module L0 is connected to the other end of the third NAND gate W3 and then connected to the input terminal of the OR gate O1, and the output terminal of the OR gate O1 is connected to the current-mode comparator 1 with input pair transistors.

[0034] The specific working process of the present invention is as follows:

[0035] 1) Comparison stage:

[0036] The current-mode comparator 1 with input pair transistors completes the comparison process when the clock signal is high according to the magnitudes of the input current signal and the reference current signal.

[0037] 2) Successive approximation logic generation stage:

[0038] The synchronous sequential successive approximation logic circuit 2 generates the combined signals required by the switch logic circuit 3 and the output digital signal of the analog-to-digital converter according to the input clock and the comparison result of the current-mode comparator 1 with input pair transistors.

[0039] 3) Control signal generation stage:

[0040] The switch logic circuit 3 generates the switch signals required by the current mirror array according to the two groups of output signals generated by the synchronous sequential successive approximation logic circuit 2, and generates clock overlap through the overlap logic module 4. This group of signals controls the switches at the drains of the current mirrors to complete the switching of the current mirror array, and finally achieves the successive approximation process of the reference current signal to the input current signal.

[0041] The present invention is designed using the standard 0.18μm CMOS process, without the need for special processes and equipment. It cancels the conversion of the current signal in the intermediate stage into a voltage signal (I-V), and at the same time cancels the sample and hold circuit (SHA), reducing the hardware overhead, while improving the conversion speed and reducing the power consumption. The current-mode comparator 1 with input pair transistors generates control signals through overlapping logic to only switch the switches to complete the successive approximation of the reference current, and avoids the overly long establishment time of the current from zero to the target value, greatly increasing the speed of the analog-to-digital converter (ADC). The design of the synchronous sequential successive approximation logic circuit 2 enables each clock signal of the circuit to be directly controlled externally, having good process-voltage-temperature (PVT) stability. < / j> < / j>

Claims

1. A current-domain read successive approximation analog-to-digital converter structure for RRAM, characterized in that, including a first signal input terminal CLK and a second signal input terminal I cell , a third signal input terminal I ref , a current-mode comparator 1 with an input pair of transistors, a successive approximation logic circuit 2 with synchronous timing, a switching logic circuit 3, an overlap logic module 4, an a-bit register 5, and a first delay module 6; The first signal input terminal CLK is connected to one end of the first delay module 6, and the other end of the first delay module 6, the second signal input terminal I cell and the third signal input terminal I ref are connected to the input terminal of the current-mode comparator 1 with input pair transistors. The first signal input terminal CLK is connected to the input terminal of the main inverter. The output terminal of the main inverter and the output terminal of the current-mode comparator 1 with input pair transistors are connected to one end of the synchronous sequential successive approximation logic circuit 2. The other end of the synchronous sequential successive approximation logic circuit 2 is respectively connected to one end of the switch logic circuit 3 and one end of the a-bit register 5. The other end of the switch logic circuit 3 is connected to one end of the overlap logic module 4. The other end of the overlap logic module 4 is connected to the input terminal of the current-mode comparator 1 with input pair transistors; The current-mode comparator 1 with input differential pairs includes a transmission gate switch, a first pre-charge transistor M P2 , a first latch differential pair M P0 , a second pre-charge transistor M P3 , a first drain switch M N2 —M Ni+1 , a second drain switch M Ni+2 —M N2i+1 , a third drain switch M N2i+2 —M N3i+2 , a fourth drain switch M N3i+3 , a first MOS capacitor C0, a second MOS capacitor C1, a first buffer B1, and a second buffer B2; The first signal input terminal CLK is connected to the gate of the transmission gate switch and the first pre-charge transistor M P2 and the gate of the second pre-charge transistor M P3 The second signal input terminal I cell is connected to one end of the first drain switch M N2 —M Ni+1 The third signal input terminal I ref is connected to one end of the fourth drain switch M N3i+3 The gate of the first drain switch M N2 —M Ni+1 and the gate of the second drain switch M Ni+2 —M N2i+1 are connected to one end of the first MOS capacitor C0. The gate of the third drain switch M N2i+2 —M N3i+2 and the gate of the fourth drain switch M N3i+3 are connected to one end of the second MOS capacitor C1. One end of the second drain switch M Ni+2 —M N2i+1 and one end of the transmission gate switch are connected to the first buffer B1. The other end of the transmission gate switch is connected to the drain of the first pre-charge transistor M P2 the drain of the first latch pair transistor M P0 and the gate of the second latch pair transistor M P1 The other end of the third drain switch M N2i+2 —M N3i+2 is connected to one end of the transmission gate switch and the second buffer B2. The other end of the transmission gate switch is connected to the drain of the second pre-charge transistor M P3 the drain of the second latch pair transistor M P1 and the gate of the first latch pair transistor M P0 The other end of the first drain switch M N2 —M Ni+1 the other end of the second drain switch M Ni+2 —M N2i+1 the other end of the third drain switch M N2i+2 —M N3i+2 the other end of the fourth drain switch M N3i+3 the other end of the second MOS capacitor C1 and the other end of the first MOS capacitor C0 are connected together.

2. The current-domain read successive approximation analog-to-digital converter structure for RRAM according to claim 1, wherein The third drain switch M N2i+2 —M N3i+2 and the current mirror ratios of the fourth drain switch M N3i+3 are 2 0 : 2 1 : ……: 2 i : 2 i .

3. The current-domain read successive approximation analog-to-digital converter structure for RRAM according to claim 1, characterized in that, The successive approximation logic circuit 2 with synchronous timing includes c + 1 first D flip-flops, c second D flip-flops, a first sub-inverter I 01 , a second sub-inverter I 11 , an AND gate A0 and an AND gate A1; The Q pin of the previous first D flip-flop is connected to the D pin of the next first D flip-flop. The D pin of the first flip-flop is connected to the power supply VDD. The input terminal of the first sub-inverter I 01 and the CLK pins of each first D flip-flop are connected to the output terminal of the main inverter. The output terminal of the first sub-inverter I 01 and the Q pin of the first first D flip-flop are connected to the input terminals of the first AND gate A0. The output terminal of the first AND gate A0 is connected to the switch logic circuit 3. The Set pins of each first flip-flop and the Set pins of each second flip-flop are connected to the Q pin of the c-th first flip-flop. The Q pin of the (k + 1)-th first flip-flop is connected to the CLK pin of the k-th second flip-flop. The D pins of each second flip-flop are connected to the output terminal of the current-mode comparator 1 with input pairs of transistors. The Q pins of each second flip-flop are connected to the switch logic circuit 3 and the a-bit register 5. The input terminal of the second sub-inverter I 11 is connected to the CLK pin of the (c - 1)-th first flip-flop. The input terminals of the second AND gate A1 are connected to the output terminal of the second sub-inverter I 11 and the CLK pin of the c-th second flip-flop. The output terminal of the second AND gate A1 is connected to the a-bit register 5.

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