Memory core power-up with reduced peak current

Abstract

A memory has a plurality of cores, which are powered up according to a power-up sequence from a first core to a final core. When a core power supply voltage of a current core is powered up according to the power-up sequence, in response to the core power supply voltage exceeding a threshold voltage of a control transistor in a subsequent core, power-up of a subsequent core in the power-up sequence is triggered.

Description

[0001] Claiming priority under 35 U.S.C. § 119

[0002] This patent application claims priority to non-provisional application No. 16 / 430,137, filed on June 3, 2019, entitled “MEMORY CORE POWER-UP WITH PEAK CURRENT REDUCTION,” which application has been assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The present application relates to a memory, and more particularly, to a memory with reduced peak current during power-on. Background Art

[0004] Each bit cell in a static random access memory (SRAM) is an active latch where the bit is passed through a cross-coupled inverter pair. In contrast to the passive cells in dynamic random access memory (DRAM), SRAM bit cells are powered so that the bit result can be driven out during a read operation. Therefore, due to the active nature of the bit cells, SRAM is significantly faster than DRAM. However, powering up the bit cells in SRAM requires a large amount of charge. The amount of charge required at power up varies with the number of bit cells of a particular memory. The charge is supplied by the core power rail that carries the core supply voltage of the bit cells.

[0005] Prior to power-up, the core supply is isolated from the bit cells by one or more power switching transistors. All power switching transistors are typically turned on at power-up. During power-up, a pair of cross-coupled inverters in each bit cell must resolve to a stable latched state. In this latched state, the output node of one cross-coupled inverter is driven to the high level of the core supply voltage, while the output nodes of the remaining cross-coupled inverters remain discharged. The charging of all output nodes results in a significant peak input current to the memory core during power-up, which can damage the memory.

[0006] To reduce the peak input current, power-ups are typically sequenced by memory bank. After the first memory bank is powered up, then the second memory bank is powered up, and so on, until all memory banks are powered up. The sequencing of the different memory banks is controlled by delay logic with fixed resistor capacitor (RC) delays. However, this fixed delay is problematic because the amount of time and peak current for powering up a given memory bank depends on the process, voltage, and temperature (PTV) corners. Since all process corners must be met, the result is that the power-up time is long. In addition, as the size of the memory bank changes, the delay must also change, which makes it problematic to port the design from one process node to another.

[0007] Thus, there is a need in the art for a memory having reduced peak input current and reduced latency during power up. Summary of the invention

[0008] A memory is disclosed, comprising an external power rail; a first core power rail configured to provide power to a first plurality of bit cells; a first power switch transistor coupled between the first core power rail and the external power rail; a second core power rail configured to provide power to a second plurality of bit cells; a second power switch transistor coupled between the second core power rail and the external power rail; and a control transistor having a gate connected to the first core power rail, wherein the second power switch transistor is configured to be turned on in response to turning on the control transistor.

[0009] In addition, a power-up method of a memory is disclosed, comprising the following actions: turning on a first power switch transistor to connect a first core power rail for a bit cell of a first core to an external power rail to charge the first core power rail from ground to a core power voltage, wherein the core power voltage is greater than a threshold voltage of a control transistor; turning on the control transistor in response to the first core power rail being charged above the threshold voltage; and turning on a second power switch transistor in response to the turning on of the control transistor to connect a second core power rail for a bit cell of a second core to the external power rail to charge the second core power rail from ground to the core power voltage.

[0010] Finally, a memory is disclosed, comprising a plurality of bit cells arranged into a plurality of cores, wherein the cores are arranged according to a power-on order; a plurality of power rails corresponding to the plurality of cores, each power rail being configured to power a corresponding core; and a plurality of control transistors corresponding to the plurality of cores, wherein each control transistor is configured to control powering of a core of the control transistor, and wherein a gate of the control transistor in each consecutive core in the power-on order is connected to the power rail of a previous core in the power-on order.

[0011] These and other advantages may be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a circuit diagram of a memory core for a memory vault in which bit cells are powered by a core power rail independent of other core power rails according to one aspect of the present disclosure.

[0013] Figure 2 Illustrated is a zeroth memory core and a first memory core each having independent core power rails configured for continuous power-up according to one aspect of the present disclosure.

[0014] Figure 3 An example embodiment is illustrated in which each memory bank includes memory configured for multiple cores powered up continuously according to one aspect of the present disclosure.

[0015] Figure 4is a flow chart of a method for continuously powering up a core of a memory according to one aspect of the present disclosure.

[0016] Figure 5 Some example systems incorporating memory configured for continuous power-up of the memory core according to one aspect of the present disclosure are shown.

[0017] Embodiments of the present disclosure and their advantages may be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures of the drawings. DETAILED DESCRIPTION

[0018] In order to provide reduced peak input current without excessive delay during memory power-up, the power supply of the bit cell is isolated by its input / output (IO). With respect to IO, traditionally, the bit cells are arranged in rows and columns. Each row is addressed by a corresponding word line, and each column is addressed by a corresponding bit line pair. During a read operation, the sense amplifier senses the voltage difference generated across the bit line pair of the addressed column. The sense amplifier typically has a wider pitch than the bit line pitch, so several columns are typically multiplexed to a single sense amplifier through a column multiplexer. The read output data latch (IO) latches the bit decision from the sense amplifier of the selected column. Therefore, power isolation applies to all bit cells in the column multiplexed to the read output data latch.

[0019] The rows and columns of memory are typically arranged into sub-arrays designated as memory banks. Each memory bank has its own set of read output data latches, arranged from the zeroth read output data latch to the last read output data latch. The number of read output data latches of a memory bank depends on the word length of the memory bank. For example, if the word length is 64 bits wide, the memory bank may include 64 read output data latches. The number of independent core power rails of the memory bank corresponds one-to-one to the number of read output data latches. In the previous example of 64 read output data latches, the memory bank may have 64 different core power rails. These rails are powered on sequentially. Each core power rail supplies core power to the bit cells in the column that are multiplexed onto the corresponding read output data latch.

[0020] Figure 1 An example memory core 100 is shown for the i-th read output data latch 130. <ith>The name refers to its bit position within the word formed by the set of read output data latches of the corresponding memory. For example, the number of bits in the word can be from the zeroth bit to the (M-1)th bit, where M is a positive integer of the word width. As used herein, the term "core" refers to the bit cells addressed by the columns multiplexed onto a single read output data latch. In core 100, column multiplexing is N:1 multiplexing through column multiplexer 125. Therefore, there are N columns in core 100, ranging from the zeroth column (column 0) to the (N-1)th column (column N). The number of bit cells in a single column depends on the number of rows of the memory bank. For example, if the memory bank including core 100 has thirty-two rows corresponding to thirty-two word lines, a single column may have thirty-two bit cells. Therefore, in column 0, there is a first bit cell 105 corresponding to the first row. Each remaining row may also have a corresponding bit cell. For clarity of explanation, column 0 only shows bit cell 105 and the final bit cell 110 of the last row. Similarly, the (N-1)th column includes a plurality of bit cells ranging from the first bit cell 115 of the first row to the final bit cell 120 of the last row. Therefore, the total number of bit cells of a core such as core 100 depends not only on the number of rows of the core's memory bank, but also on the column multiplexing. In embodiments without column multiplexing, the number of bit cells per core may be equal to the number of rows. If the column multiplexing is 2:1, the number of bit cells per core may be twice the number of rows. Similarly, if the column multiplexing is 4:1, the number of bit cells per core may be four times the number of rows. In general, the number of bit cells per core is the product of the number of rows of the memory bank and the column multiplexing order. Each bit cell in core 100 is powered by the same core power rail VDDCore Supply. The core power rail <ith>The names correspond to the read output data latches 130. <ith>name.

[0021] In view of the concept of memory core power rails defined as described above, a memory is disclosed herein that continuously powers up various cores in each memory bank. For example, assume that the memory has a pair of memory banks. The cores in the first of the memory banks are powered up continuously. Once the sequence reaches the final core of the cores in the first memory bank, the sequence continues for the remaining cores in the second memory bank. If the memory has additional memory banks, the sequence of cores may extend across these additional memory banks. Then, the power-up sequence may proceed across the cores in one memory bank to another memory bank until all cores in all memory banks are powered up.

[0022] The order of crossing between cores is not based on any strict fixed delay, but rather utilizes the ramp-up of the core power supply from ground to its final charge state. Each core power rail is coupled to an external power rail through a corresponding power switch transistor. When the power switch transistor of the core is turned on, the core power rail is charged to the core power supply voltage supplied by the external power rail. Therefore, when the power switch transistor is turned on, the core power supply voltage will be charged from ground to its fully charged state. By using this charging of the core power supply voltage, the memory architecture disclosed herein advantageously utilizes the core power supply voltage to be charged from ground to its fully charged state to control when the consecutive cores begin to charge. As used herein, the term "external power rail" refers to any suitable power rail isolated from the core power rail by a corresponding power switch transistor. In general, an integrated circuit including a memory as disclosed herein has various power rails for distributing the power supply voltage to classified components within the integrated circuit. The external power rail may be a global power rail that provides the core power supply voltage to other components other than the memory. Alternatively, the external power rail may be dedicated to the distribution of the core power supply voltage to the memory.

[0023] The cores in the memory bank are arranged from the first core to the final core. For the cores in this order, the core power supply from the previous core controls whether the power switch transistor is turned on to power the core. In one embodiment, the power switch transistor of the core can be an n-type metal oxide semiconductor (NMOS) transistor. In this embodiment, once the core power supply voltage from the previous core reaches the threshold voltage of the power switch transistor, the core power supply voltage from the previous core begins to turn on the power switch transistor of the current core. Although this NMOS embodiment is advantageous for powering up the core, it is noted that the p-type metal oxide switch (PMOS) power switch transistor will pass a higher power supply voltage compared to the NMOS power switch transistor. Therefore, the following discussion will assume that the power switch transistor of each core will be a PMOS power switch transistor without loss of generality.

[0024] With respect to the power-up order of cores within a bank, the "current core" refers to the core that is currently being powered up in the order. As the order progresses, the current core becomes the previous core of another current core. However, the first core in the first bank being powered up does not have a previous core. A control signal controls whether the core power of the first core is powered up. For each remaining core in the power-up order, the core power control voltage of the previous core starts to power up. For example, for the second core in the power-up order, the power supply voltage of the first core controls the charging of the power supply voltage of the second core. For the third core in the power-up order, the power supply voltage of the second core controls the charging of the power supply voltage of the third core, and so on throughout the power-up order.

[0025] Since the power switch transistor of each core is a PMOS power switch transistor, the core power supply voltage from the previous core drives the gate of the NMOS control transistor in the current core. When the core power supply voltage from the previous core rises above the threshold voltage of the control transistor in the current core, the control transistor in the current core is turned on to ground the gate of the PMOS power switch transistor of the current core. This grounding of the gate of the power switch transistor turns on the power switch transistor so that the power supply voltage of the current core begins to charge. In turn, the current core becomes the previous core of the new current core in the power-on sequence. The power-on sequence can be considered to correspond to an integer order: first core, second core, third core, fourth core, etc. Therefore, charging the core power supply voltage of the i-th core to the threshold voltage determines when the core power supply voltage of the (i+1)-th core begins to charge, where i is a positive integer in the integer order.

[0026] Figure 2 A memory vault 200 is shown including multiple cores powered up according to an embodiment of the power-up sequence disclosed herein. For clarity of illustration, only the cores of the memory vault 200 are shown. <0> and core <1> Each core includes Figure 1 For example, the core 100 may include a plurality of bit cells (not shown) discussed above. <0> The bit cells in the column addressed by the zeroth read output data latch are included. These bit cells are <0> The zeroth read output data latch and other addressing components such as the word line decoder and column address decoder are powered by the core <0> During a write operation, the GIO circuit 215 receives the zeroth bit Din<0 of the input word to be written to the memory bank 200. According to the addressing, the zeroth bit is then written to the core <0> During a read operation, the GIO circuit 215 outputs the zeroth bit Dout of the output word being read from the memory bank 200. <0> Similarly, the core <1> Included are all bit cells corresponding to the first read output data latch as represented by GIO circuit 210. GIO circuit 210 receives the first bit of an input word and outputs the first bit of an output word.

[0027] To initiate power up of the memory bank 200, the controller 230 asserts a control signal that drives the core <0> The gate of the NMOS control transistor M1 is connected to the power-on and sleep modes. To coordinate the power-on and sleep modes, the drain of the control transistor M1 is connected to the source of the NMOS transistor M2, which has its drain connected to the drain of the PMOS transistor P1. The source of the transistor P1 is connected to the drain of another PMOS transistor P2, which has its source connected to the external power rail 235 supplying the external power supply voltage vddehx. In an alternative embodiment, the transistors P1 and P2 can be replaced by a single PMOS transistor. The active low level sleep signal (Slp_core_n) drives the gates of the transistors M2, P1 and P2.

[0028] The source of control transistor M1 is connected to ground so that when the control signal is asserted, the source of transistor M2 is grounded. Therefore, transistors P2, P1 and M1 act as inverters to invert the sleep signal while the control signal is asserted. During normal operation, the sleep signal is asserted to a high level of the external power supply voltage vddhx. Therefore, the inverter formed by transistors M1, P2 and P1 inverts this high value of the sleep signal so that the drains of transistors P1 and M2 are grounded. These drain nodes are connected to the gate of a PMOS power switch transistor P3, which has its source connected to the external power rail 235 and its drain connected to the core <0> Power rail 220. Before power is applied, the core <0> The voltage of power rail 220 is grounded. However, in response to the turning on of power switch transistor P3, the core <0> Power rail 220 charges up to the core supply voltage vddehx carried on external power rail 235 .

[0029] To make power-up continuous from one core to another, the core <0> Power rail 220 connects to the core <1> The gate of the NMOS control transistor M3. <1> In the embodiment, the first control transistor M3, the NMOS transistor M4, the PMOS transistor P4, the PMOS transistor P5 and the PMOS first power switch transistor P6 are similar to those in the core. <0> In this regard, when the control transistor M3 responds to the core <0> When the power rail 220 is charged above the threshold voltage of the control transistor M3 and turned on, the transistors P5, P4 and the transistor M4 act as an inverter. <0> As discussed, in an alternative embodiment, transistors P5 and P4 may be replaced by a single PMOS transistor. The active low sleep signal Slp_core_n drives the gates of transistors M4, P4, and P5. As control transistor M3 discharges the source of transistor M4, transistors M4, P4, and P5 act as inverters to invert the charge state of the sleep signal during normal operation, thereby grounding the gate of power switch transistor P6. Thus, when the core <0> When the power rail 220 is charged above the threshold voltage of the control transistor M3, the power switch transistor P6 will begin to turn on. The source of the power switch transistor P6 is tied to the external power rail 235 and its drain is connected to the core <1> Power rail 225. Core <1> Power rail 225 to the core <1> All bit cells in the core supply voltage are supplied.

[0030] Then, the core <1> The power rail 225 will charge from ground to the core supply voltage vddehx. As it does so, it will pass through the core <2> The threshold voltage of the control transistor in (not shown) causes the power rail of the second core to start charging toward the power supply voltage vddehx. In turn, the power-up of the second core triggers the power-up of the third core, and so on.

[0031] Figure 3 This sequential power up of the cores of memory 300 with bank 0 and bank 1 is also illustrated. In memory 300, each memory bank has 64 cores ranging from core <0> To the core <63> . Core in library 0 <0> Similar to the core in memory bank 200 <0> , because it is this core that responds to the assertion of the control signal. <0> When the core supply voltage rises above the threshold voltage, it triggers the core in bank 0 <1> In turn, successive power-ups of the cores continue until the final core in bank 0 <63> The power rails in these 63 cores are tied to the cores in bank 1 <0> Therefore, the successive power-ups of the cores in bank 0 will trigger the successive power-ups of the cores in bank 1 until the final core in bank 1 is powered up. <63> Fully charged.

[0032] Although it is convenient to match the power-up order of the cores to the bit order of the data output words of each bank, it should be appreciated that the order is arbitrary and may vary in alternative embodiments. In addition, the order need not be from core to core, but may be from one core group to another core group. For example, the power rails for consecutive groups of two cores may be tied together so that the core pairs are powered up together. Once the core supply voltage of the first core pair reaches the threshold voltage of the second core pair, the power-up of the second core pair is triggered, and so on.

[0033] Now, refer to Figure 4 An example power-up method is discussed in the flowchart of FIG. The method includes an action 400 of turning on a first power switch transistor to connect a first power rail of a first memory core to an external power rail to charge the first power rail from ground to a core power voltage, wherein the core power voltage is greater than a threshold voltage of a first control transistor. The core of the memory bank 200 <0> The turning on of the power switch transistor P3 in is an example of action 400. In addition, the method includes action 405: in response to the first power rail charging above the threshold voltage, turning on the first control transistor. The core of the memory bank 200 <1> The turning on of the control transistor M3 in is an example of action 405. Finally, the method includes action 410, which is responsive to the turning on of the first control transistor and includes: turning on the second power switch transistor to connect the second power rail of the second memory core to the external power rail to charge the second power rail from ground to the core supply voltage. <1> Charging of power rail 225 is an example of action 410 .

[0034] A continuously powered memory having a core as disclosed herein can be incorporated into a wide variety of electronic systems. Figure 5 As shown, according to the present disclosure, a cellular phone 500, a laptop computer 505, and a tablet PC 510 can all include a continuously powered memory with a core. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a memory constructed according to the present disclosure.

[0035] As those skilled in the art will now appreciate and depending on the particular application at hand, many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments illustrated and described herein, as they are merely by way of some examples thereof, but should be fully commensurate with the scope of the appended claims and their functional equivalents.< / ith> < / ith> < / ith>

Claims

1. A memory, comprising: External power rail; a first core power rail configured to provide power to a first plurality of bit cells; a first power switch transistor coupled between the first core power rail and the external power rail; a first control transistor configured to be turned on in response to a control signal, wherein the first power switch transistor is configured to be turned on in response to the turning on of the first control transistor; a second core power rail configured to provide power to a second plurality of bit cells; a second power switch transistor coupled between the second core power rail and the external power rail; a first inverter configured to invert the sleep signal and drive the second power switch transistor; as well as a second control transistor having a source connected to ground, a drain connected to the first inverter, and a gate connected to the first core power rail, wherein the second power switch transistor is configured to be turned on in response to turning on of the second control transistor and assertion of a sleep signal to a power supply voltage, and is configured to be turned off in response to turning on of the second control transistor and discharge of the sleep signal to ground. 2 . The memory of claim 1 , wherein the second power switch transistor is a p-type metal oxide semiconductor (PMOS) transistor, and the control transistor is an NMOS transistor.

3. The memory of claim 1 , wherein the first power switch transistor is a PMOS transistor having a source connected to the external power rail and a drain connected to the first core power rail, and wherein the first control transistor is an NMOS transistor having a source connected to ground and a drain coupled to a gate of the first power switch transistor.

4. The memory according to claim 3, further comprising: A second inverter is configured to invert the sleep signal, wherein a drain of the first control transistor is connected to a ground node of the second inverter, and wherein an output node of the second inverter is connected to a gate of the first power switch transistor.

5. The memory according to claim 1, further comprising: a third core power rail configured to provide power to a third plurality of bit cells; a third power switch transistor coupled between the third core power rail and the external power rail; as well as A second control transistor has a gate connected to the second core power rail, wherein the third power switch transistor is configured to turn on in response to turning on of the second control transistor.

6. The memory of claim 5, wherein the third power switch transistor is a PMOS transistor and the second control transistor is an NMOS transistor having a source connected to ground and a drain coupled to a gate of the third power switch transistor.

7. The memory of claim 1 , wherein the first plurality of bit cells and the second plurality of bit cells are arranged in a first memory bank, the first memory bank having a final plurality of bit cells, the final plurality of bit cells being configured to be powered by a final power rail, the memory further comprising: The second memory bank comprises: a third plurality of bit cells configured to be powered by a third core power rail; a third power switching transistor coupled between the third core power rail and the external power rail; and A third control transistor has a gate connected to the final power rail, wherein the third power switch transistor is configured to turn on in response to the second control transistor being turned on.

8. The memory of claim 1, wherein the first plurality of bit cells are arranged into a first plurality of columns, and wherein the second plurality of bit cells are arranged into a second plurality of columns.

9. A method for powering up a memory, comprising: turning on the first control transistor in response to assertion of the control signal; in response to the turning on of the first control transistor, turning on a first power switch transistor to connect a first core power rail for the bit cells of the first core to an external power rail to charge the first core power rail from ground to a core power voltage, wherein the core power voltage is greater than a threshold voltage of the second control transistor; turning on the second control transistor to provide ground to the inverter in response to the first core power rail charging above the threshold voltage; When the second control transistor is turned on, the sleep signal is inverted through the inverter, and the sleep signal is charged to the core power supply voltage to discharge the inverter output signal; in response to the discharge of the inverter output signal, turning on a second power switch transistor to connect a second core power rail for bit cells of a second core to the external power rail to charge the second core power rail from ground to the core power voltage; When the second control transistor is turned on, the sleep signal is inverted by the inverter and the sleep signal is discharged at the same time, so as to charge the first inverter output signal to the core power supply voltage; and In response to the first inverter output signal being charged to the core power supply voltage, the second power switch transistor is turned off.

10. The method of claim 9, wherein the bit cells of the first core and the bit cells of the second core are arranged in a first bank of the memory, the method further comprising: powering up a final core power rail in the first bank for the memory from ground to the core supply voltage; turning on a third control transistor in response to the final core power rail charging above the threshold voltage; as well as In response to the turning on of the third control transistor, a third power switch transistor is turned on to connect a third power rail for bit cells of a third core in a second bank of the memory to the external power rail to charge the third power rail from ground to the core supply voltage.

11. The method according to claim 10, further comprising: A plurality of additional cores in the second bank of the memory are powered up sequentially according to a power up order, wherein each sequential additional core is powered up in response to a core power supply for a previous additional core rising above the threshold voltage.

12. The method according to claim 9, further comprising: turning on a third control transistor in response to the second core power rail charging above the threshold voltage; as well as In response to the turning on of the third control transistor, a third power switch transistor is turned on to connect a third core power rail of the bit cells of a third core to the external power rail to charge the third core power rail from ground to the core supply voltage.

Images