Method for manufacturing wiring board

Abstract

A method for manufacturing a wiring substrate, after performing a joining process of joining a joining portion (18a) of an FC-BGA wiring substrate (1) to a joining portion (18b) of an intermediary layer (3), performs: a resin supply process of filling a bottom filling glue (2A) between the FC-BGA wiring substrate (1) and the intermediary layer (3); a resin curing process of curing the bottom filling glue (2A); and a support body peeling process of peeling a support body (5) from the intermediary layer (3), wherein after performing the support body peeling process, a resin supply process is performed, and then a resin curing process is performed.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board. Background Art

[0002] In recent years, with the advancement of faster and more highly integrated semiconductor devices, FC-BGA (Flip Chip-Ball Grid Array) wiring boards have also required narrower pitches for connecting terminals to semiconductor devices and finer wiring on the boards. Meanwhile, the connection between FC-BGA wiring boards and motherboards requires the use of connecting terminals with a pitch that is roughly the same as before.

[0003] In order to narrow the pitch of the connection terminals connected to the semiconductor element and to miniaturize the substrate wiring, for example, Patent Document 1 below proposes a method in which wiring is formed on silicon to serve as a substrate (silicon interposer) for connecting the semiconductor element and then connected to an FC-BGA wiring substrate. Furthermore, Patent Document 2 below proposes a method in which the surface of the FC-BGA wiring substrate is flattened by chemical mechanical polishing (CMP) or the like, and then fine wiring is formed. Furthermore, Patent Document 3 below proposes a method in which a substrate (interposer) having a fine wiring layer is formed on a support, mounted on an FC-BGA substrate, and then the support is peeled off to form a narrow-pitch wiring substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-280490

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2014-225671

[0008] Patent Document 3: International Publication No. 2018 / 047861 Summary of the Invention

[0009] Problems to be solved by the present invention

[0010] In the method disclosed in Patent Document 1, silicon interposers are produced using silicon wafers and equipment used for semiconductor pre-processing. Silicon wafers have limited shapes and sizes, limiting the number of interposers that can be produced from a single wafer. Manufacturing equipment is also expensive, making interposers expensive. Furthermore, because silicon wafers are semiconductors, transmission characteristics degrade.

[0011] The method disclosed in Patent Document 2 does not suffer from the problem of transmission characteristic degradation encountered in Patent Document 1. However, it does suffer from issues such as reduced yields caused by defects in the manufacturing of the FC-BGA wiring board and defects in forming the challenging fine wiring, as well as problems with mounting semiconductor devices caused by warping and deformation of the FC-BGA wiring board.

[0012] The method disclosed in Patent Document 3 does not suffer from the problems of deterioration in transmission characteristics and reduced yield associated with the method disclosed in Patent Document 1 or Patent Document 2. However, it does suffer from the problem of defects being easily generated during the support peeling step, which can lead to reduced yield.

[0013] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a wiring board that can improve the throughput in the step of peeling off the support and manufacture the wiring board with a good yield.

[0014] Solutions to Problems

[0015] In order to solve the above-mentioned problems, the present invention relates to a method for manufacturing a wiring substrate, wherein the first wiring substrate is joined to a joining surface of a second wiring substrate on which wiring finer than that of the first wiring substrate is formed, and a semiconductor element is mounted on a surface of the second wiring substrate on the opposite side of the joining surface, characterized in that the following steps are performed: a step of forming a first electrode joined to the semiconductor element via a peeling layer on a support; a step of forming a multilayer wiring layer obtained by stacking a plurality of insulating resin layers and wiring layers on the first electrode; and a step of forming a second electrode joined to the first wiring substrate on the multilayer wiring layer, thereby manufacturing the second wiring substrate; and a step of joining the third electrode of the first wiring substrate joined to the second wiring substrate to the third electrode of the second wiring substrate. The invention relates to a method for manufacturing a support body stripping device according to the present invention. The method comprises the following steps: (1) performing the support body stripping process, performing the resin supply process, and then performing the resin curing process; (2) performing the support body stripping process, and then performing the resin curing process; (3) performing the resin removal process after the resin supply process: removing the sealing resin attached to the second wiring substrate, the peeling layer, and the peripheral edge of the support body; and performing the resin curing process.

[0016] Effects of the present invention

[0017] According to the method for producing a wiring board according to the present invention, the throughput in the step of peeling off the support can be improved, and production can be performed with a high yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [ Figure 1 ] is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by utilizing the first embodiment of the manufacturing method of the wiring substrate according to the present invention.

[0019] [ Figure 2 ] is a cross-sectional view showing a schematic structure of an example of an interposer used in the first embodiment of the method for manufacturing a wiring substrate according to the present invention.

[0020] [ Figure 3A ] is used for illustration Figure 2 Cross-sectional view of the fabrication steps of the interposer.

[0021] [ Figure 3B ] is used for illustration Figure 3A Cross-sectional view of subsequent fabrication steps.

[0022] [ Figure 3C ] is used for illustration Figure 3B Cross-sectional view of subsequent fabrication steps.

[0023] [ Figure 3D ] is used for illustration Figure 3C Cross-sectional view of subsequent fabrication steps.

[0024] [ Figure 3E ] is used for illustration Figure 3D Cross-sectional view of subsequent fabrication steps.

[0025] [ Figure 3F ] is used for illustration Figure 3E Cross-sectional view of subsequent fabrication steps.

[0026] [ Figure 3G ] is used for illustration Figure 3F Cross-sectional view of subsequent fabrication steps.

[0027] [ Figure 3H ] is used for illustration Figure 3G Cross-sectional view of subsequent fabrication steps.

[0028] [ Figure 3I ] is used for illustration Figure 3H Cross-sectional view of subsequent fabrication steps.

[0029] [ Figure 3J ] is used for illustration Figure 3I Cross-sectional view of subsequent fabrication steps.

[0030] [ Figure 3K ] is used for illustration Figure 3J Cross-sectional view of subsequent fabrication steps.

[0031] [ Figure 3L ] is used for illustration Figure 3K Cross-sectional view of subsequent fabrication steps.

[0032] [ Figure 3M ] is used for illustration Figure 3L Cross-sectional view of subsequent fabrication steps.

[0033] [ Figure 3N ] is used for illustration Figure 3M Cross-sectional view of subsequent fabrication steps.

[0034] [ Figure 4A ] is used for illustration Figure 3N Cross-sectional view of subsequent fabrication steps.

[0035] [ Figure 4B ] is used for illustration Figure 4A Cross-sectional view of subsequent fabrication steps.

[0036] [ Figure 5A ] is used for illustration Figure 4B Cross-sectional view of subsequent fabrication steps.

[0037] [ Figure 5B ] is used for illustration Figure 5A Cross-sectional view of subsequent fabrication steps.

[0038] [ Figure 5C ] is used for illustration Figure 5B Cross-sectional view of subsequent fabrication steps.

[0039] [ Figure 5D ] is used for illustration Figure 5C Cross-sectional view of subsequent fabrication steps.

[0040] [ Figure 6 ] is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by utilizing the second embodiment of the manufacturing method of the wiring substrate according to the present invention.

[0041] [ Figure 7A ] is used to explain the second embodiment of the method for manufacturing a wiring substrate according to the present invention. Figure 4B Cross-sectional view of subsequent fabrication steps.

[0042] [ Figure 7B ] is used for illustration Figure 7A Cross-sectional view of subsequent fabrication steps.

[0043] [ Figure 7C ] is used for illustration Figure 7B Cross-sectional view of subsequent fabrication steps.

[0044] [ Figure 7D ] is used for illustration Figure 7C Cross-sectional view of subsequent fabrication steps.

[0045] [ Figure 8 ] is a cross-sectional view showing a schematic structure of an example of a semiconductor package manufactured by utilizing the third embodiment of the manufacturing method of the wiring substrate according to the present invention.

[0046] [ Figure 9A ] is used to explain the third embodiment of the method for manufacturing a wiring substrate according to the present invention. Figure 4B Cross-sectional view of subsequent fabrication steps.

[0047] [ Figure 9B ] is used for illustration Figure 9A Cross-sectional view of subsequent fabrication steps.

[0048] [ Figure 9C ] is used for illustration Figure 9B Cross-sectional view of subsequent fabrication steps.

[0049] [ Figure 9D ] is used for illustration Figure 9C Cross-sectional view of subsequent fabrication steps.

[0050] [ Figure 9E ] is used for illustration Figure 9D Cross-sectional view of subsequent fabrication steps.

[0051] [ Figure 10 ] is a cross-sectional view for illustrating the manufacturing steps of another example 3 in the third embodiment of the method for manufacturing a wiring substrate according to the present invention. DETAILED DESCRIPTION

[0052] The embodiments of the method for manufacturing a wiring board according to the present invention will be described based on the drawings, but the present invention is not limited to the following embodiments described based on the drawings. It should be noted that the drawings are exaggerated for the sake of convenience.

[0053] <First embodiment>

[0054] based on Figure 1 、 2 , 3A to 3N, 4A, 4B, and 5A to 5D describe a first embodiment of a method for manufacturing a wiring board according to the present invention.

[0055] In the wiring substrate manufactured by the manufacturing method involved in this embodiment, the first wiring substrate is joined to the bonding surface of the second wiring substrate on which wiring is formed finer than that of the first wiring substrate, and the semiconductor element is mounted on the surface of the second wiring substrate on the opposite side of the bonding surface.

[0056] Specifically, if Figure 1 As shown, in the semiconductor package 100 on which the semiconductor element 4 is mounted, one surface side ( Figure 1 The lower surface side of the FC-BGA wiring substrate 1 is connected to one surface side (the lower surface side of the FC-BGA wiring substrate 1) of the first wiring substrate by a bonding portion 18 such as a solder bump, a copper cylinder (copper column) or a gold bump. Figure 1 The interposer 3 is a thin layer having fine wiring, and the fine wiring is composed only of a multilayer wiring layer obtained by laminating a plurality of insulating resin layers and wiring layers, that is, a build-up wiring layer.

[0057] An underfill 2A, an insulating sealing resin having adhesive properties, is embedded in the gap between the FC-BGA wiring board 1 and the interposer 3. The semiconductor element 4 is bonded to the other surface side of the interposer 3 via a bonding portion 20 consisting of a copper pillar and solder at its tip. Figure 1 An underfill 21 is embedded in the gap between the semiconductor element 4 and the interposer 3.

[0058] Underfill 2A is used to secure FC-BGA wiring substrate 1 to interposer 3 and seal joint 18. Examples of underfill 2A include epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, with a filler such as silicon dioxide, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide added. Underfill 2A can be formed by filling the gap between FC-BGA wiring substrate 1 and interposer 3 with a liquid form of one of these materials and allowing it to cure.

[0059] Underfill 21 is an adhesive used to secure semiconductor chip 4 to interposer 3 and seal joint 20, and is made of the same material as underfill 2A. It should be noted that, instead of underfills 2A and 21 that utilize capillary action to fill liquid resin after bonding, an anisotropic conductive film (ACF) or film-like connection material (NCF) that pre-disposes a sheet of film before bonding and fills the gap during bonding, or a non-conductive paste (NCP) that pre-disposes a liquid resin before bonding and fills the gap during bonding, can be used.

[0060] The intervals between the joints 20 between the interposer 3 and the semiconductor element 4 are generally narrower than the intervals between the joints 18 between the interposer 3 and the FC-BGA wiring board 1. Figure 1 The lower surface side in the figure) is the surface side bonded to the FC-BGA wiring substrate 1, and the other surface side ( Figure 1 The upper surface side (the upper surface side in FIG), that is, the surface side bonded to the semiconductor element 4, requires finer wiring.

[0061] For example, to meet current high-bandwidth memory (HBM) specifications, interposer 3 requires a wiring width of at least 2μm and no more than 6μm. To achieve a characteristic impedance match of 50Ω, when the wiring width is 2μm and the wiring height is 2μm, the insulation film thickness between the wirings is set to 2.5μm. If the thickness of one layer, including the wiring, is set to 4.5μm, then when five interposer 3 layers are formed with this thickness, the total thickness of the interposer 3 is approximately 25μm.

[0062] As mentioned above, the total thickness of the interposer 3 is as thin as about 25 μm. In this state, it is difficult to directly bond it to the FC-BGA wiring board 1. Therefore, it is effective to use a support 5 to ensure rigidity. In addition, in order to form a wiring with a width and height of about 2 μm, a flat support 5 is required. For the reasons mentioned above, Figure 2 As shown, the intermediary layer 3 is formed on a rigid and flat support 5 via a release layer 6, a protective layer 7, and a seed layer 8. It should be noted that layers other than the release layer 6, the protective layer 7, and the seed layer 8 may also be provided on the support 5.

[0063] Next, based on Figures 3A to 3N The method for manufacturing the interposer 3 (second wiring board manufacturing process) according to this embodiment will be described.

[0064] First, if Figure 3A As shown, a peeling layer 6 required for peeling the support 5 in a step described later is formed on one surface of the support 5 .

[0065] For example, the peeling layer 6 may be made of a resin that absorbs UV light or other light to generate heat or undergo degradation, thereby allowing peeling, or a resin that foams and allows peeling. When a resin that is peelable by UV light or other light is used, the support 5 can be removed from the bonded structure of the interposer 3 and the FC-BGA wiring board 1 by irradiating light onto the support 5 from the surface opposite to the side where the peeling layer 6 is provided.

[0066] In this case, the support 5 needs to be light-transmissive, and glass, for example, can be used. Glass has excellent flatness and is suitable for forming fine patterns on the interposer 3. Furthermore, glass has a low coefficient of thermal expansion (CTE) and is less susceptible to strain, making it excellent for ensuring pattern placement accuracy and flatness.

[0067] When glass is used as the support 5, from the perspective of suppressing warping during the manufacturing process, the glass is preferably thicker, for example, at least 0.7 mm, and particularly preferably at least 1.1 mm. Furthermore, the CTE of the glass is preferably at least 3 ppm and at most 15 ppm, and particularly preferably around 9 ppm from the perspective of the CTE of the FC-BGA wiring board 1 and the semiconductor element 4.

[0068] On the other hand, when a resin foamed by heat is used for the release layer 6, the support 5 can be removed by heating the bond between the interposer 3 and the FC-BGA wiring board 1. In this case, the support 5 can be made of a material with less strain, such as metal or ceramic.

[0069] In addition, in this embodiment, a resin that can be peeled by absorbing UV light is used as the peeling layer 6, and glass is used as the support 5.

[0070] Next, if Figure 3B As shown, a protective layer 7 is formed on the release layer 6. The protective layer 7 is a layer for protecting the interposer layer 3 when the support 5 is released in the process described later. Examples of the protective layer 7 include epoxy resins, acrylic resins, urethane resins, silicone resins, polyester resins, and oxetane resins, or a mixture of two or more of these resins.

[0071] The resin can be removed after the interposer 3 is peeled off from the support 5. The protective layer 7 can be formed appropriately by spin coating, lamination, etc. depending on the shape of the resin. In this embodiment, the protective layer 7 is formed by lamination using an acrylic resin.

[0072] Next, if Figure 3C As shown, in a vacuum, a seed layer 8 is formed on the protective layer 7. In the process of wiring formation, the seed layer 8 acts as a power supply layer for electroplating. The seed layer 8 can be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, a Cu alloy monomer or a combination of multiple materials, and can be formed by, for example, a sputtering method, a CVD method, or the like.

[0073] In this embodiment, a titanium layer and a copper layer are sequentially formed by sputtering, taking into account electrical properties, ease of manufacturing, and cost considerations. As the electroplated power supply layer, the combined thickness of the titanium and copper layers is preferably set to 1 μm or less. In this embodiment, the thickness of Ti is 50 nm and the thickness of Cu is 300 nm.

[0074] Next, if Figure 3D As shown, a resist pattern 9 is formed, and a conductor layer 10 serving as a first electrode is formed in the opening 9a thereof by electroplating. The conductor layer 10 becomes an electrode for bonding to the semiconductor element 4. Examples of electroplating methods include nickel electroplating, copper electroplating, chromium electroplating, palladium electroplating, gold electroplating, rhodium electroplating, and iridium electroplating. In particular, copper electroplating is preferred because it is easy to operate, inexpensive, and has good electrical conductivity. From the viewpoints of circuit connection reliability and manufacturing cost, the thickness of the electroplated copper is preferably not less than 1 μm and not more than 30 μm. Then, as Figure 3E As shown, the resist pattern 9 is removed.

[0075] Next, if Figure 3FAs shown, insulating resin layer 11 is formed. Insulating resin layer 11 is formed by embedding conductive layer 10 inside. In this embodiment, insulating resin layer 11 is formed by spin coating a photosensitive epoxy resin, for example. Photosensitive epoxy resins can be cured at relatively low temperatures and exhibit minimal shrinkage after curing, making them excellent for subsequent fine pattern formation.

[0076] In addition to the above, the insulating resin layer 11 can also be formed by compressing and curing an insulating resin film using a vacuum laminator. In this case, an insulating film with good flatness can be formed. In addition, for example, polyimide can also be used as the insulating resin.

[0077] Next, if Figure 3G As shown, openings 11a are formed in the insulating resin layer 11 on the conductive layer 10 by photolithography or the like. It should be noted that the openings 11a may be subjected to plasma treatment to remove residues from development.

[0078] Next, if Figure 3H As shown, a seed layer 12 is provided on the surface of the insulating resin layer 11 and the conductor layer 10 in the opening 11a. The seed layer 12 has the same composition and thickness as the seed layer 8, and can be appropriately changed as needed. In this embodiment, it is formed by sputtering so that Ti becomes 50nm and Cu becomes 300nm.

[0079] Next, if Figure 3I As shown, a resist pattern 13 is formed on the seed layer 12, and a conductor layer 14 serving as a wiring layer is formed in the opening 13a thereof by electroplating. The conductor layer 14 becomes the wiring layer inside the interposer 3. In this embodiment, copper is used as the conductor layer 14. Then, as shown in FIG. Figure 3J As shown, the resist pattern 13 is removed. Then, the unnecessary seed layer 12 is removed by etching.

[0080] Next, the above Figures 3F to 3J Repeat the process several times, such as Figure 3K As shown, a multilayer wiring layer is formed by laminating a plurality of insulating resin layers 11 and conductor layers 14. The conductor layer 15 located on the outermost surface is used as an electrode for bonding to the FC-BGA wiring board 1.

[0081] Next, if Figure 3LAs shown, outermost insulating resin layer 16 is provided on the surface of insulating resin layer 11 and conductive layer 15. Openings 16a are formed in outermost insulating resin layer 16 by exposure and development, etc., so that while insulating resin layer 11 is covered, a portion of conductive layer 15 is exposed. In this embodiment, outermost insulating resin layer 16 is formed using a photosensitive epoxy resin. It should be noted that outermost insulating resin layer 16 can be formed using the same material as insulating resin layer 11.

[0082] Next, if Figure 3M As shown, in order to prevent surface oxidation of the conductor layer 15 and improve the wettability of the solder bump, a surface treatment layer 17 is provided on the conductor layer 15 within the opening 16a. In this embodiment, an electroless Ni / Pd / Au plating film is formed as the surface treatment layer 17. It should be noted that an OSP (surface treatment using an organic solderability preservative / water-soluble preservative) film may also be formed on the surface treatment layer 17. In addition, an appropriate selection may be made from electroless tin plating, electroless Ni / Au plating, and the like, depending on the intended use.

[0083] Next, if Figure 3N As shown, solder material is applied to surface treatment layer 17 and solidified by a single melt cooling process, thereby forming a joint 18a consisting of solder bumps that join FC-BGA wiring board 1 and interposer 3. It should be noted that in this embodiment, the second electrode is composed of conductor layer 15, surface treatment layer 17, and joint 18a. As described above, interposer 3 formed on support 5 is obtained.

[0084] Next, based on Figure 4A 、 4B The process of bonding the interposer 3 and the FC-BGA wiring board 1 in this embodiment will be described.

[0085] like Figure 4A 、 4B As shown, interposer 3 formed on support 5 is placed on manufactured FC-BGA wiring substrate 1 and bonded together, thereby forming joint portion 18. FC-BGA wiring substrate 1 includes joint portion 18b, which is designed to mate with joint portion 18a of interposer 3 and serves as a third electrode. Specifically, interposer 3 is mounted on FC-BGA wiring substrate 1 using a placement machine, and a tape heating device (reflow) is used to melt and bond joint portion 18a of interposer 3 and joint portion 18b of FC-BGA wiring substrate 1, thereby forming joint portion 18.

[0086] It should be noted that when flux is used in solder bonding, it is desirable to perform a flux cleaning step after the bonding step. In the flux cleaning step, a through cleaning device is preferably used, but an ultrasonic cleaning device may also be used.

[0087] Then, based on Figures 5A to 5D A method for applying the underfill 2A and a method for removing the support 5 in this embodiment will be described.

[0088] First, if Figure 5A As shown in FIG. 1 , UV laser light L is irradiated onto the peeling layer 6 via the support 5, thereby peeling the support 5. Specifically, the other surface side ( Figure 5A The upper surface side in the figure (i.e., the surface opposite to the surface connected to the FC-BGA wiring substrate 1) is irradiated with a scanning laser L via the support 5, so that the peeling layer 6 formed at the interface with the support 5 becomes peelable. Figure 5B As shown, the support 5 is removed via the release layer 6 (the above is referred to as the support release step).

[0089] It should be noted that the removal of the support 5 varies depending on the properties of the release layer 6. When the retention of the release layer 6 is reduced, it can be easily removed by pulling the support 5. In addition, when the retention of the release layer 6 is strong, for example, a sheet with strong adhesiveness is adhered to the support 5, and the sheet can be removed by pulling the sheet.

[0090] Next, if Figure 5C As shown, underfill 2A is applied between interposer 3 and FC-BGA wiring substrate 1 (the above is the resin supply process). Underfill 2A is supplied and filled using a dispenser that pressurizes and discharges the underfill using a syringe. An air-dispensing or jet-dispensing underfill applicator can be used to apply underfill 2A to a position adjacent to interposer 3. The applied underfill 2A fills the space between interposer 3 and FC-BGA wiring substrate 1 through capillary action.

[0091] If the amount of underfill 2A supplied per unit time is too high, the disadvantageous situation of underfill 2A overflowing over the interposer 3 may occur. Therefore, in this embodiment, the underfill 2A is supplied to fill the gap between the interposer 3 and the FC-BGA wiring board 1 in multiple cycles with intervals of at least 3 seconds. This prevents the underfill 2A from overflowing over the interposer 3.

[0092] Then, underfill 2A is heated to a temperature equal to or higher than the curing temperature to cure underfill 2A, thereby fixing interposer 3 and FC-BGA wiring board 1 and sealing joint 18 (the above is a resin curing step).

[0093] After completing the support peeling process, resin supply process and resin curing process in this way, Figure 5D As shown, protective layer 7 is removed, and then seed layer 8 is removed, thereby obtaining wiring substrate 22A. In this embodiment, protective layer 7 made of acrylic resin is removed using an alkaline solvent (1% NaOH, 2.3% TMAH). Furthermore, seed layer 8 made of titanium and copper is dissolved and removed, starting from the protective layer 7 side, using an alkaline etchant and an acidic etchant, respectively. In this way, wiring substrate 22A can be manufactured by bonding interposer 3 to wiring substrate 1 for FC-BGA.

[0094] It should be noted that, in order to prevent oxidation and improve the wettability of the solder bump, the conductor layer 10 exposed on the surface may be further subjected to surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, or electroless Ni / Au plating.

[0095] In the manufacturing method of the wiring substrate 22A involved in such an embodiment, after the support body peeling process is performed, the resin supply process is performed, and then the resin curing process is performed, so that the bottom filling glue 2A can be prevented from surrounding the periphery of the support body 5, and the support body 5 can be prevented from remaining fixed as the bottom filling glue 2A cures.

[0096] Therefore, in the method for manufacturing the wiring board 22A according to the present embodiment, by irradiating the release layer 6 with the laser light L as described above, the support 5 can be easily and reliably released from the protective layer 7 .

[0097] Therefore, according to the method for manufacturing the wiring substrate 22A according to the present embodiment, the throughput in the step of peeling the support 5 can be improved, and the wiring substrate 22A can be manufactured with a good yield.

[0098] Furthermore, by performing flux cleaning before peeling the support body 5 from the interposer 3 , the interposer 3 can be cleaned while being protected by the support body 5 .

[0099] In addition, since the gap between the FC-BGA wiring substrate 1 and the interposer 3 is sealed by the bottom filler 2A, the connection portion 18 can be protected from the effects of the alkaline etchant or acidic etchant used to remove the protective layer 7 and the seed layer 8, thereby preventing a decrease in connection reliability.

[0100] <Second embodiment>

[0101] based on Figure 6 、 7A 7D to 7D describe a second embodiment of the method for manufacturing a wiring board according to the present invention. However, the same reference numerals as those used in the description of the above embodiment are used for the same parts as those in the above embodiment, and redundant descriptions are omitted.

[0102] like Figure 6 As shown, in the wiring substrate 22B of the semiconductor package 100B according to this embodiment, the underfill 2B is thicker than the surface of the interposer 3 on the side connected to the semiconductor element 4 ( Figure 6 The upper surface in the middle) is closer to the semiconductor element 4 side ( Figure 6 Except for this, the wiring substrate 22B has the same structure as the wiring substrate 22A of the semiconductor package 100A according to the above embodiment.

[0103] In the manufacturing method of the wiring substrate 22B according to the present embodiment, the bonding step ( Figure 4B The steps of manufacturing the wiring board 22A are the same as those in the above-mentioned embodiment.

[0104] Then, if Figure 7A As shown, the interposer 3 and the FC-BGA wiring substrate 1 are sealed, and the bottom filling glue 2B is supplied in a manner surrounding the interposer 3, seed layer 8, protective layer 7, peeling layer 6 and the periphery of the support body 5 to temporarily fix the interposer 3 and the FC-BGA wiring substrate 1 formed on the support body 5 (the above is the resin supply process).

[0105] Next, if Figure 7B As shown, laser light L is applied to the release layer 6 through the support 5. Even with the laser light L, the support 5 does not peel off because the underfill 2B adheres to the outer edges of its sides and is bonded to the support 5. Next, the underfill 2B is softened by heating, reducing its adhesion to the support 5, making it easier to peel the support 5 from the underfill 2B (this is the resin adhesion reduction step).

[0106] Then, if Figure 7C As shown, after the support body 5 is removed (the above is the support body peeling process), the bottom filling glue 2B is cured by heating it to above the curing temperature to fix the interposer 3 and the FC-BGA wiring substrate 1 and seal the joint 18 (the above is the resin curing process).

[0107] Next, if Figure 7D As shown, protective layer 7 and seed layer 8 are removed in the same manner as in the above embodiment. In this manner, wiring board 22B in which interposer 3 and FC-BGA wiring board 1 are bonded together can be manufactured.

[0108] In the manufacturing method of the wiring substrate 22B involved in such an embodiment, after the resin supply process, the resin adhesion reduction process is performed, then the support body peeling process is performed, and then the resin curing process is performed, so that the support body 5 can be freed from the adhesion of the support body 5 caused by the bottom filling glue 2B attached to the periphery of the support body 5, so that the support body 5 can be easily removed.

[0109] Therefore, in the method for manufacturing the wiring substrate 22B according to the present embodiment, the throughput in the step of peeling the support 5 can be improved, and the wiring substrate 22B can be manufactured with a good yield.

[0110] <Third embodiment>

[0111] based on Figure 8 、 9A 9E describe a third embodiment of the method for manufacturing a wiring board according to the present invention. However, the same reference numerals as those used in the description of the above embodiment are used for the same parts as those in the above embodiment, and redundant descriptions are omitted.

[0112] like Figure 8 As shown, in the wiring substrate 22C of the semiconductor package 100C according to this embodiment, the underfill 2C is thicker than the surface ( Figure 8 The upper surface in the middle) is closer to the FC-BGA wiring substrate 1 side ( Figure 8 Except for this, the wiring substrate 22C has the same structure as the wiring substrates 22A and 22B of the semiconductor packages 100A and 100B according to the above-described embodiments.

[0113] In the manufacturing method of the wiring substrate 22C according to the present embodiment, the bonding step ( Figure 4B The steps in the above embodiment are the same as those in the method for manufacturing the wiring substrates 22A and 22B.

[0114] Then, if Figure 9A As shown in FIG. 1 , the bottom filler 2C is filled between the interposer 3 and the FC-BGA wiring board 1 (the above is the resin supply process). Figure 9BAs shown, when the bottom filler removal jig T such as a scraper is used to remove the bottom filler and the side of the interposer 3 ( Figure 9B While in contact with the left and right surfaces in the drawing and the front and back surfaces in the drawing, the interposer 3 is slid and moved along the peripheral edge of the interposer 3, thereby scraping off and removing the bottom filling glue 2C attached to the side surface of the interposer 3, at least closer to the support body 5 than the insulating resin layer 11 (the above is the resin removal process).

[0115] That is, because the seed layer 8, protective layer 7, and release layer 6 are closer to the support 5 than the insulating resin layer 11, at least the underfill 2C adhering to the outer peripheral edges of the seed layer 8, protective layer 7, release layer 6, and the side surfaces of the support 5 is removed. In this embodiment, only the underfill 2C closer to the support 5 than the insulating resin layer 11 is removed, and the underfill 2C located on the side surfaces of the insulating resin layer 11 is not removed.

[0116] The underfill removal jig T may be, for example, a flat scraper, preferably with a tapered end in the thickness direction. The scraper may be appropriately selected based on various conditions. Furthermore, the underfill removal jig T is preferably made of a relatively low-hardness material, such as silicone rubber, urethane, Teflon (registered trademark), other rubbers, and plastics.

[0117] Next, the bottom filler 2C is heated and cured to fix the interposer 3 and the FC-BGA wiring board 1 and seal the joint 18 (the above is the resin curing step). Figure 9C As shown in FIG. 1 , laser light L is irradiated onto the peeling layer 6 via the support 5. Then, as shown in FIG. Figure 9D As shown, the support 5 is peeled off in the same manner as in the case of the above embodiment. Figure 9E As shown, protective layer 7 and seed layer 8 are removed in the same manner as in the above embodiment (the above is the support stripping step). In this manner, wiring board 22C in which interposer 3 and FC-BGA wiring board 1 are bonded can be manufactured.

[0118] In the manufacturing method of the wiring substrate 22C involved in such an embodiment, after the resin supply process, the following resin removal process is performed: the bottom filling glue 2C located on the side of the interposer 3 and at least closer to the support body 5 than the insulating resin layer 11 is removed, and then the resin curing process is performed, and then the support body peeling process is performed. Therefore, regardless of the shape of the bottom filling glue 2C when it is supplied, the shape of the bottom filling glue 2C after curing can be controlled, thereby preventing the support body 5 from remaining fixed as the bottom filling glue 2C cures.

[0119] Therefore, in the method for manufacturing the wiring board 22C according to the present embodiment, similarly to the above-described embodiment, by irradiating the release layer 6 with the laser light L, the support 5 can be easily and reliably released from the protective layer 7 .

[0120] Therefore, according to the method for manufacturing the wiring board 22C according to the present embodiment, similarly to the case of the above-described embodiment, the throughput in the step of peeling the support 5 can be improved, and the wiring board 22C can be manufactured with a good yield.

[0121] Furthermore, by using the aforementioned material having a relatively low hardness for the underfill removal jig T, the underfill removal jig T can be more easily adapted to the side surface shape of the interposer 3 , thereby enabling more reliable removal of the underfill 2C.

[0122] Other Example 1 of the Third Implementation Method

[0123] It should be noted that in the third embodiment described above, a material with a relatively high hardness can also be used for the underfill removal jig T. Specifically, for example, any one of Cu, Ti, Sn, Fe, Al, Cr, Ag, Au, Pt, Ni, and Mn, or an alloy of two or more of these, or a composite of two or more of these, can be used. Using such a relatively high-hardness material for the underfill removal jig T can suppress deformation of the underfill removal jig T during removal of the underfill 2C, thereby improving the positional accuracy of the underfill 2C removal.

[0124] Other Example 2 of the Third Implementation Method

[0125] Furthermore, in the third embodiment described above, a syringe needle connected to a suction mechanism can be used as the underfill removal jig T to remove the underfill 2C adhering to the outer peripheral edge of the side surface of the interposer 3 by suctioning it. Using a syringe needle connected to such a suction mechanism as the underfill removal jig T can prevent the underfill 2C from spreading onto the underfill removal jig T during the removal process and reattaching to the interposer 3. Furthermore, the removed underfill 2C can be prevented from spreading across the width of the FC-BGA wiring substrate 1.

[0126] Other Example 3 of the Third Implementation Method

[0127] Furthermore, in the third embodiment, the mask forming step may be performed before the resin supplying step, the resin removing step may be performed, and then the mask removing step may be performed before the resin curing step.

[0128] Specifically, if Figure 10As shown, a peelable first mask 23 is formed on a portion of the surface of the FC-BGA wiring substrate 1 facing the interposer 3, and a peelable second mask 24 is formed on the surface of the support 5 opposite to the surface on which the interposer 3 is provided.

[0129] The first and second masks 23 and 24 can be made of a material that can be patterned and peeled off. For example, a photosensitive dry film resist or liquid photosensitive resist for wiring formation can be used. When the first and second masks 23 and 24 are photosensitive dry film resists, roll lamination methods, vacuum lamination methods, etc. can be used. When liquid photosensitive resists are used, spin coating methods, slit coating methods, screen printing methods, gravure offset printing methods, etc. can be used.

[0130] In the first mask 23, openings 23a for filling the underfill 2C are formed by photolithography. The openings 23a of the first mask 23 can be formed along the entire outer periphery of the side surface of the interposer 3, or only on a portion thereof. The thickness of the first mask 23 is set to be less than or equal to the thickness of the interposer 3.

[0131] Through the opening 23a of the first mask 23, underfill 2C is filled between the interposer 3 and the FC-BGA wiring board 1. The underfill 2C adhering to the outer edges of the side surfaces of the interposer 3 is removed using an underfill removal jig T in the same manner as described above. The underfill removal jig T is preferably large enough (high enough) to abut against the first mask 23. After the underfill 2C is cured, the first and second masks 23 and 24 are removed. A stripping solution for removing photosensitive resin is used to remove the first and second masks 23 and 24.

[0132] In this manufacturing method, the first mask 23 is formed in advance on a portion of the surface of the FC-BGA wiring board 1 facing the interposer 3 before the resin supply step, and the resin removal step is performed. Then, the first mask 23 is removed before the resin curing step. This allows the shape of the underfill 2C after curing to be controlled with high precision. That is, for example, Figure 10 As shown, by setting the first mask 23 to a thickness approximately the same as the thickness of the outermost insulating resin layer 16 of the intermediary layer 3, the bottom filling glue removal fixture T can be configured in a manner abutting against the first mask 23, so that the bottom filling glue 2C at the interface between the insulating resin layer 11 and the outermost insulating resin layer 16, that is, up to the lowest position of the insulating resin layer 11, can be removed.

[0133] In addition, before the resin supply process, the second mask 24 is pre-formed on the surface of the support body 5 on the opposite side to the surface on which the interposer 3 is provided, and the resin removal process is performed. Then, the second mask 24 is removed before the resin curing process is performed, so that the bottom filling glue 2C wetted to the surface of the support body 5 on the opposite side to the surface on which the interposer 3 is provided can be easily removed.

[0134] It should be noted that the above-mentioned embodiment is an example, and other specific detailed structures and the like can be appropriately changed.

[0135] Industrial Applicability

[0136] The present invention can be used for a semiconductor device having a wiring substrate including an interposer and the like interposed between a main substrate and an IC chip.

[0137] Explanation of symbols

[0138] 1 FC-BGA wiring board (first wiring board)

[0139] 2A, 2B, 2C, 21 bottom filler (sealing resin)

[0140] 3 Interposer (Second Wiring Board)

[0141] 4 Semiconductor components

[0142] 5 Support

[0143] 6 Peeling layer

[0144] 7 protective layer

[0145] 8, 12 seed layers

[0146] 9.13 Resist pattern

[0147] 9a, 13a openings

[0148] 10 Conductor layer (first electrode)

[0149] 11 Insulating resin layer

[0150] 11a Opening

[0151] 14 Conductor layer (wiring layer)

[0152] 15 Conductor layer

[0153] 16. Outermost insulating resin layer

[0154] 16a Opening

[0155] 17 Surface treatment layer

[0156] 18, 18a, 18b, 20 joints

[0157] 22A, 22B, 22C wiring boards

[0158] 23 1st Mask

[0159] 23a Opening

[0160] 24 Second Mask

[0161] L Laser (UV light)

[0162] T Underfill Removal Fixture

Claims

1. A method for manufacturing a wiring board, wherein: The first wiring substrate is bonded to a bonding surface of a second wiring substrate having wiring finer than that of the first wiring substrate, and a semiconductor element is mounted on a surface of the second wiring substrate opposite to the bonding surface, wherein the following steps are performed: a second wiring substrate manufacturing step of manufacturing the second wiring substrate by performing: a step of forming a first electrode bonded to the semiconductor element on a support via a peeling layer; a step of forming a multilayer wiring layer obtained by laminating a plurality of insulating resin layers and wiring layers on the first electrode; and a step of forming a second electrode bonded to the first wiring substrate on the multilayer wiring layer, thereby manufacturing the second wiring substrate; and a joining step of joining the third electrode of the first wiring substrate joined to the second wiring substrate to the second electrode of the second wiring substrate, Then proceed with: a resin supplying step of filling a sealing resin between the first wiring substrate and the second wiring substrate; a resin curing step of curing the sealing resin; and a support peeling step of peeling the support from the second wiring substrate via the peeling layer, After the resin supplying step, a resin removing step is performed to remove the sealing resin attached to the second wiring substrate, the peeling layer, and the outer peripheral edge of the support, followed by the resin curing step, and then the support peeling step. Before the resin supply process, a process of forming a first mask on a portion of the surface of the first wiring substrate opposite to the second wiring substrate is performed, and the resin removal process is performed, and then before the resin curing process is performed, a process of removing the first mask is performed.

2. The method for manufacturing a wiring board according to claim 1, wherein: After the bonding step is performed, a flux cleaning step is performed.

3. The method for manufacturing a wiring board according to claim 1 or 2, wherein: In the second wiring board manufacturing step, a step of further forming a protective layer and a seed layer between the release layer and the first electrode is performed.

4. The method for manufacturing a wiring board according to claim 3, wherein: After the resin supplying step, the support peeling step, and the resin curing step are performed, a step of removing the protective layer and then removing the seed layer is performed.

5. The method for manufacturing a wiring board according to claim 1 or 2, wherein: In the resin supplying step, the sealing resin is filled in a plurality of times.

6. The method for manufacturing a wiring board according to claim 5, wherein: In the resin supplying step, the sealing resin is filled separately at intervals of 3 seconds or more.

7. The method for manufacturing a wiring board according to claim 1 or 2, wherein: The resin removal step is a step of scraping and removing the sealing resin with a scraper.

8. The method for manufacturing a wiring board according to claim 1 or 2, wherein: The resin removal step is a step of removing the sealing resin by sucking it out with an injection needle.

9. The method for manufacturing a wiring board according to claim 1 or 2, wherein: Before the resin supply process, a process of forming a second mask on the surface of the support body opposite to the surface on which the second wiring substrate is set is performed, and the resin removal process is performed, and then before the resin curing process, a process of removing the second mask is performed.

10. The method for manufacturing a wiring board according to claim 1 or 2, wherein: The support body is made of glass.

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