I2C bus detection device and method

Abstract

The present invention discloses an I2C bus detection device and method, wherein the device comprises: a bus status detection module; a counter; a register group; a data serial-to-parallel conversion module; and an address comparison module. The bus status detection module is connected to the counter, which is connected to the data serial-to-parallel conversion module, which is connected to the register group, and the address comparison module is connected to the register group. The device and method utilize gate-level circuits, which can reduce circuit area and improve chip performance per unit area. The device and method lack a system clock and utilize an asynchronous circuit design, which can improve module compatibility.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and in particular to an I2C bus detection device and method. Background Art

[0002] The current market demands increasingly higher chip functionality and performance. Therefore, to better control chip features and enhance their flexibility, numerous registers are required to configure chip functions. At the same time, to improve system stability and reduce costs, the chip's peripheral circuitry must be kept as simple as possible. To maintain good compatibility, these registers are typically configured via the Philips I2C interface. However, the aforementioned prior art suffers from the following technical issues: Most chip configurations utilize synchronous designs, resulting in limited compatibility and unsuitable for mobile devices and video surveillance equipment, which have high power consumption and area requirements. Summary of the Invention

[0003] One of the inventive objectives of the present invention is to provide an I2C bus detection device and method, which are constructed using gate-level circuits, can reduce the circuit area and improve the performance of the chip per unit area.

[0004] Another object of the present invention is to provide an I2C bus detection device and method, which has no system clock and is designed as an asynchronous circuit, thereby improving module compatibility.

[0005] Another object of the present invention is to provide an I2C bus detection device and method, which can reduce the total power consumption of the chip while reducing the circuit area, and can improve the battery life when applied to mobile devices.

[0006] In order to achieve at least one of the above-mentioned objects, the present invention further provides an I2C bus detection device, comprising:

[0007] Bus status detection module;

[0008] counter;

[0009] register bank;

[0010] Data conversion module;

[0011] Address comparison module;

[0012] The bus state detection module is connected to the counter, the counter is connected to the data conversion module, the data conversion module is connected to the register group, and the address comparison module is connected to the register group.

[0013] According to one of the preferred embodiments of the present invention, the data conversion module includes an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, and the register group includes a first output end and a second output end, wherein the first output end is connected to the input data serial-to-parallel conversion module, and the second output end is connected to the output data parallel-to-serial conversion module.

[0014] According to another preferred embodiment of the present invention, the address comparison module includes a slave address comparison module and an on-chip address selection module, wherein the input data serial-to-parallel conversion module is connected to the slave address comparison module, the slave address comparison module is connected to the on-chip address selection module, and the on-chip address selection module is connected to the register group.

[0015] According to another preferred embodiment of the present invention, the device includes a data input interface, a clock input interface and a data output interface, and the counter is an 8-bit memory, wherein the data input interface is respectively arranged in the bus status detection module, the input data serial-to-parallel conversion module and the address comparison module.

[0016] According to another preferred embodiment of the present invention, the device includes a data output line enable interface and a reset interface, wherein the data output line enable interface is provided in the output data parallel-to-serial conversion module, and the reset interface is provided in the bus status detection module.

[0017] According to another preferred embodiment of the present invention, the register group includes 9 registers, wherein the 9 registers are configured as 8-bit registers.

[0018] According to another preferred embodiment of the present invention, the counter includes a clock signal output interface, and the clock signal output interface is respectively connected to the input data serial-to-parallel conversion module, the output data parallel-to-serial conversion module and the address comparison module.

[0019] According to another preferred embodiment of the present invention, the bus status detection module includes a clock signal enable interface, and the clock signal enable interface is connected to the counter.

[0020] According to another preferred embodiment of the present invention, the bus status detection module includes a signal start interface and a signal stop interface, wherein the signal start interface and the signal stop interface are connected to the counter respectively.

[0021] In order to achieve at least one of the above-mentioned objects, the present invention further provides an I2C bus detection method comprising:

[0022] The bus state detection module samples the D trigger of the input clock signal at the falling edge of the input data signal to generate a first detection signal;

[0023] Sampling the first detection signal at a rising edge of a clock signal to generate a second detection signal, and performing ANDing of the first detection signal and the inverted signal of the second detection signal to generate an initial detection signal;

[0024] The clock output signal is counted and output according to the clock SCL clock cycle;

[0025] The reset signal and reset error signal clear the count asynchronously when pulled high;

[0026] Or when the count enable signal is high, the reference signal is high and the address comparison fails, the count is cleared synchronously.

[0027] According to one of the preferred embodiments of the present invention, the input serial-to-parallel conversion module includes a shift register. When the count enable signal is high, the serial data is saved in the input serial-to-parallel conversion module through the data input interface, and when the count value is 8, the stored 8-bit serial data is compared with its own slave address plus 1 bit. If the comparison is successful, a response signal is returned, and if the comparison fails, a non-response signal is returned. The host executes communication and non-communication instructions respectively according to the response signal and non-response signal.

[0028] The present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program can be executed by a processor to detect the I2C bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a structural schematic diagram of an I2C bus detection device of the present invention.

[0030] Figure 2 Shown is a schematic structural diagram of the bus detection module in the present invention.

[0031] Figure 3 Shown is a schematic structural diagram of a counter in the present invention.

[0032] Figure 4 Shown is an interface diagram of the input data serial-to-parallel conversion module in the present invention.

[0033] Figure 5 Shown is an interface diagram of the output data parallel-to-serial conversion module in the present invention.

[0034] Figure 6 Shown is a schematic diagram of the interface of the address comparison module in the present invention.

[0035] Figure 7 Shown is a flow chart of a detection method for an I2C bus according to the present invention. DETAILED DESCRIPTION

[0036] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0037] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0038] Please combine Figure 1-Figure 7 The present invention discloses an I2C bus detection device and method, wherein the device includes the following components: a bus state detection module, a counter, a register group, a data conversion module, and an address comparison module, wherein the bus state detection module is connected to the corresponding I2C bus for detecting I2C bus-related signals, the bus state detection module is connected to the counter, the counter itself includes an SCL clock and counts according to the cycle of the SCL clock, the counter is connected to the data conversion module, wherein the data conversion module includes an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, the counter is connected to the input data serial-to-parallel conversion module, the register includes a first output interface and a second output interface, the first output interface is connected to the input data serial-to-parallel conversion module, and the second output interface is connected to the output data parallel-to-serial conversion module, the address comparison module includes a slave address comparison module and an off-chip address selection module, wherein the input data serial-to-parallel conversion module is connected to the slave address comparison module, the slave address comparison and conversion module is connected to the off-chip address selection module, the off-chip address selection module has an output end, and the output end of the off-chip address selection module is connected to the register group.

[0039] Please refer to Figure 2The present invention discloses an interface diagram of the bus state detection module, wherein the bus state detection module is connected to the i_scl signal line, which is connected to the clock interface of the bus state detection module for inputting a clock signal (i_scl); the bus state detection module is also connected to the i_sda signal line, which is connected to the data input interface of the bus state detection module for obtaining a data input signal (i_sda); the output end of the bus state detection module includes a start signal interface for outputting a start signal (start), the bus state detection module includes a reference signal interface for outputting a reference signal (rs), the bus state detection module includes an error reference signal interface for outputting an error reference signal (rs_error), the bus state detection module includes a stop signal interface and a count signal enable interface, the stop signal interface is used to generate a stop signal (stop), and the count signal enable interface is used to generate a count enable signal (cnt_en). It should be noted that the above-mentioned bus state detection module can be composed of, including but not limited to, a single-chip microcomputer, and the above-mentioned functions can be achieved through different interfaces and logic settings, which will not be described in detail in the present invention.

[0040] The bus status detection module is connected to the counter, please refer to Figure 3 The input end of the counter includes a start signal interface, a stop signal interface, an error reference signal interface and a count enable interface, which are respectively connected to the start signal interface, stop signal interface, error reference signal interface and count enable interface corresponding to the output end of the bus state detection module. The output end of the counter includes: a count signal output interface, which is used to output a count signal (cnt_scl), wherein the counter includes a shift register, and the shift register.

[0041] Please refer to Figure 4The counter is connected to an input data serial-to-parallel conversion module, wherein the input end of the input data serial-to-parallel conversion module includes a count signal input interface, wherein the count signal input interface is connected to the count signal output interface of the counter for obtaining a count signal (cnt_scl), wherein the input end of the input data serial-to-parallel conversion module also includes a data input interface, wherein the data input interface of the input data serial-to-parallel conversion module is connected to a register group for obtaining a data input signal (i_sda) in the register group, wherein the input data serial-to-parallel conversion module also includes a clock interface, wherein the clock interface is connected to the register group for obtaining an input clock signal (i_scl) in the register group. The output end of the input data serial-to-parallel conversion module includes a parallel data output interface for outputting parallel data (reg_data), wherein the input end of the address comparison module includes a count signal input interface, wherein the count signal input interface is connected to the count signal output interface of the counter for obtaining a count signal (cnt_scl) on the counter, wherein the input end of the address comparison module also includes a data signal input interface and a clock signal input interface, respectively for obtaining an external data input signal and a clock signal, and wherein the address comparison module also includes a reference signal input interface for obtaining a reference signal from a storage register. The address comparison module includes an address matching output interface for outputting an address matching signal (match / rd_match). The output data parallel-to-serial conversion module is connected to a register bank. The input end of the output data parallel-to-serial conversion module includes a counting signal input interface, a parallel data input interface, a clock signal input interface, and an address matching signal input interface, which respectively receive a counting signal (cnt_scl), parallel data (reg_data), a clock signal (i_scl), and an address matching signal (match / rd_match). The input end signals of the output data parallel-to-serial conversion module are obtained from the register bank. The output end of the output data parallel-to-serial conversion module includes a data output interface and an output data line enable interface, which are respectively used to generate a data output signal (o_sda) and an output data enable signal (o_sda_en).

[0042] In order to better illustrate the present invention, the present invention further provides the following specific I2C bus detection method based on the above-mentioned I2C bus detection device:

[0043] A D-type flip-flop sampling i_scl on the falling edge of i_sda detects the start signal start_cnd0. On the rising edge of i_scl, start_cd0 is sampled to generate the start_cnd1 signal. The start pulse signal is formed by ANDing the start_cnd0 signal with the inverse of the start_cnd1 signal. The start pulse signal is the actual start signal for the circuit. The cnt_en signal pulls high when the start signal is detected as high on the falling edge of i_scl and is asynchronously reset when the stop signal is high. After cnt_en pulls high, cnt_scl counts SCL clock cycles on the rising edge of i_scl until cnt_en goes low and stops incrementing. The count value is asynchronously reset to zero when both rs_error and stop signals pull high. The shift register in the input serial-to-parallel converter stores the serial data on the i_sda line when cnt_en is high. When cnt_scl is 8, the stored 8-bit data is compared with the 7-bit slave address plus a 1-bit write (low) signal. When o_sda_en (the o_sda enable signal) is pulled high, o_sda outputs the inverse of the comparison result: a successful comparison pulls o_sda low, while a failed comparison pulls o_sda high. This signals an ACK or NACK response. When cnt_scl is 17 or 26, the upper and lower 8 bits of the internal register address are compared, respectively. If the rs signal is not pulled high after the response, it indicates a read operation. The rs signal is detected in the same way as the start signal, but remains high until stop is cleared asynchronously. During a read operation, the selected register at count 35 is written to the current value of shift register 0. After responding to the acknowledge signal, the host sends the stop signal, completing the register configuration. The stop signal, i_sda, is generated by sampling i_scl on the rising edge and is asynchronously cleared when the next start signal goes high. If rs is high, the data in shift register 0 is compared when cnt_scl counts to 36. The comparison value is the slave address plus one bit read (high). If the comparison is successful, the 8-bit data of the selected configuration register is written to shift register 1 on the falling edge of i_scl. i_sda then outputs the 8-bit data sequentially over the next eight i_scl clock cycles. The communication ends after the host responds with a no-acknowledge signal and a stop signal. If an abnormal repeated start signal is detected during the transmission, the rs_error signal generates a single-cycle pulse, asynchronously clearing the counter value. If the stop signal is abnormal, the transmission ends immediately.

[0044] In particular, according to the embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above-mentioned functions defined in the method of the present application are executed. It should be noted that the computer-readable medium mentioned above in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, a system, device or device of an electrical, magnetic, optical, electromagnetic, infrared segment, or semiconductor, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wire segments, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including, but not limited to, an electromagnetic signal, an optical signal, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, electrical wire, optical fiber cable, RF, etc., or any suitable combination thereof.

[0045] The flow charts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0046] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments. Without departing from the principles, the implementation methods of the present invention may be subject to any deformation or modification.

Claims

1. A detection method for an I2C bus, characterized in that: include: The bus state detection module samples the D trigger of the input clock signal at the falling edge of the input data signal to generate a first detection signal; Sampling the first detection signal at a rising edge of a clock signal to generate a second detection signal, and performing ANDing of the first detection signal and the inverted signal of the second detection signal to generate an initial detection signal; The clock output signal is counted and output according to the clock SCL clock cycle; The reset signal and reset error signal clear the count asynchronously when pulled high; Or when the count enable signal is high, the reference signal is high and the address comparison fails, the count is cleared synchronously; Specifically, it includes: receiving cnt_scl, i_sda and i_scl signals through the input data serial-to-parallel conversion module and outputting reg_data signal; receiving cnt_scl, reg_data, i_scl, match and rd_match signals through the output data parallel-to-serial conversion module and outputting o_sda and o_sda_en signals; receiving cnt_scl, i_sda, i_scl and rs signals through the address comparison module and outputting match and rd_match signals; The start signal start_cnd0 is detected by sampling the D flip-flop of i_scl on the falling edge of i_sda, and the start_cd0 is sampled on the rising edge of i_scl to generate the start_cnd1 signal; the start pulse signal is formed by the inverse signal of the start_cnd0 signal and the start_cnd1 signal, and the start pulse signal is the actual circuit start signal; the cnt_en signal will be pulled high when the start signal is detected to be high on the falling edge of i_scl, and will be asynchronously reset when the stop signal is high; after cnt_en is pulled high, cnt_scl will count the SCL clock cycles on the rising edge of i_scl until the count value no longer increases when cnt_en is low, and the count value will be asynchronously cleared after the rs_error signal and the stop signal are pulled high; the shift register will store the serial data of the i_sda line when cnt_en is high, and the 8-bit data stored will be compared with its own 7-bit slave address plus 1 bit when cnt_scl is 8, and o_sda_en, that is, the o_sda enable signal, will be pulled high. o_sda will output the opposite value of the comparison result, that is, if the comparison is successful, o_sda will be pulled low, and if the comparison fails, o_sda will be pulled high, thereby replying a response signal ACK or a non-response signal NACK; if the rs signal is not pulled high after the response, it is a read operation, and the rs signal detection method is the same as the start signal, but it will remain until the stop is high and then asynchronously cleared to zero; during the read operation, when the count is 35, the selected register will be written to the value of shift register 0 at this time. After replying to the acknowledgment signal, the host sends the termination signal stop to complete the register configuration, and is asynchronously cleared to zero when the next start signal is pulled high; if rs is high, the data in shift register 0 will be compared when cnt_scl counts to 36, and the comparison value is read as its own slave address plus 1 bit. If the comparison is successful, the 8-bit data of the selected configuration register will be written to shift register 1 on the falling edge of i_scl, and i_sda will output 8 data in sequence in the next 8 i_scl clock cycles.

2. A detection device for an I2C bus, characterized in that: The I2C bus detection method according to claim 1 is applied, wherein the device comprises: Bus status detection module; counter; register bank; Data conversion module; Address comparison module; Wherein, the bus state detection module is connected to the counter, the counter is connected to the data conversion module, the data conversion module is connected to the register group, and the address comparison module is connected to the register group; The data conversion module includes an input data serial-to-parallel conversion module and an output data parallel-to-serial conversion module, and the register group includes a first output end and a second output end, wherein the first output end is connected to the input data serial-to-parallel conversion module, and the second output end is connected to the output data parallel-to-serial conversion module; The address comparison module includes a slave address comparison module and an on-chip address selection module, wherein the input data serial-to-parallel conversion module is connected to the slave address comparison module, the slave address comparison module is connected to the on-chip address selection module, and the on-chip address selection module is connected to the register group, the register group includes 9 registers, and the 9 registers are configured as 8-bit registers.

3. The I2C bus detection device according to claim 2, wherein: The device includes a data input interface, a clock input interface and a data output interface, and the counter is an 8-bit memory, wherein the data input interface is respectively arranged in the bus state detection module, the input data serial-to-parallel conversion module and the address comparison module.

4. The I2C bus detection device according to claim 2, wherein: The device comprises a data output line enable interface and a reset interface, wherein the data output line enable interface is arranged in the output data parallel-to-serial conversion module, and the reset interface is arranged in the bus state detection module.

5. The I2C bus detection device according to claim 2, characterized in that: The counter includes a clock signal output interface, which is respectively connected to the input data serial-to-parallel conversion module, the output data parallel-to-serial conversion module and the address comparison module. The bus status detection module includes a clock signal enable interface, which is connected to the counter.

6. The I2C bus detection device according to claim 2, characterized in that: The bus state detection module includes a signal start interface and a signal stop interface, wherein the signal start interface and the signal stop interface are connected to the counter respectively.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program can be executed by a processor to detect the I2C bus method according to claim 1.

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