A method and apparatus for monitoring memory bandwidth

Abstract

The embodiment of the application discloses a kind of method and device for monitoring memory bandwidth, it is related to computer field.The method comprises: the memory bandwidth size that process group is accessed volatile memory is used in the preset period is obtained by processor core, and after the memory operation that process group executes in the preset period is counted, the memory bandwidth size that process group is accessed non-volatile memory is used is calculated according to memory bandwidth size and the memory operation of counting.It is realized to monitor the memory bandwidth of non-volatile memory with process group as granularity, and then the memory bandwidth size of non-volatile memory is used as the basis for limiting the memory bandwidth of non-volatile memory.

Description

[0001] This application claims priority to Chinese Patent Application No. 202010691597.4, filed on July 17, 2020, entitled "A Method and Apparatus for Monitoring Memory Bandwidth", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to a method and apparatus for monitoring memory bandwidth. Background Technology

[0003] With the development and prosperity of cloud technology, a single server can run multiple processes from different tenants. These processes share various server resources (such as computing, storage, and memory resources) to improve resource utilization. However, resource sharing can lead to performance unfairness. For example, processes with the same priority may receive different resources. Or, a low-priority process may consume a large amount of resources, while a high-priority process may not be able to obtain sufficient resources, impacting tenant services and reducing user experience. Traditionally, control groups (cgroups) are used to divide multiple processes into different groups, with each group using different resources (such as computing, storage, and memory). Additionally, resource director technology is used to identify processes consuming excessive amounts of volatile memory bandwidth and limit their volatile memory usage to ensure other processes have access to sufficient memory resources.

[0004] Because the bandwidth of non-volatile memory (NVM) is significantly lower than that of volatile memory, bandwidth contention for NVM is much more intense in multi-tenant cloud environments, potentially leading to service degradation or even outages. However, since NVM lacks bandwidth limiting functionality, resource allocation techniques cannot monitor and limit its bandwidth. Therefore, how to monitor NVM bandwidth is a pressing issue that needs to be addressed. Summary of the Invention

[0005] This application provides a method and apparatus for monitoring memory bandwidth, which realizes the monitoring of non-volatile memory bandwidth at the process group level, and then uses the memory bandwidth of non-volatile memory as the basis for limiting the memory bandwidth of non-volatile memory.

[0006] Firstly, a method for monitoring memory bandwidth is provided for monitoring the memory bandwidth of non-volatile memory. The method includes: a processor core obtaining the memory bandwidth used by a process group to access volatile memory within a preset period, and statistically analyzing the memory operations performed by the process group within the preset period; then calculating a first memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth and the statistically analyzed memory operations. Here, memory operations include both non-volatile and volatile memory operations. Thus, the processor core estimates the memory bandwidth used by the process group to access volatile memory based on the non-volatile memory operations, volatile memory operations, and the memory bandwidth used by the process group to access volatile memory within the preset period. This software method enables monitoring of non-volatile memory bandwidth at the process group level, and the non-volatile memory bandwidth is used as a basis for limiting the memory bandwidth of non-volatile memory.

[0007] It is worth noting that the memory operations performed by a process group within a preset period can be understood as the memory addresses accessed by the memory operations performed by the process group within the preset period. Memory operations are memory read and write operations. A process group includes at least one process. In some embodiments, a process group can be a container or a virtual machine. All processes contained in a process group can be run by a container or a virtual machine. In other embodiments, the processes contained in a process group can be run by multiple containers or multiple virtual machines. That is, the processes contained in a process group are processes in multiple containers. Alternatively, the processes contained in a process group are processes in multiple virtual machines.

[0008] In one possible design, the first memory bandwidth used by the process group to access non-volatile memory is calculated based on the memory bandwidth size and statistical memory operations. This includes: the processor core determining the amount of non-volatile memory accessed by the process group and the proportion of volatile memory accesses based on the memory addresses accessed by memory operations; and calculating the first memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth size and the proportion. Since the memory addresses accessed by memory operations include both non-volatile and volatile memory addresses, the memory type and size of the accessed memory can be determined based on these addresses. Memory types include both non-volatile and volatile memory. Memory size includes the size of volatile memory accessed by the process group and the size of non-volatile memory accessed by the process group. Furthermore, the processor core determines the amount of non-volatile memory accessed by the process group and the proportion of volatile memory accesses based on the memory size and type of the memory operations. Understandably, the amount of time a process group accesses non-volatile memory is equal to the amount of non-volatile memory accessed by the process group. The amount of time a process group accesses volatile memory is equal to the amount of volatile memory accessed by the process group.

[0009] Optionally, the memory operations performed within the preset period can be all memory operations or a portion of the memory operations within the preset period.

[0010] Furthermore, after calculating the first memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth size and statistical memory operations, the method further includes: if the first memory bandwidth size of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, setting a memory bandwidth limit for the process group, where the non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for the process group to access non-volatile memory. Thus, by controlling the memory bandwidth used by the process group to access volatile memory through limiting measures, the memory bandwidth used by the process group to access non-volatile memory is indirectly limited. This avoids the situation where excessive use of non-volatile memory bandwidth by a process group, container, or virtual machine affects other process groups, containers, or virtual machines' access to non-volatile memory, resolving the problem of performance degradation or even interruption caused by the spread of adjacent interference faults.

[0011] Setting memory bandwidth limits for process groups includes one or more of the following: adjusting a first volatile memory bandwidth threshold for the process group to a second volatile memory bandwidth threshold, where the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first and second volatile memory bandwidth thresholds refer to the maximum allowed memory bandwidth for the process group to access volatile memory. By reducing the maximum allowed volatile memory bandwidth for the process group, the total memory bandwidth used by the process group for both volatile and non-volatile memory is reduced, indirectly reducing the memory bandwidth used by the process group for non-volatile memory, thus limiting the non-volatile memory bandwidth to any value.

[0012] The processes contained in the process group are moved from the first processor core running the process group to the second processor core. Because the number of processes contained in the process group running on a processor core is reduced, the process group's memory operations on volatile and non-volatile memory are reduced accordingly. The total memory bandwidth used by the process group for both volatile and non-volatile memory is also reduced, indirectly reducing the memory bandwidth of non-volatile memory used by the process group, thus limiting the memory bandwidth of non-volatile memory to an arbitrary value.

[0013] The first time slice of the process group is adjusted to the second time slice, with the first time slice being longer than the second time slice. Both the first and second time slices represent the duration the process group occupies the first processor core. Because the duration the process group occupies the processor core is shortened, the process group's memory operations on volatile and non-volatile memory decrease accordingly. This reduces the total memory bandwidth used by the process group for both volatile and non-volatile memory, indirectly reducing the memory bandwidth used for non-volatile memory. This effectively limits the non-volatile memory bandwidth to any value.

[0014] In one possible design, if the first volatile memory bandwidth threshold of a process group is adjusted to a second volatile memory bandwidth threshold, and the second non-volatile memory bandwidth size is greater than or equal to the non-volatile memory bandwidth threshold, the processes contained in the process group are migrated from the first processor core running the process group to the second processor core. Optionally, the first and second processor cores belong to one or more NUMA nodes in a non-uniform memory access (NUMA) system.

[0015] In one possible design, if the processes contained in a process group are migrated from the first processor core to the second processor core, the first time slice of the process group is adjusted to the second time slice when the third memory bandwidth of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0016] In this way, the dynamic adjustment method can precisely control the memory bandwidth of non-volatile memory to a specific value, avoid business performance degradation or even interruption, and reduce resource deployment costs.

[0017] After limiting the memory bandwidth of non-volatile memory, if the memory bandwidth of non-volatile memory monitored by the processor core is less than the non-volatile memory bandwidth threshold, the restriction on process group access to volatile memory can be lifted, which indirectly increases the memory bandwidth used by process group to access non-volatile memory, so that process group has sufficient available resources.

[0018] In one possible design, after adjusting the first time slice of the process group to the second time slice, the method further includes: when the fourth memory bandwidth of non-volatile memory is less than the non-volatile memory bandwidth threshold, adjusting the second time slice of the process group to the first time slice. Because the duration of processor core usage by the process group is increased, the memory operations of the process group on volatile and non-volatile memory increase accordingly. The total memory bandwidth used by the process group for both volatile and non-volatile memory also increases, indirectly increasing the memory bandwidth of non-volatile memory used by the process group, thus ensuring that the process group has sufficient available resources.

[0019] In one possible design, after adjusting the second time slice of the process group to the first time slice, the method further includes: when the fifth memory bandwidth of non-volatile memory is less than the non-volatile memory bandwidth threshold, migrating the processes contained in the process group from the second processor core to the first processor core. Because the number of processes contained in the process group running on the processor core increases, the memory operations of the process group on volatile and non-volatile memory increase accordingly. The total memory bandwidth used by the process group for volatile and non-volatile memory also increases, indirectly increasing the memory bandwidth of non-volatile memory used by the process group, thus ensuring that the process group has sufficient available resources.

[0020] In one possible design, after migrating the processes contained in the process group from the second processor core to the first processor core, the method further includes: when the sixth memory bandwidth of non-volatile memory is less than the non-volatile memory bandwidth threshold, adjusting the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold. Because the maximum value of the volatile memory bandwidth used by the process group is increased, the total memory bandwidth of both volatile and non-volatile memory used by the process group also increases, indirectly increasing the memory bandwidth of non-volatile memory used by the process group, thus ensuring that the process group has sufficient available resources.

[0021] It should be noted that the non-volatile memory bandwidth threshold is set through the first file system interface. The first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set through the second file system interface.

[0022] Secondly, a method for limiting memory bandwidth is provided, comprising: if the first memory bandwidth used by a process group to access non-volatile memory within a preset period is greater than or equal to a non-volatile memory bandwidth threshold, adjusting the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold, wherein the non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth of the process group to access non-volatile memory, the first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both the first and second volatile memory bandwidth thresholds refer to the maximum allowed memory bandwidth of the process group to access volatile memory, and the process group includes at least one process; when the second memory bandwidth of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, migrating the processes included in the process group from the first processor core running the process group to the second processor core. In this way, by using a dynamic adjustment method to control the volatile memory bandwidth used by process groups to access volatile memory, the memory bandwidth of non-volatile memory is indirectly limited to any value. This avoids the situation where process groups, containers, or virtual machines use too much non-volatile memory bandwidth, which would prevent other process groups, containers, or virtual machines from accessing non-volatile memory. This solves the problem of business performance degradation or even interruption caused by the spread of adjacent interference faults.

[0023] In one possible design, after migrating the processes contained in the process group from the first processor core running the process group to the second processor core, the method further includes: when the third memory bandwidth of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, adjusting the first time slice of the process group to a second time slice, wherein the first time slice is longer than the second time slice, and both the first time slice and the second time slice are the duration for which the process group occupies the first processor core.

[0024] In one possible design, after adjusting the first time slice of the process group to the second time slice, the method further includes: adjusting the second time slice of the process group to the first time slice when the fourth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold.

[0025] In one possible design, after adjusting the second time slice of the process group to the first time slice, the method further includes: when the fifth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold, migrating the processes contained in the process group from the second processor core to the first processor core.

[0026] In one possible design, after migrating the processes contained in the process group from the second processor core to the first processor core, the method further includes: when the sixth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold, adjusting the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.

[0027] Thirdly, a device for monitoring memory bandwidth is provided, the beneficial effects of which are described in the first aspect and will not be repeated here. The device for monitoring memory bandwidth has the function of implementing the behavior in the method example of the first aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function. In one possible design, the device for monitoring memory bandwidth includes: an acquisition unit, a monitoring unit, and a limiting unit. The acquisition unit is used to acquire the memory bandwidth used by a process group to access volatile memory within a preset period, and to statistically analyze the memory operations performed by the process group within the preset period. The memory operations include non-volatile memory operations and volatile memory operations, and the process group includes at least one process. The monitoring unit is used to calculate a first memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth size and the statistically analyzed memory operations. The limiting unit is used to set a memory bandwidth limit for the process group if the first memory bandwidth size is greater than or equal to a non-volatile memory bandwidth threshold, where the non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for the process group to access non-volatile memory. These units can perform the corresponding functions in the method examples of the first aspect above, as detailed in the method examples, which will not be repeated here.

[0028] Fourthly, a device for limiting memory bandwidth is provided, the beneficial effects of which are described in the second aspect and will not be repeated here. The device for limiting memory bandwidth has the function of implementing the behavior in the method example of the second aspect. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function. In one possible design, the device for limiting memory bandwidth includes: an acquisition unit and a limiting unit. The acquisition unit is used to acquire the memory bandwidth used by a process group to access non-volatile memory within a preset period. The limiting unit is used to adjust the first volatile memory bandwidth threshold of the process group to a second volatile memory bandwidth threshold if the first memory bandwidth used by the process group to access non-volatile memory within the preset period is greater than or equal to a non-volatile memory bandwidth threshold. The non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for the process group to access non-volatile memory. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first and second volatile memory bandwidth thresholds refer to the maximum allowed memory bandwidth for the process group to access volatile memory. The process group includes at least one process. The limiting unit is further configured to migrate processes contained in the process group from the first processor core running the process group to the second processor core when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold. The limiting unit is also configured to adjust the first time slice of the process group to a second time slice when the third memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold. The first time slice is longer than the second time slice, and both the first and second time slices represent the duration the process group occupies the first processor core. These modules can perform the corresponding functions in the method examples of the second aspect described above; please refer to the detailed description in the method examples for details, which will not be repeated here.

[0029] Fifthly, a processor is provided, comprising a plurality of processor cores for executing the method of monitoring memory bandwidth as described in the first aspect or any possible design of the first aspect. The processor cores can execute the operational steps of the method executed by the first processor core in the method examples of the first aspect described above, as detailed in the method examples, and will not be repeated here.

[0030] Sixthly, a processor is provided, comprising a plurality of processor cores for executing the method of limiting memory bandwidth in the second aspect or any possible design of the second aspect. The processor cores can execute the operational steps of the method executed by the second processor core in the method examples of the second aspect described above, as detailed in the method examples, and will not be repeated here.

[0031] In a seventh aspect, a server is provided, the server including at least one processor as described in the fifth aspect and main memory, the processor including a plurality of processor cores, each processor core being configured to perform operational steps of the method for monitoring memory bandwidth as described in the first aspect or any possible implementation thereof.

[0032] Eighthly, a server is provided, comprising at least one processor as described in the sixth aspect and main memory, the processor comprising a plurality of processor cores, each processor core being configured to perform operational steps of the method for limiting memory bandwidth as described in the second aspect or any possible implementation thereof.

[0033] A ninth aspect provides a computer-readable storage medium comprising: computer software instructions; which, when executed in a server, cause the server to perform operational steps of the method as described in the first aspect or any possible implementation thereof.

[0034] A tenth aspect provides a computer-readable storage medium comprising: computer software instructions; which, when executed in a server, cause the server to perform operational steps of the method as described in the second aspect or any possible implementation thereof.

[0035] Eleventhly, a computer program product is provided that, when run on a computer, causes the computer to perform the operational steps of the method as described in the first aspect or any possible implementation thereof.

[0036] In a twelfth aspect, a computer program product is provided that, when run on a computer, causes the computer to perform the operational steps of the method as described in the second aspect or any possible implementation thereof.

[0037] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0038] Figure 1 A simplified schematic diagram of a cloud environment provided for an embodiment of this application;

[0039] Figure 2 A flowchart illustrating a method for monitoring memory bandwidth provided in this application embodiment;

[0040] Figure 3 A flowchart illustrating a method for monitoring memory bandwidth provided in this application embodiment;

[0041] Figure 4 A flowchart illustrating a method for monitoring memory bandwidth provided in this application embodiment;

[0042] Figure 5 A schematic diagram of process migration provided in an embodiment of this application;

[0043] Figure 6 A flowchart illustrating a method for limiting memory bandwidth provided in an embodiment of this application;

[0044] Figure 7 A flowchart illustrating a method for limiting memory bandwidth provided in an embodiment of this application;

[0045] Figure 8 A schematic diagram illustrating a process for dynamically limiting memory bandwidth, provided as an embodiment of this application;

[0046] Figure 9 A schematic diagram illustrating the composition of a device for monitoring memory bandwidth provided in an embodiment of this application;

[0047] Figure 10 A schematic diagram illustrating the composition of a device for limiting memory bandwidth, provided in an embodiment of this application;

[0048] Figure 11 This is a schematic diagram of the composition of a server provided in an embodiment of this application. Detailed Implementation

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] A cloud environment is an entity that provides cloud services to users using basic resources under the cloud computing model. For example... Figure 1 As shown, the cloud environment 100 includes a cloud data center 110 and a cloud service platform 120. The cloud data center 110 includes a large amount of basic resources owned by the cloud service provider (including computing resources 111, storage resources 112, and memory resources 113).

[0051] Computing resources 111 can be a large number of computing devices (e.g., servers). These computing devices include multiple processors, for example... Figure 1 The processors 1111 and 1112 are shown in the diagram. Processor 1111 is the control center of the computing device. Typically, processor 1111 is a central processing unit (CPU), which includes one or more processor cores, for example... Figure 1The processor cores 0 and 1 are shown in the diagram. Furthermore, processor 1111 can also be an application-specific integrated circuit (ASIC), or configured as one or more integrated circuits, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). Processor core 0 and processor core 1 can refer to the physical or logical processor cores within processor 1111. Processor 1111 can perform various functions of the computing device by running or executing software programs stored in storage resource 112 and accessing data stored in storage resource 112 and memory resource 113. Processor 1112 can be a processor with the same physical form as processor 1111, or a processor with a different physical form. However, processor 1112 is a processing chip with computing capabilities, used to offload the processes running by processor 1111, thereby reducing the computational burden on processor 1111.

[0052] Memory resource 113 includes non-volatile memory 1131 and volatile memory 1132. Volatile memory includes random access memory (RAM). Non-volatile memory is characterized by non-volatility, byte-by-byte access, high storage density, low power consumption, and read / write performance close to dynamic random access memory (DRAM), but its read / write speeds are asymmetrical, with reads being much faster than writes, and its lifespan is limited. Data stored in non-volatile memory is not lost when the current is turned off. Common types of non-volatile memory include phase-change memory (PCM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FeRAM), racetrack memory, and graphene memory.

[0053] In terms of physical form, storage resource 112 can be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Storage resource 112 can exist independently or can be connected to computing resource 111 via a communication bus. Storage resource 112 can also be integrated with computing resource 111, without limitation. Communication buses can be industry standard architecture (ISA) buses, peripheral component (PCI) buses, or extended industry standard architecture (EISA) buses, etc. These buses can be categorized into address buses, data buses, control buses, etc.

[0054] In addition, storage resource 112 is also used to store software programs that execute the scheme of this application, and the execution is controlled by computing resource 111.

[0055] Users can access various services (such as financial services, gaming services, etc.) provided by the cloud service platform 120 through terminal device 130. When multiple service processes 114 for different users are running on the computing device, the processes of multiple services share basic resources (such as computing resources 111, storage resources 112, and memory resources 113, etc.).

[0056] To avoid unfairness caused by multiple processes sharing basic resources, resource control groups (cgroups) are used to divide multiple processes into different process groups. Different process groups use different resources (such as computing resources, storage resources, and memory resources). A process group includes at least one process.

[0057] Resource control groups (RCGs) are a resource control mechanism that divides all processes in an operating system into groups, organizing these groups hierarchically. Each process group is assigned a set of access resources (e.g., computing resources, storage resources, and memory resources). Different process groups access different resources. For example, processes in different process groups may access different amounts of memory and have different memory bandwidths. System administrators can configure the processes contained in each process group through the First File System Interface (FSI). The FSI is used to configure the processes contained in a process group. A user's application processes can be assigned to the same process group or different process groups. A process group can contain processes from the same application or processes from different applications.

[0058] When a processor core is running processes within a process group, it can access both volatile and non-volatile memory. Traditionally, resource director technology is used to identify processes consuming excessive volatile memory bandwidth and limit their volatile memory usage to ensure other processes have sufficient memory resources. Since non-volatile memory does not provide bandwidth limiting functionality, resource director technology cannot monitor and limit its bandwidth. This embodiment provides a method for monitoring memory bandwidth. Based on the memory bandwidth used by a process group accessing volatile memory within a preset period and memory operations, the method estimates the memory bandwidth used by the process group accessing non-volatile memory. This allows for monitoring of non-volatile memory bandwidth at the process group level, and the non-volatile memory bandwidth is then used as a basis for limiting overall memory bandwidth.

[0059] Next, combined Figure 2 The method for monitoring memory bandwidth provided in this embodiment will be described in detail.

[0060] S201, the first processor core obtains the memory bandwidth used by the process group to access volatile memory within a preset period, and counts the memory operations performed by the process group within the preset period.

[0061] The kernel is the core of an operating system, responsible for managing system processes, memory, device drivers, files, and network systems, and determining system performance and stability. When the first processor core runs processes within a process group, memory bandwidth monitoring (MBM) technology can be used to view kernel memory management information and obtain the memory bandwidth used by the process group to access volatile memory within a preset period. The preset period can be 1 second.

[0062] Memory operations include non-volatile memory operations and volatile memory operations. Memory operations performed by a process group within a preset period can be understood as the memory addresses accessed by the process group within that preset period.

[0063] In some embodiments, the first processor core monitors the read / write interface of the file system, collects memory operations performed on the system's memory through the file system's read / write interface within a preset period, and obtains the memory addresses accessed by the memory operations. Since the system contains both non-volatile and volatile memory, the memory addresses accessed by the memory operations include the memory addresses of both non-volatile and volatile memory.

[0064] In other embodiments, the first processor core utilizes precise event-based sampling (PEBS) technology to collect other memory access operations. These other memory access operations include, but are not limited to: memory operations that map a file or other object into memory, memory operations that access shared memory, memory operations that access file descriptors, and memory operations that access piped files.

[0065] Optionally, the memory operations performed within the preset period may be all memory operations or a portion of the memory operations within the preset period. For example, the memory operations counted by the first processor core may be memory operations for a portion of the preset period, such as memory operations for half the preset period. The memory operations include memory read / write operations on volatile memory and memory read / write operations on non-volatile memory.

[0066] S202, the first processor core calculates the memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth size and statistical memory operations.

[0067] Specifically, Figure 3 The method described is... Figure 2 The specific operational process included in S202 is illustrated in the figure: S2021, the first processor core determines the amount of non-volatile memory accessed by the process group and the ratio of the amount of volatile memory accessed by the process group based on the memory addresses accessed by memory operations. S2022, the first processor core calculates the memory bandwidth used by the process group to access non-volatile memory based on the memory bandwidth size and ratio.

[0068] Since memory operations access memory addresses including those accessed by non-volatile memory operations performed by process groups and those accessed by volatile memory operations performed by process groups, the type of memory accessed can be determined based on the memory address accessed, including both non-volatile and volatile memory.

[0069] The amount of non-volatile memory accessed can be determined by the memory addresses accessed by the process group performing non-volatile memory operations. The amount of non-volatile memory accessed can be understood as the size of non-volatile memory accessed by the process group.

[0070] The amount of volatile memory accessed can be determined by the memory addresses accessed by the process group performing volatile memory operations. The amount of volatile memory accessed can be understood as the size of volatile memory accessed by the process group.

[0071] Furthermore, the first processor core determines the ratio of the amount of non-volatile memory accessed by the process group to the amount of volatile memory accessed by the process group based on the amount of non-volatile memory accessed by the process group and the amount of volatile memory accessed by the process group.

[0072] The memory bandwidth used by a process group to access non-volatile memory satisfies formula (1).

[0073] B2=B1*(d2 / d1) (1)

[0074] Where B2 represents the memory bandwidth used by the process group to access non-volatile memory within the preset period, B1 represents the memory bandwidth used by the process group to access volatile memory within the preset period, d1 represents the number of times the process group accesses volatile memory within the preset period, and d2 represents the number of times the process group accesses non-volatile memory within the preset period. d2 / d1 represents the ratio of the number of times the process group accesses non-volatile memory to the number of times the process group accesses volatile memory.

[0075] Understandably, the first processor core can use MBM technology to view memory management information in the kernel and obtain the memory bandwidth B1 used by the process group to access volatile memory within a preset period. d1 and d2 are obtained by the first processor core through the file system's read / write interface for memory operations on system memory and other memory access operations.

[0076] For example, a system administrator can assign a unique identifier to a user's service process. The first processor core uses this identifier to monitor the memory bandwidth used by the process group to access volatile memory within a preset period, and to sample the memory addresses accessed by the memory operations performed by the process group. Specifically, the first processor core monitors the memory bandwidth at the start time T1 of the preset period as Bo, and the memory bandwidth at the end time T2 of the preset period as Bn. The absolute value of the difference between Bn and Bo is the memory bandwidth used by the process group to access volatile memory within the preset period. Assuming that the memory bandwidth B1 used by the process group to access volatile memory within the preset period is 10G / s, the first processor core samples 60,000 memory addresses accessed by memory operations within the preset period, of which 20,000 addresses are non-volatile memory addresses and 40,000 addresses are volatile memory addresses. The ratio of the number of non-volatile memory accesses by the process group to the number of volatile memory accesses by the process group is 20,000 / 40,000 = 0.5. The memory bandwidth used by the process group to access non-volatile memory is 20000 / 40000*10G / s=5G / s.

[0077] In this way, the processor core estimates the memory bandwidth used by the process group to access volatile memory based on the non-volatile memory operations, volatile memory operations, and the memory bandwidth used by the process group to access volatile memory within a preset period. It realizes the monitoring of non-volatile memory bandwidth at the process group level through software methods, and then uses the memory bandwidth of non-volatile memory as the basis for limiting the memory bandwidth of non-volatile memory.

[0078] Furthermore, after monitoring the memory bandwidth used by process groups to access non-volatile memory (referred to as: non-volatile memory bandwidth), the non-volatile memory bandwidth can be used as a basis for limiting the non-volatile memory bandwidth, combined with... Figure 4 The method for limiting memory bandwidth provided in this embodiment will be described in detail.

[0079] S401, the first processor core determines whether the memory bandwidth of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0080] If the non-volatile memory bandwidth is greater than or equal to the non-volatile memory bandwidth threshold, execute S402; if the non-volatile memory bandwidth is less than the non-volatile memory bandwidth threshold, and if the first processor core has not set a memory bandwidth limit for the process group, continue executing S201 and S202. Optionally, if the first processor core has set a memory bandwidth limit for the process group, execute S403. The non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for accessing non-volatile memory. System administrators can set the non-volatile memory bandwidth threshold for different process groups accessing non-volatile memory through the second file system interface. For example, the allowed non-volatile memory bandwidth for different process groups in each preset period can be limited.

[0081] S402, the first processor core sets the memory bandwidth limit for the process group.

[0082] After the first processor core sets the memory bandwidth limit for the process group, it executes S201 and S202, which means it continues to monitor the memory bandwidth used by the process group to access non-volatile memory and determines whether the memory bandwidth of non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0083] S403, the first processor core removes the memory bandwidth limit for the process group.

[0084] The first processor core can remove the memory bandwidth limit for a process group by reversing the process group's memory bandwidth limit. After removing the memory bandwidth limit for the process group, the first processor core executes S201 and S202, which means it continues to monitor the memory bandwidth used by the process group to access non-volatile memory and determines whether the non-volatile memory bandwidth is greater than or equal to the non-volatile memory bandwidth threshold.

[0085] The following section details the specific implementation of setting memory bandwidth limits for process groups on the first processor core.

[0086] In a first possible implementation, the first processor core adjusts a first volatile memory bandwidth threshold for the process group to a second volatile memory bandwidth threshold. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold, and both thresholds refer to the maximum allowed memory bandwidth for the process group to access volatile memory. The first processor core can call a third file system interface to adjust the maximum allowed memory bandwidth for the process group to access volatile memory.

[0087] In some embodiments, the first processor core can adjust the first volatile memory bandwidth threshold with an adjustment step size of 0.2 G / s. For example, if the memory bandwidth of non-volatile memory in the i-th preset period is greater than or equal to the non-volatile memory bandwidth threshold, the first processor core reduces the first volatile memory bandwidth threshold by 0.2 G / s to obtain a third volatile memory bandwidth threshold, which is greater than the second volatile memory bandwidth threshold. Furthermore, the first processor core obtains the memory bandwidth of non-volatile memory in the (i+1)-th preset period. If the memory bandwidth of non-volatile memory in the (i+1)-th preset period is greater than or equal to the non-volatile memory bandwidth threshold, the first processor core further reduces the third volatile memory bandwidth threshold by 0.2 G / s to obtain a fourth volatile memory bandwidth threshold, which is greater than the second volatile memory bandwidth threshold. If the memory bandwidth of non-volatile memory in the (i+1)-th preset period is less than the non-volatile memory bandwidth threshold, there is no need to set a memory bandwidth limit for the process group. i is an integer. System administrators can set and adjust the step size based on factors such as business needs.

[0088] If the first processor core adjusts the first volatile memory bandwidth threshold with a granularity of 0.2 G / s until the first volatile memory bandwidth threshold is reduced to the second volatile memory bandwidth threshold, but the non-volatile memory bandwidth size is still greater than or equal to the non-volatile memory bandwidth threshold, the first processor executes the second possible implementation, that is, the first processor core migrates the processes contained in the process group from the first processor core running the process group to the second processor core.

[0089] Understandably, the second volatile memory bandwidth threshold is the maximum limit on the memory bandwidth used by a process group to access volatile memory. The system administrator can set the first volatile memory bandwidth threshold through the third file system interface. The system administrator can be the personnel responsible for business deployment. For example, the system administrator might use volatile memory bandwidth allocation (MBA) technology to set the first volatile memory bandwidth threshold for a process group through the third file system interface.

[0090] By reducing the maximum memory bandwidth of volatile memory used by the process group, that is, by restricting the process group's access to volatile memory, the memory bandwidth of volatile memory used by the process group is reduced accordingly. As a result, the total memory bandwidth of volatile and non-volatile memory used by the process group is also reduced, and indirectly, the memory bandwidth of non-volatile memory used by the process group is also reduced, thus achieving the restriction of non-volatile memory bandwidth to any value.

[0091] In the second possible implementation, the first processor core migrates processes from the process group to the second processor core, which then runs the migrated processes. The second processor core can be the first processor core with fewer running processes. The number of processes migrated from the first processor core to the second processor core can be set by the system administrator or determined by the system itself. The first processor core can migrate one or two processes at a time, without limitation. If the first processor core migrates half of the processes in the process group to the second processor core, and the non-volatile memory bandwidth is still greater than or equal to the non-volatile memory bandwidth threshold, the first processor executes the third possible implementation, where the first processor core adjusts the first time slice of the process group to the second time slice, where the first time slice is longer than the second time slice.

[0092] By reducing the number of processes in the process group running on the first processor core, the memory operations of the process group on volatile and non-volatile memory are reduced accordingly. The total memory bandwidth used by the process group for volatile and non-volatile memory is also reduced, which indirectly reduces the memory bandwidth of non-volatile memory used by the process group, thus limiting the memory bandwidth of non-volatile memory to an arbitrary value.

[0093] In some embodiments, the first processor core and the second processor core belong to one or more NUMA nodes in a NUMA system. It is understood that the first processor core and the second processor core may belong to the same NUMA node in the NUMA system, or the first processor core and the second processor core may belong to different NUMA nodes in the NUMA system.

[0094] Typically, a NUMA system consists of multiple nodes, and each node contains multiple processor cores. A processor contains multiple physical processor cores. Each physical processor core can also be divided into two logical processor cores. The logical processor cores in a physical processor can be divided into multiple NUMA nodes (or simply nodes).

[0095] It is worth noting that the first processor core can be either a physical processor core or a logical processor core. If the first processor core is a physical processor core, it contains multiple logical processor cores. The first processor core and the second processor core can be cores in the same processor or cores in different processors.

[0096] For example, such as Figure 5As shown, the processor contains 8 processor cores, which can be either physical or logical processor cores. These 8 cores are divided into 2 nodes. Assuming processor core 1 runs a process group, processor core 1 can migrate a process from the process group from processor core 1 to processor core 2. Alternatively, processor core 1 can migrate a process from the process group from processor core 1 to processor core 5.

[0097] In the third possible implementation, the first processor core adjusts the process group's first time slice to a second time slice, where the first time slice is longer than the second time slice. Both the first and second time slices represent the duration the process group occupies the first processor core. The first processor core can call the file system interface to adjust the duration the process group occupies the first processor core.

[0098] By reducing the time allocated to the first processor core to run processes in the process group, the time spent running processes in the process group on the first processor core is shortened. Consequently, the process group's memory operations on volatile and non-volatile memory are reduced, and the total memory bandwidth used by the process group for volatile and non-volatile memory is also reduced. Indirectly, the memory bandwidth used by the process group for non-volatile memory is also reduced, thus limiting the memory bandwidth of non-volatile memory to an arbitrary value.

[0099] The first processor core strengthens or relaxes the restrictions on the process group based on the amount of non-volatile memory bandwidth used by the process group in the i-th preset period and the non-volatile memory bandwidth threshold, thereby allowing the process group to use less or more non-volatile memory bandwidth resources in the i+1 preset period.

[0100] Therefore, by controlling the memory bandwidth used by process groups to access volatile memory, the amount of memory bandwidth used by process groups to access non-volatile memory is indirectly limited. This avoids the situation where excessive use of non-volatile memory bandwidth by process groups, containers, or virtual machines prevents other process groups, containers, or virtual machines from accessing non-volatile memory, thus solving the problem of performance degradation or even interruption caused by the spread of adjacent interference faults.

[0101] In the above embodiments, the first processor core selects one of three possible implementations to limit the memory bandwidth of the non-volatile memory used by the process group. However, after limiting the memory bandwidth of the non-volatile memory used by the process group, the memory bandwidth size of the non-volatile memory may still be greater than or equal to the non-volatile memory bandwidth threshold. In this case, the first processor core can also dynamically limit the memory bandwidth of the non-volatile memory, such as... Figure 6 As shown, this embodiment also provides a method for dynamically limiting memory bandwidth.

[0102] S601, The first processor core obtains the first memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0103] S602, the first processor core determines whether the first memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0104] If the first memory bandwidth used by the process group to access non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, execute S603. If the first memory bandwidth used by the process group to access non-volatile memory is less than the non-volatile memory bandwidth threshold, execute S604.

[0105] S603, The first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold. Execute S604.

[0106] S604, the first processor core obtains the second memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0107] S605, the first processor core determines whether the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0108] If the second memory bandwidth used by the process group to access non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, execute S606. If the second memory bandwidth used by the process group to access non-volatile memory is less than the non-volatile memory bandwidth threshold, execute S607.

[0109] Optionally, if the first processor core adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold, and the second memory bandwidth used by the process group to access non-volatile memory is less than the non-volatile memory bandwidth threshold, the first processor core can further adjust the second volatile memory bandwidth threshold of the process group back to the first volatile memory bandwidth threshold according to the adjustment step size. For example, when business demands increase, the first processor core can further adjust the second volatile memory bandwidth threshold of the process group back to the first volatile memory bandwidth threshold according to the adjustment step size.

[0110] S606, The first processor core migrates the processes contained in the process group from the first processor core running the process group to the second processor core. Execute S607.

[0111] S607, the first processor core obtains the third memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0112] S608, the first processor core determines whether the size of the third memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

[0113] If the third memory bandwidth used by the process group to access non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, execute S609. If the third memory bandwidth used by the process group to access non-volatile memory is less than the non-volatile memory bandwidth threshold, execute S610.

[0114] Optionally, if after the first processor core migrates the processes contained in the process group from the first processor core running the process group to the second processor core, the third memory bandwidth used by the process group to access non-volatile memory is less than the non-volatile memory bandwidth threshold, the first processor core may also migrate the processes contained in the process group from the second processor core to the first processor core.

[0115] S609, The first processor core adjusts the first time slice of the process group to the second time slice. Execute S610.

[0116] The specific method by which the first processor core obtains the memory bandwidth (including the first, second, and third memory bandwidths) used by the process group to access non-volatile memory can be found in the detailed explanations of S201 and S202, and will not be repeated here. A detailed explanation of S603 can be found in the explanation of the first possible implementation described above. A detailed explanation of S606 can be found in the explanation of the second possible implementation described above. A detailed explanation of S609 can be found in the explanation of the third possible implementation described above.

[0117] It should be noted that after limiting the memory bandwidth of non-volatile memory used by the process group using one of the three possible implementation methods, the first processor core periodically monitors the memory bandwidth size of the non-volatile memory used by the process group. The first processor core can obtain the memory bandwidth size of non-volatile memory within adjacent preset periods, or within non-adjacent preset periods. For example, the first processor core obtains the first memory bandwidth size used by the process group to access non-volatile memory within the i-th preset period, the first processor core can obtain the second memory bandwidth size used by the process group to access non-volatile memory within the (i+1)-th preset period, and the first processor core can also obtain the second memory bandwidth size used by the process group to access non-volatile memory within the (i+2)-th preset period. i is an integer. The number of periods in which the first processor obtains the memory bandwidth size of non-volatile memory is not limited.

[0118] In the above embodiments, the first processor core dynamically limits the memory bandwidth of non-volatile memory. After limiting the memory bandwidth of non-volatile memory, if the memory bandwidth of non-volatile memory is less than the non-volatile memory bandwidth threshold, the memory bandwidth of the process group can be increased, that is, the limitation on the memory bandwidth of non-volatile memory can be lifted, so that the process group has sufficient available resources. Figure 7 As shown, this embodiment also provides a method for dynamically limiting memory bandwidth.

[0119] S610, the first processor core obtains the fourth memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0120] S611, The first processor core determines that the fourth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold. Execute S612.

[0121] S612, The first processor core adjusts the second time slice of the process group to the first time slice. Execute S613.

[0122] The first processor core adjusts the process group's second time slice to its first time slice, thus increasing the duration the process group occupies the processor core. This leads to increased memory operations by the process group on both volatile and non-volatile memory, increasing the total memory bandwidth used by the process group. Indirectly, this also increases the bandwidth of non-volatile memory used by the process group, ensuring sufficient available resources for the process group. The specific adjustment method is the reverse of adjusting the process group's first time slice to its second time slice; for details, please refer to the explanation of the third possible implementation method above.

[0123] S613, the first processor core obtains the fifth memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0124] S614. The first processor core determines that the fifth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold. Execute S615.

[0125] S615, The first processor core migrates the processes contained in the process group from the second processor core to the first processor core. Execute S616.

[0126] Understandably, the processes migrating from the second processor core to the first processor core are processes included in the process group that migrates from the first processor core to the second processor core. The specific migration method can be found in the detailed explanation of the second possible implementation above. Because the number of processes included in the process group running on the processor core increases, the memory operations of the process group on volatile and non-volatile memory increase accordingly. The total memory bandwidth used by the process group for both volatile and non-volatile memory also increases, indirectly increasing the memory bandwidth of non-volatile memory used by the process group, thus ensuring sufficient available resources for the process group.

[0127] S616, the first processor core obtains the sixth memory bandwidth size used by the process group to access non-volatile memory within a preset period.

[0128] S617. The first processor core determines that the sixth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold. Execute S618.

[0129] S618, the first processor core adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold. The first processor core continues to monitor the memory bandwidth used by the process group to access non-volatile memory within a preset period. Because the maximum value of the volatile memory bandwidth used by the process group is increased, the total memory bandwidth of volatile and non-volatile memory used by the process group also increases, indirectly increasing the memory bandwidth of non-volatile memory used by the process group, ensuring sufficient available resources for the process group. The first processor core can increase the volatile memory bandwidth threshold to the first volatile memory bandwidth threshold according to the adjustment step size. The method of increasing the volatile memory bandwidth threshold according to the adjustment step size is the reverse process of decreasing the volatile memory bandwidth threshold; the specific method of adjusting the volatile memory bandwidth threshold can be referred to the detailed description of the first possible implementation method above.

[0130] The specific method by which the first processor core obtains the memory bandwidth size (including the fourth, fifth, and sixth memory bandwidth sizes) used by the process group to access non-volatile memory can be found in the detailed explanations in S201 and S202, and will not be repeated here.

[0131] For example, such as Figure 8 As shown in (a), in user mode, the system administrator configures process groups, sets non-volatile memory bandwidth thresholds, and sets volatile memory bandwidth thresholds through different interfaces in the file system. For example, the system administrator configures process groups through the first file system interface. The system administrator sets the non-volatile memory bandwidth threshold through the second file system interface. The system administrator sets the first volatile memory bandwidth threshold through the third file system interface.

[0132] The first processor core uses MBM technology to view memory management information in the kernel, obtaining the memory bandwidth used by process groups to access volatile memory within a preset period, and collecting memory operations on system memory through the file system's read / write interface and other memory access operations. The monitoring module in the first processor core calculates the memory bandwidth used by process groups to access non-volatile memory based on the memory bandwidth and statistical memory operations. If the non-volatile memory bandwidth is greater than or equal to a non-volatile memory bandwidth threshold, the limiting module in the first processor core sets a memory bandwidth limit for the process group using any one of the following methods: adjusting the volatile memory bandwidth threshold, migrating processes, and adjusting the time slice occupied by the process group on the first processor core.

[0133] Assume that the non-volatile memory bandwidth threshold B2’ is 5 GB / s. If the non-volatile memory bandwidth B2 used by the process group is 3 GB / s, at this time, the non-volatile memory bandwidth of 3 GB / s used by the process group is lower than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 3 GB / s < B2’ = 5 GB / s, and the non-volatile memory bandwidth used by the process group is not restricted.

[0134] If the non-volatile memory bandwidth used by the process group is 15 GB / s, at this time, the non-volatile memory bandwidth of 15 GB / s used by the process group is greater than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 15 GB / s > B2’ = 5 GB / s. As Figure 8 shown in (b) of, the first processor core adjusts the volatile memory bandwidth threshold B1’, that is, adjusts the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold.

[0135] After adjusting the volatile memory bandwidth threshold (maximum limit), the non-volatile memory bandwidth used by the process group is 12 GB / s. The non-volatile memory bandwidth of 12 GB / s used by the process group is greater than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 12 GB / s > B2’ = 5 GB / s, and the first processor core migrates the processes of the process group, that is, migrates the processes included in the process group from the first processor core running the process group to the second processor core.

[0136] After migrating the processes, the non-volatile memory bandwidth used by the process group is 6 GB / s. The non-volatile memory bandwidth of 6 GB / s used by the process group is greater than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 6 GB / s > B2’ = 5 GB / s, and the first processor core adjusts the duration of the process group occupying the first processor core, that is, adjusts the first time slice of the process group to the second time slice. For example, the first time slice is the duration of a preset period. The second time slice is 83% of the duration of the preset period.

[0137] After adjusting the duration of the process group occupying the first processor core (maximum limit), the non-volatile memory bandwidth used by the process group is 1 GB / s. The non-volatile memory bandwidth of 1 GB / s used by the process group is less than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 1 GB / s < B2’ = 5 GB / s. The first processor core adjusts the duration of the process group occupying the first processor core, that is, adjusts the second time slice of the process group to the first time slice.

[0138] After adjusting the duration for which the process group occupies the first processor core, the non-volatile memory bandwidth used by the process group is 2 GB / s. The non-volatile memory bandwidth of 2 GB / s used by the process group is less than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 2 GB / s < B2' = 5 GB / s. The first processor core migrates the processes of the process group, that is, migrates the processes included in the process group from the second processor core running the process group to the first processor core.

[0139] After migrating the processes, the non-volatile memory bandwidth used by the process group is 3 GB / s. The non-volatile memory bandwidth of 3 GB / s used by the process group is less than the non-volatile memory bandwidth threshold of 5 GB / s, that is, B2 = 3 GB / s < B2' = 5 GB / s. The first processor core adjusts the volatile memory bandwidth threshold, that is, adjusts the second volatile memory bandwidth threshold of the process group to the first volatile memory bandwidth threshold.

[0140] It can be understood that, in order to implement the functions in the above embodiments, the server includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and method steps of each example described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application scenario and design constraint conditions of the technical solution.

[0141] As described above in combination with Figures 1 to 8 , the method for monitoring memory bandwidth and the method for restricting memory bandwidth provided according to this embodiment are described in detail. Next, the device for monitoring memory bandwidth, the device for restricting memory bandwidth, and the server provided according to this embodiment will be described in combination with Figures 9 to 11 .

[0142] Figure 9 FIG. is a schematic structural diagram of a possible device for monitoring memory bandwidth provided in this embodiment. These devices for monitoring memory bandwidth can be used to implement the functions of the processor core in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments. In this embodiment, the device for monitoring memory bandwidth can be the processor core 0 as shown in Figure 1 , or can also be a module (such as a chip) applied to the server.

[0143] As shown in Figure 9 , the device 900 for monitoring memory bandwidth includes an acquisition unit 910, a monitoring unit 920, and a restriction unit 930. The device 900 for monitoring memory bandwidth is used to implement the functions of the first processor core in the above Figure 2 , Figure 3 or Figure 4 method embodiments.

[0144] When the device 900 for monitoring memory bandwidth is used to implement Figure 2 In the method embodiment shown, the function of the first processor core is as follows: the acquisition unit 910 is used to implement the function executed by the first processor core in S201; the monitoring unit 920 is used to implement the function executed by the first processor core in S202.

[0145] When the device 900 for monitoring memory bandwidth is used to implement Figure 3 In the method embodiment shown, the function of the first processor core is as follows: the acquisition unit 910 is used to implement the function executed by the first processor core in S201; the monitoring unit 920 is used to implement the function executed by the first processor core in S2021 and S2022.

[0146] When the device 900 for monitoring memory bandwidth is used to implement Figure 4 In the method embodiment shown, the functions of the first processor core are as follows: the acquisition unit 910 is used to implement the functions executed by the first processor core in S201; the monitoring unit 920 is used to implement the functions executed by the first processor core in S202; and the restriction unit 930 is used to implement the functions executed by the first processor core in S401, S402 and S403.

[0147] For a more detailed description of the acquisition unit 910, monitoring unit 920, and restriction unit 930 mentioned above, please refer to [link / reference needed]. Figure 2 , Figure 3 or Figure 4 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0148] Figure 10 This is a schematic diagram illustrating the structure of a possible memory bandwidth limiting device provided in this embodiment. These memory bandwidth limiting devices can be used to implement the functionality of the processor core in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments. In this embodiment, the memory bandwidth limiting device can be as follows: Figure 1 The processor core 0 shown can also be a module (such as a chip) used in servers.

[0149] like Figure 10 As shown, the memory bandwidth limiting device 1000 includes an acquisition unit 1010 and a limiting unit 1020. The memory bandwidth limiting device 1000 is used to implement the above-described... Figure 6 or Figure 7 The method embodiment shown illustrates the function of the first processor core.

[0150] When the memory bandwidth limiting device 1000 is used to implement Figure 6In the method embodiment shown, the function of the first processor core is as follows: the acquisition unit 1010 is used to implement the functions executed by the first processor core in S601, S604, S607 and S610; the restriction unit 1020 is used to implement the functions executed by the first processor core in S602, S603, S605, S606, S608 and S609.

[0151] When the memory bandwidth limiting device 1000 is used to implement Figure 7 In the method embodiment shown, the function of the first processor core is as follows: the acquisition unit 1010 is used to implement the functions executed by the first processor core in S610, S613 and S616; the restriction unit 1020 is used to implement the functions executed by the first processor core in S611, S612, S614, S615, S617 and S618.

[0152] For a more detailed description of the aforementioned acquisition unit 1010 and restriction unit 1020, please refer to [the relevant documentation]. Figure 6 or Figure 7 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0153] It is understood that the processor in this embodiment can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0154] The processor may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present application.

[0155] Figure 11This is a schematic diagram of the structure of a server 1100 provided in this embodiment. As shown in the figure, the server 1100 includes a processor 1110, a bus 1120, a communication interface 1150, main memory 1130, and a memory 1140.

[0156] It should be understood that in this embodiment, the processor 1110 may be a central processing unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0157] The communication interface 1150 is used to enable communication between the server 1100 and external devices or components.

[0158] Bus 1120 may include a pathway for transmitting information between the aforementioned components (such as processor 1110, main memory 1130, and memory 1140). In addition to a data bus, bus 1120 may also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus 1120 in the figure.

[0159] As an example, server 1100 may include multiple processors. A processor may be a multi-core (multi-CPU) processor. Here, "processor" can refer to one or more devices, circuits, and / or computing units used to process data (e.g., computer program instructions). Processor 1110 can monitor the memory bandwidth used by a running process group to access volatile memory within a preset period, and statistically analyze the memory operations performed by the process group within the preset period. Based on the memory bandwidth and the statistically analyzed memory operations, it calculates the memory bandwidth used by the process group to access non-volatile memory. If the memory bandwidth of non-volatile memory is greater than or equal to a non-volatile memory bandwidth threshold, a memory bandwidth limit is set for the process group. The specific process of monitoring the memory bandwidth of non-volatile memory and setting the memory bandwidth limit for the process group can be directly obtained from the relevant descriptions in the above method embodiments, and will not be elaborated here.

[0160] It is worth noting that, Figure 11Taking server 1100 as an example, which includes one processor 1110 and one main memory 1130, the processor 1110 and the main memory 1130 are used to indicate a type of device or equipment. In specific embodiments, the number of each type of device or equipment can be determined according to business needs.

[0161] The storage device 1140 can be used to store relevant information in a cloud environment, such as a disk, like a mechanical hard drive or a solid-state drive.

[0162] The server 1100 described above can be a general-purpose device or a special-purpose device. For example, the server 1100 can be an x86 or ARM-based server, or it can be other special-purpose servers, such as a policy control and charging (PCC) server. This application does not limit the type of server 1100.

[0163] It should be understood that the server 1100 according to this embodiment can correspond to the device 900 for monitoring memory bandwidth and the device 1000 for limiting memory bandwidth in this embodiment, and can correspond to the execution according to Figures 2 to 4 ,as well as Figure 6 and Figure 7 The corresponding subject in any of the methods, and the above and other operations and / or functions of each module in the device are respectively for the purpose of implementing Figures 2 to 4 ,as well as Figure 6 and Figure 7 For the sake of brevity, the corresponding processes of each method in the code will not be elaborated here.

[0164] This embodiment also provides a processor, the structure of which is as follows: Figure 11 As shown, it includes multiple processor cores for implementing, such as Figures 2 to 4 ,as well as Figure 6 and Figure 7 To avoid repetition, the operational steps of the method will not be described again here.

[0165] The method steps in this embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a network device or terminal device. Of course, the processor and storage medium can also exist as discrete components in the network device or terminal device.

[0166] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for monitoring memory bandwidth, characterized in that, include: The memory bandwidth used by the process group to access volatile memory within a preset period is obtained, and the memory addresses accessed by the memory operations performed by the process group within the preset period are counted. The memory operations include non-volatile memory operations and volatile memory operations. The process group includes at least one process. The amount of non-volatile memory accessed by the process group and the proportion of volatile memory accessed by the process group are determined based on the memory addresses accessed by the memory operations. The first memory bandwidth used by the process group to access the non-volatile memory is calculated based on the memory bandwidth size and the ratio.

2. The method according to claim 1, characterized in that, Determining the ratio of the amount of non-volatile memory accessed by the process group to the amount of volatile memory accessed by the process group based on the memory addresses accessed by the memory operations includes: The memory size and type of the memory operation are determined based on the memory address accessed by the memory operation. The memory type includes volatile memory and non-volatile memory. The memory size includes the memory size of the process group accessing the volatile memory and the memory size of the process group accessing the non-volatile memory. The proportion of the process group's access to the non-volatile memory and the proportion of the process group's access to the volatile memory are determined based on the memory size and memory type of the memory operation.

3. The method according to claim 1, characterized in that, The memory operations performed within the preset period are either all memory operations or partial memory operations.

4. The method according to any one of claims 1-3, characterized in that, The memory operations are memory read and write operations.

5. The method according to any one of claims 1-3, characterized in that, After calculating the first memory bandwidth size used by the process group to access the non-volatile memory based on the memory bandwidth size and the ratio, the method further includes: If the first memory bandwidth size is greater than or equal to the non-volatile memory bandwidth threshold, a memory bandwidth limit is set for the process group, wherein the non-volatile memory bandwidth threshold is the maximum memory bandwidth allowed for the process group to access the non-volatile memory.

6. The method according to claim 5, characterized in that, Setting the memory bandwidth limit for the process group includes one or more of the following: The first volatile memory bandwidth threshold of the process group is adjusted to the second volatile memory bandwidth threshold. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the maximum memory bandwidth that the process group is allowed to use to access the volatile memory. The processes contained in the process group are migrated from the first processor core running the process group to the second processor core; The first time slice of the process group is adjusted to the second time slice, where the first time slice is longer than the second time slice, and both the first time slice and the second time slice represent the duration during which the process group occupies the first processor core.

7. The method according to claim 6, characterized in that, Migrating the processes contained in the process group from the first processor core running the process group to the second processor core includes: After adjusting the first volatile memory bandwidth threshold of the process group to the second volatile memory bandwidth threshold, when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the processes contained in the process group are migrated from the first processor core running the process group to the second processor core.

8. The method according to claim 7, characterized in that, Adjusting the first time slice of the process group to the second time slice includes: After migrating the processes contained in the process group from the first processor core running the process group to the second processor core, when the third memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice.

9. The method according to claim 8, characterized in that, After adjusting the first time slice of the process group to the second time slice, the method further includes: When the fourth memory bandwidth of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the second time slice of the process group is adjusted to the first time slice.

10. The method according to claim 9, characterized in that, After adjusting the second time slice of the process group to the first time slice, the method further includes: When the fifth memory bandwidth of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the processes contained in the process group are migrated from the second processor core to the first processor core.

11. The method according to claim 10, characterized in that, After migrating the processes contained in the process group from the second processor core to the first processor core, the method further includes: When the sixth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the second volatile memory bandwidth threshold of the process group is adjusted to the first volatile memory bandwidth threshold.

12. The method according to any one of claims 7-11, characterized in that, The non-volatile memory bandwidth threshold is set through the first file system interface.

13. The method according to any one of claims 6-11, characterized in that, The first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set through the second file system interface.

14. The method according to any one of claims 6-11, characterized in that, The first and second processor cores belong to one or more NUMA nodes in a non-uniform memory access NUMA system.

15. A method for limiting memory bandwidth, characterized in that, include: If the first memory bandwidth used by a process group to access non-volatile memory within a preset period is greater than or equal to a non-volatile memory bandwidth threshold, the first volatile memory bandwidth threshold of the process group is adjusted to a second volatile memory bandwidth threshold. The non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for the process group to access the non-volatile memory. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first and second volatile memory bandwidth thresholds refer to the maximum allowed memory bandwidth for the process group to access volatile memory. The process group includes at least one process. The first memory bandwidth is determined based on the memory bandwidth used by the process group to access the volatile memory within the preset period and the ratio of the number of times the process group accesses the non-volatile memory to the number of times the process group accesses the volatile memory. The ratio is determined based on the memory addresses accessed by the memory operations performed by the process group within the preset period. When the second memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the processes contained in the process group are migrated from the first processor core running the process group to the second processor core.

16. The method according to claim 15, characterized in that, After migrating the processes contained in the process group from the first processor core running the process group to the second processor core, the method further includes: When the third memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice. The first time slice is longer than the second time slice. Both the first time slice and the second time slice are the duration for which the process group occupies the first processor core.

17. The method according to claim 16, characterized in that, After adjusting the first time slice of the process group to the second time slice, the method further includes: When the fourth memory bandwidth of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the second time slice of the process group is adjusted to the first time slice.

18. The method according to claim 17, characterized in that, After adjusting the second time slice of the process group to the first time slice, the method further includes: When the fifth memory bandwidth of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the processes contained in the process group are migrated from the second processor core to the first processor core.

19. The method according to claim 18, characterized in that, After migrating the processes contained in the process group from the second processor core to the first processor core, the method further includes: When the sixth memory bandwidth size of the non-volatile memory is less than the non-volatile memory bandwidth threshold, the second volatile memory bandwidth threshold of the process group is adjusted to the first volatile memory bandwidth threshold.

20. The method according to any one of claims 15-19, characterized in that, The non-volatile memory bandwidth threshold is set through the first file system interface, and the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold are set through the second file system interface.

21. The method according to any one of claims 15-19, characterized in that, The first processor core and the second processor core belong to one or more NUMA nodes in a non-uniform memory access NUMA system.

22. A device for monitoring memory bandwidth, characterized in that, include: The acquisition unit is used to acquire the memory bandwidth used by the process group to access volatile memory within a preset period, and to count the memory addresses accessed by the memory operations performed by the process group within the preset period. The memory operations include non-volatile memory operations and volatile memory operations. The process group includes at least one process. The monitoring unit is used to determine the amount of non-volatile memory accessed by the process group and the proportion of volatile memory accessed by the process group based on the memory address accessed by the memory operation. The first memory bandwidth used by the process group to access the non-volatile memory is calculated based on the memory bandwidth size and the ratio.

23. The apparatus according to claim 22, characterized in that, The device also includes a limiting unit. The limiting unit is used to set a memory bandwidth limit for the process group if the first memory bandwidth size is greater than or equal to the non-volatile memory bandwidth threshold, wherein the non-volatile memory bandwidth threshold is the maximum memory bandwidth that the process group is allowed to use to access the non-volatile memory.

24. The apparatus according to claim 23, characterized in that, The limiting unit is specifically used to set the memory bandwidth limit for the process group, including one or more of the following: The first volatile memory bandwidth threshold of the process group is adjusted to the second volatile memory bandwidth threshold. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first volatile memory bandwidth threshold and the second volatile memory bandwidth threshold refer to the maximum memory bandwidth that the process group is allowed to use to access the volatile memory. The processes contained in the process group are migrated from the first processor core running the process group to the second processor core; The first time slice of the process group is adjusted to the second time slice, where the first time slice is longer than the second time slice, and both the first time slice and the second time slice represent the duration during which the process group occupies the first processor core.

25. A device for limiting memory bandwidth, characterized in that, include: A limiting unit is configured to adjust the first volatile memory bandwidth threshold of a process group to a second volatile memory bandwidth threshold if the first memory bandwidth used by the process group to access non-volatile memory within a preset period is greater than or equal to a non-volatile memory bandwidth threshold. The non-volatile memory bandwidth threshold is the maximum allowed memory bandwidth for the process group to access the non-volatile memory. The first volatile memory bandwidth threshold is greater than the second volatile memory bandwidth threshold. Both the first and second volatile memory bandwidth thresholds refer to the maximum allowed memory bandwidth for the process group to access volatile memory. The process group includes at least one process. The first memory bandwidth is determined based on the memory bandwidth used by the process group to access the volatile memory within the preset period and the ratio of the number of times the process group accesses non-volatile memory to the number of times the process group accesses volatile memory. This ratio is determined based on the memory addresses accessed by the memory operations performed by the process group within the preset period. The limiting unit is further configured to migrate the processes contained in the process group from the first processor core running the process group to the second processor core when the second memory bandwidth size of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold.

26. The apparatus according to claim 25, characterized in that, After the limiting unit migrates the processes contained in the process group from the first processor core running the process group to the second processor core, the limiting unit is further configured to: When the third memory bandwidth of the non-volatile memory is greater than or equal to the non-volatile memory bandwidth threshold, the first time slice of the process group is adjusted to the second time slice. The first time slice is longer than the second time slice. Both the first time slice and the second time slice are the duration for which the process group occupies the first processor core.

27. A server, characterized in that, The server includes a memory and a processor, the processor including multiple processor cores, and the memory for storing a set of computer instructions; when the processor cores execute the set of computer instructions, they implement the method of any one of claims 1 to 14.

28. A server, characterized in that, The server includes a memory and a processor, the memory being used to store a set of computer instructions; when the processor core executes the set of computer instructions, it implements the method of any one of claims 15 to 21.

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