A physical construction method suitable for meeting triple modular redundancy

Abstract

The present invention discloses a physical construction method suitable for meeting triple modular redundancy. In the layout stage, a customized design is adopted for the clock management unit. The three registers in the same group are effectively controlled through scripts during implementation. Since the existing triple modular registers increase the clock delay and have the characteristic of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, and the design efficiency is effectively accelerated. Finally, the triple modular clock phase difference check is completed by using the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly meets the design specifications. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to a physical construction method suitable for meeting triple modular redundancy. Background Art

[0002] With the rapid development of space technology, core electronic components are more and more widely used in the space environment. Various space radiation effects will have different degrees of impact on the reliability of components. Among them, the single event effect seriously affects the normal use of space electronic equipment. In order to reduce the impact of single event upsets on the reliability of devices, core chips must meet various anti-radiation indicators. With the progress of process technology, the single event effect has become more serious. The main problems in the physical design of triple modular redundancy under advanced processes are manifested in the following aspects:

[0003] 1. With the gradual progress of process technology, due to poor control of tools in the physical implementation of triple modular redundant circuits, the implementation effects of the three registers in the same group are not good, resulting in the failure to effectively solve the single event upset effect.

[0004] 2. With the gradual progress of the process, due to the increase in clock delay of triple modular registers, and at the same time, the delay differences of standard cells and interconnect lines are large under different process corners, the difficulty of timing convergence of triple modular registers increases, and it is very difficult to meet the timing convergence requirements by using traditional clock tree design.

[0005] 3. At present, there is no guiding basis for the delay check of the three clocks corresponding to the three-way registers. Summary of the Invention

[0006] The purpose of the present invention is to overcome the above deficiencies and provide a physical construction method suitable for meeting triple modular redundancy, which can ensure the effective improvement of the single event effect while ensuring that the triple modular design quickly reaches the design index.

[0007] To achieve the above purpose, the present invention includes the following steps:

[0008] S1, input the design file;

[0009] S2, place the clock management unit and the control unit in the center of the chip, and script to ensure that the three registers in the same group maintain equal distances, avoiding the single event hitting two or three signals simultaneously, which may cause the failure of triple modular redundancy protection and circuit flip.

[0010] S3, for the triple modular registers in the top-level clock tree synthesis, after the buffer unit of the triple modular registers, define three clocks respectively through the create_clock command to balance the three clocks, fix the delay unit of the triple modular registers, ensure the delay difference between the three clocks, and separately lay a common path from the clock origin to the delay unit of the triple modular registers;

[0011] In S4, adopt the strategy of clock tree first routing to route the clock lines and signal lines;

[0012] In S5, extract the resistors and capacitors from the layout information after physical synthesis, and backannotate the resistor and capacitor parameters to the process file;

[0013] In S6, calculate the delay of the actual circuit through the backannotated resistor and capacitor information, and check whether the timing meets the design convergence requirements;

[0014] In S7, adopt the clock length comparison method to judge whether the triple-mode clock meets the design requirements.

[0015] In S1, the input design files include netlist, library file, constraint file, and IO constraint file.

[0016] The specific method of S2 is as follows:

[0017] Set the directions and types of the three registers in the same group to be consistent, so that the three registers form a triangle. The moving position in the X direction can be freely determined, and the moving position in the Y direction is an integer multiple of the height of the register itself. This parameter is saved in the script. The three registers form a triple-mode register. Fix all the triple-mode registers, move away other standard cells, and finally place the overlapping triple-mode registers reasonably.

[0018] Register 1 is moved to the lower right of Register 0, and Register 2 is moved to the directly below of Register 0. Register 0, Register 1, and Register 2 form a triangle and jointly form a triple-mode register.

[0019] In S3, fix the clock management unit, and set the registers inside the clock management unit as clock exclusion pins.

[0020] The three-way registers are for a unified clock source, which is completed through the create_generate_clock command. When the triple-mode clock loads are different, there will be clock skew between the clocks. Use the command clock_opt - inter_clock_balance for clock equalization.

[0021] In S4, the strategy of clock tree first routing includes the following steps:

[0022] After clock tree synthesis, start to pay attention to the setup time, determine the relationship between the setup time and the clock skew, and determine that the result after clock tree synthesis and the timing result after placement only differ in clock skew.

[0023] In S7, the specific method of the clock length comparison method is as follows:

[0024] The clock path from the clock port to the clock terminal of the DFF is set as the clock path. Assume that T0, T1, and T2 are the three regions passing through the triple modular redundancy circuit respectively. The longest and shortest clock path lengths of the three regions are recorded as S0_max, S0_min, S1_max, S1_min, S2_max, and S2_min respectively;

[0025] Judge whether the shortest clock path of the T1 region minus the longest clock path of the T0 region is greater than or equal to the pulse width of the SEU flip;

[0026] Judge whether the shortest clock path of the T2 region minus the longest clock path of the T1 region is greater than or equal to the pulse width of the SEU flip.

[0027] Compared with the prior art, the present invention adopts a customized design for the clock management unit in the layout stage. The three registers in the same group are effectively controlled through scripts in the implementation. Since the existing triple modular registers increase the clock delay and have the characteristics of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, the design efficiency is effectively accelerated, and finally the triple modular clock phase difference check is completed by the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly reaches the design index. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions. Description of the Drawings

[0028] Figure 1 It is the constraint schematic diagram for the layout, clock tree optimization, and routing stages;

[0029] Figure 2 It is the constraint schematic diagram for the clock tree synthesis stage;

[0030] Figure 3 It is the schematic diagram of the clock length comparison method;

[0031] Figure 4 It is the schematic diagram of the script controlling the positions of the triple modular registers;

[0032] Figure 5 It is the schematic diagram of the clock laying the common path. Detailed Embodiment

[0033] The present invention will be further described below with reference to the drawings.

[0034] Refer to Figure 1 , the present invention includes the following steps:

[0035] S1, input the design files, and the input design files include the netlist, library files, constraint files, and IO constraint files;

[0036] S2. Place the clock management unit and the control unit at the center of the chip. Script to ensure equal distances between three registers in the same group, preventing a single particle from hitting two or three signals simultaneously and causing the failure of triple modular redundancy protection, which may lead to circuit flipping.

[0037] See Figure 4 , Set the directions and types of the three registers in the same group to be consistent, forming a triangle with the three registers. The moving position in the X direction can be freely determined, and the moving position in the Y direction is an integer multiple of the height of the register itself. This parameter is saved in the script. The three registers form a triple modular register. Fix all triple modular registers, remove other standard cells, and finally place the overlapping triple modular registers rationally. Register 1 is moved to the lower right of register 0, and register 2 is moved directly below register 0. Registers 0, 1, and 2 form a triangle and jointly form a triple modular register. Fix the clock management unit and set the registers inside the clock management unit as clock exclusion pins. The three-way register uses a unified clock source, and the layout is completed through the create_generate_clock command constraint.

[0038] S3. See Figure 2 and Figure 5 , The triple modular register in the top-level clock tree synthesis is after the buffer unit of the triple modular register. Through the create_clock command, define three clocks respectively to balance the three clocks. Fix the delay unit of the triple modular register to ensure the delay difference between the three clocks. A common path is laid separately from the clock origin to the delay unit of the triple modular register; when the triple modular clock loads are different, there will be clock skew between the clocks, and the clock_opt - inter_clock_balance command is used for clock equalization.

[0039] S4. Adopt the strategy of clock tree first routing to route the clock lines and signal lines; the strategy of clock tree first routing includes the following steps:

[0040] After clock tree synthesis, start to focus on the setup time, determine the relationship between the setup time and the clock skew, and determine that the result after clock tree synthesis and the timing result after layout only differ in clock skew.

[0041] S5. Extract the resistance and capacitance of the layout information after physical synthesis and backannotate the resistance and capacitance parameters to the process file;

[0042] S6. Calculate the delay of the actual circuit based on the backannotated resistance and capacitance information and check whether the timing meets the design convergence requirements;

[0043] S7. See Figure 3 , Use the clock length comparison method to determine whether the triple modular clock meets the design requirements.

[0044] The specific method of the clock length comparison method is as follows:

[0045] The clock end from the clock port to the DFF is set as the clock path. Assume that T0, T1 and T2 are three areas passing through the triple-module redundant circuit respectively. The longest and shortest time of the clock path lengths in the three areas are recorded as S0_max, S0_min, S1_max, S1_min, S2_max and S2_min respectively.

[0046] Determine whether the shortest clock path in the T1 region minus the longest clock path in the T0 region is greater than or equal to the pulse width of the SEU flip;

[0047] Determine whether the shortest clock path in the T2 region minus the longest clock path in the T1 region is greater than or equal to the pulse width of the SEU flip.

[0048] Example:

[0049] The process of designing an example chip by triple-module redundancy of the present invention is as follows:

[0050] 1) Input design files

[0051] 2) Set constraints related to the three-mode design in the layout, that is, the three registers use the same clock, execute the timing constraints of the create_generate_clock command from the clock management unit port, and adopt a timing-driven layout method. The clock and control unit are placed in the center of the entire chip, and the script is used to keep the three registers at an equal distance to prevent a single particle from hitting two or three signals at the same time, causing the three-mode redundancy protection to fail and causing the circuit to flip. The specific method is as follows: Set the directions of the three registers in the same group to be consistent, and set the types of the three registers in the same group to the same type. Move register 1 to the lower right of register 0, and register 2 to the bottom of register 0 to form a triangle. The movement position in the X direction is freely determined, and the movement position in the Y direction is an integer multiple of the height of the register itself, which is also reflected in the script. The three parameters that need to be entered in the script are: the row to which register 1 moves down, the row to which register 2 moves down, and the distance to which register 1 moves to the right. It is necessary to rationalize all units while meeting the spacing requirements as much as possible, and the positions of the three registers in the same group cannot be too far apart, otherwise it will affect the timing. First, fix all the three-mode registers, move other standard units, and finally rationalize the placement of overlapping three-mode registers. The above operations can not only increase the distance between registers in the same group, but also bring other related key units closer to a certain extent to meet subsequent timing requirements.

[0052] set_attribute[get_flat_cells{* / D0_register* / D1_register* / D2_register}]is_fixed true

[0053] legalize_placement-incr

[0054] set_attribute[get_flat_cells{* / D0_register* / D1_register* / D2_register}]is_fixed false

[0055] set_attribute[get_flat_cells{* / D0_register* / D1_register* / D2_register}]is_soft_placed true

[0056] legalize_placement-incr

[0057] 3) When performing clock tree synthesis, three-way clocks are adopted for the three registers respectively, and the three-way clocks are generated from the ports of the clock management unit through the create_clock command. The clock management unit is "fixed", and the registers inside the clock management unit are set as clock exclusion pins. The three-way clocks are generated from the ports of the clock management unit through the create_clock command to independently complete the clock tree synthesis. A separate common path is laid between the clock origin and the triple modular redundancy (TMR) buffer unit. The general practice for the top-level clock TMR is to define three clocks respectively after the TMR buffer unit, balance the three clocks, fix the delay units of the TMR registers, and ensure the delay difference between the three clocks. Finally, the clock from the clock origin to this section is laid. For the module clock TMR, the entire path from the clock origin to the module boundary is laid as a common path, and its length is guaranteed. Only one clock is set at the module clock port for the module clock TMR, and at the same time, the TMR delay units are fixed, so that the clock must be divided into three paths to reach the three registers, and the paths under the same clock will balance themselves.

[0058] 4) Perform clock tree optimization using the same constraints as in the placement stage.

[0059] 5) Route the clock lines and signal lines. To reduce the line delay and the impact of signal crosstalk, the principle of making the clock lines twice as wide and twice as spaced as the general signal lines is adopted, and the strategy of giving priority to routing the clock tree is taken.

[0060] 6) Extract the resistance and capacitance of the physical layout information after physical synthesis, and back-annotate the resistance and capacitance parameters to the process file.

[0061] 7) Calculate the delay of the actual circuit based on the resistor-capacitor information of the anti-marking, and check whether the timing meets the design convergence requirements.

[0062] 8) Use the clock length comparison method to determine whether the triple-modular clock meets the design requirements. Set the clock path from the clock port to the register clock terminal as the clock path. Assume that T0, T1, and T2 are the three regions passing through the triple-modular redundancy circuit respectively. The longest and shortest times of the clock paths in the three regions are recorded as S0, S1, and S2 respectively, such that the shortest clock path in the T1 region minus the longest clock path in the T0 region is greater than or equal to the pulse width of the SEU flip, that is, S1_min - S0_max ≥ the pulse width of the SEU flip; the shortest clock path in the T2 region minus the longest clock path in the T1 region is greater than or equal to the pulse width of the SEU flip, that is, S2_min - S1_max ≥ the pulse width of the SEU flip.

[0063] 9) End and exit.

[0064] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A physical construction method suitable for meeting triple modular redundancy, characterized in that, It includes the following steps: S1. Input the design file; S2. Place the clock management unit and the control unit at the center of the chip, and script to ensure equal distances between three registers in the same group, avoiding single-event upset from simultaneously hitting two or three signals and causing the failure of triple modular redundancy protection and circuit flip; S3. The triple modular register in the top-level clock tree synthesis is after the buffer unit of the triple modular register. Define three clocks respectively through the create_clock command to balance the three clocks, fix the delay unit of the triple modular register, ensure the delay difference between the three clocks, and lay a separate common path from the clock origin to the delay unit of the triple modular register; S4. Adopt the strategy of clock tree first routing to route the clock lines and signal lines; S5. Extract the resistance and capacitance of the layout information after physical synthesis, and back-annotate the resistance and capacitance parameters to the process file; S6. Calculate the delay of the actual circuit through the back-annotated resistance and capacitance information, and check whether the timing meets the design convergence requirements; S7. Use the clock length comparison method to determine whether the triple modular clock meets the design requirements.

2. A physical construction method suitable for meeting triple modular redundancy according to claim 1, characterized in that In S1, the input design file includes a netlist, a library file, a constraint file, and an IO constraint file.

3. A physical construction method applicable to meet triple modular redundancy according to claim 1, characterized in that, The specific method of S2 is as follows: Set the directions and types of three registers in the same group to be consistent, form a triangle with the three registers, freely determine the moving position in the X direction, and the moving position in the Y direction is an integer multiple of the height of the register itself. This parameter is saved in the script. The three registers form a triple modular register, fix all the triple modular registers, move away other standard cells, and finally rationally place the overlapping triple modular registers.

4. A physical construction method applicable to meet triple modular redundancy according to claim 3, characterized in that, Move register 1 to the lower right of register 0, move register 2 to the directly below of register 0. Register 0, register 1, and register 2 form a triangle and jointly form a triple modular register.

5. A physical construction method applicable to meeting triple modular redundancy according to claim 1, characterized in that, In S3, fix the setting of the clock management unit, and set the registers inside the clock management unit as clock exclusion pins.

6. A physical construction method applicable to meet triple modular redundancy according to claim 1, characterized in that, The three-way register is a unified clock source, completed through the create_generate_clock command. When the triple modular clock loads are different, there will be clock skew between the clocks. Use the command clock_opt - inter_clock_balance for clock equalization.

7. A physical construction method applicable to meet triple modular redundancy according to claim 1, characterized in that, In S4, the strategy of clock tree first routing includes the following steps: Start to pay attention to the setup time after clock tree synthesis, determine the relationship between the setup time and the clock skew, and determine that the result after clock tree synthesis and the timing result after placement only differ in the clock skew.

8. A physical construction method applicable to meeting triple modular redundancy according to claim 1, characterized in that In S7, the specific method of the clock length comparison method is as follows: Set the clock path from the clock port to the clock terminal of the DFF. Assume that T0, T1, and T2 are respectively three regions passing through the triple modular redundancy circuit. Record the longest and shortest times of the clock path lengths in the three regions as S0_max, S0_min, S1_max, S1_min, S2_max, and S2_min; Judge whether the shortest clock path in the T1 region minus the longest clock path in the T0 region is greater than or equal to the pulse width of the SEU flip; Determine whether the shortest clock path in region T2 minus the longest clock path in region T1 is greater than or equal to the pulse width of the SEU flip.

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