Space solid-state storage SiP module based on anti-radiation SSD controller and read-write method thereof

Abstract

The application discloses a satellite solid-state storage SiP module based on an anti-radiation SSD controller and a reading and writing method thereof, and the SiP module comprises a storage control unit, a data cache unit, a data storage unit, a program storage unit, a power supply reference unit and a resistance-capacitance network; the storage control unit comprises an anti-radiation SSD controller, the anti-radiation SSD controller receives commands and related data sent by a host computer and performs calculation and processing, and outputs required data or states; the data cache unit is composed of multiple dynamic random memories; the data storage unit is composed of multiple NAND FLASH memories; the program storage unit is composed of a nonvolatile SPI FLASH memory; the power supply reference unit is composed of a power supply chip; and the resistance-capacitance network is used for guaranteeing signal and power supply integrity of the whole SiP module. The application can meet the demand of large capacity, low cost, low power consumption, miniaturization and light weight of the satellite-borne storage system.

Description

Technical Field

[0001] This invention belongs to the field of hybrid integrated circuit design, specifically relating to a satellite solid-state storage SiP module based on a radiation-resistant SSD controller and its read / write method. Background Technology

[0002] With the increasing variety of satellite payloads and the dramatic increase in the amount and bandwidth of onboard remote sensing data, real-time, reliable, high-speed, and high-capacity data storage systems have become a fundamental requirement for such satellite applications. Therefore, the size and weight of the storage system directly affect launch costs and the satellite's on-orbit operational lifespan.

[0003] Currently, most spaceborne storage systems employ FPGA-based control cores combined with SLC NAND flash memory as the storage medium. However, limited by the resource scale and clock speed of FPGAs, they struggle to meet the resource requirements for control and management of MLC and TLC NAND flash-based storage devices. Furthermore, the limited integration density of individual SLC NAND flash chips, coupled with the capacity demands of aerospace applications far exceeding the development of SLC NAND flash manufacturing processes, has resulted in increasingly bulky storage systems. In certain applications, the physical limitations of SLC NAND flash chip storage density and interface bandwidth prevent them from meeting specific needs. Additionally, the high cost and high power consumption associated with FPGA-based control cores contradict the development trend of low-cost, low-power, and lightweight satellite technology. Summary of the Invention

[0004] The purpose of this invention is to address the problems in the prior art by providing a satellite solid-state storage SiP module based on a radiation-resistant SSD controller and its read / write method. This module forms a solid-state memory that can be used in spaceborne storage systems within a micro-sized space, meeting the requirements of spaceborne storage systems for large capacity, low cost, low power consumption, miniaturization, and lightweight design.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A satellite solid-state storage SiP module based on a radiation-hardened SSD controller includes a storage control unit, a data cache unit, a data storage unit, a program storage unit, a power supply reference unit, and a resistor-capacitor network.

[0007] The storage control unit includes a radiation-resistant SSD controller, which receives commands and related data from the host, performs calculations and processing, and outputs the required data or status.

[0008] The data caching unit consists of multiple dynamic random access memory chips, which cache data to match the data transmission rate between the storage control unit and the data storage unit.

[0009] The data storage unit is composed of multiple NAND FLASH memory chips;

[0010] The program storage unit is composed of a non-volatile SPI FLASH memory, which is used to store the SSD controller read / write program and the NAND FLASH lifetime and reliability management scheduling algorithm;

[0011] The power supply reference unit is composed of a power supply chip and is used to provide a reference power supply to the dynamic random access memory of the data cache unit and the NAND FLASH memory of the data storage unit.

[0012] The aforementioned RC network, composed of connected resistors and capacitors, is used to ensure the signal and power integrity of the entire SiP module.

[0013] Preferably, the radiation-resistant SSD controller communicates directly with the host. The host sends write commands through an interface, and the radiation-resistant SSD controller receives the data sent by the host, caches the data in dynamic random access memory (DRAM), and when the cached data reaches a set threshold amount, the radiation-resistant SSD controller sends a request to write the cached data to NAND FLASH memory. When the host sends a read command, the radiation-resistant SSD controller obtains the address stored in NAND FLASH memory according to the host's needs, reads the corresponding data into DRAM, and finally returns the result to the host through the interface.

[0014] Preferably, the radiation-resistant SSD controller, multiple dynamic random access memory chips, multiple NAND flash memory chips, SPI flash memory chips, power supply chip, resistors and capacitors are integrated into a single package using a 3D three-dimensional structure.

[0015] Furthermore, the 3D structure places the radiation-resistant SSD controller, multiple dynamic random access memory chips, SPI FLASH memory, and power supply chip on one functional unit, and places the NAND FLASH memory on one or more functional units according to storage capacity requirements; the resistors and capacitors are distributed in each functional unit.

[0016] Furthermore, the multiple dynamic random access memory chips are distributed on the front and back of the functional unit, the NAND flash memory is distributed on the front and back of the functional unit, and signal lead-out pads are provided on the outer surface of the outermost functional unit.

[0017] Furthermore, the 3D stereo structure is designed for serial signal interfaces such that every n signals are accompanied by one ground signal, where 1 ≤ n ≤ 10; the 3D stereo structure is designed for parallel signal interfaces such that each parallel signal is accompanied by one ground signal on both the left and right sides.

[0018] Preferably, if a die in a NAND FLASH memory fails, the functionality of the space-based solid-state storage SiP module can be maintained by disabling the die select and updating the back-end organization of the radiation-hardened SSD controller.

[0019] Preferably, if a NAND FLASH memory is damaged, the channel containing that device is disabled and a backup channel is enabled.

[0020] Preferably, the radiation-resistant SSD controller is model LSoCAM2R402RH, the SPI FLASH memory is model JFM25FL032RH, the power supply chip is model RSW3301RH, the dynamic random access memory is model IS43DR16128C, and the NAND FLASH memory is model MT29F1T08CUCCBH8.

[0021] This invention also provides a method for reading and writing a satellite solid-state storage SiP module based on a radiation-hardened SSD controller:

[0022] The host sends a write command, and the radiation-resistant SSD controller receives the command and related data from the host. The radiation-resistant SSD controller caches the data in multiple dynamic random access memories and allocates an address for a NAND flash memory for the data. When the data reaches a set threshold, the radiation-resistant SSD controller writes the data into the corresponding NAND flash memory according to the address of the NAND flash memory.

[0023] The host sends a read command, the radiation-hardened SSD controller receives the command from the host, processes it internally, obtains the address stored in the NAND FLASH memory as needed, reads the corresponding data into the dynamic random access memory, and finally returns it to the host.

[0024] Compared with the prior art, the present invention has at least the following beneficial effects:

[0025] The storage control unit, data cache unit, data storage unit, program storage unit, power supply reference unit, and resistor-capacitor network can be integrated into a single package using SiP (System-in-Package) design technology. The spaceborne solid-state storage SiP module achieved by this invention increases storage capacity by no less than 50% within the same volume and reduces weight by more than 40%, effectively solving the problems of excessive cost and large size of current spaceborne storage systems. At the same time, this invention realizes a modular heterogeneous storage control system with higher application flexibility. It can adapt to the storage performance and capacity requirements of different applications through array configuration and can be configured according to the reliability level requirements of different satellites to obtain the best cost performance.

[0026] Furthermore, from a control implementation perspective, chip select backup can be employed. This allows the functionality of the spaceborne solid-state storage SiP module to remain unaffected by the failure of a single die when a physical failure occurs in a particular die of a NAND flash memory. This is achieved by disabling the chip select and updating the back-end organization of the radiation-hardened SSD controller. Additionally, if a NAND flash device is damaged, the channel containing that device can be disabled, and a backup channel can be activated. This multi-level redundancy backup strategy can address issues ranging from single data bit flips, unavailability of a physical block, physical damage to a NAND flash device, and irreparable damage to a channel. Compared to the primary / backup redundancy strategy of traditional spaceborne storage systems, this significantly reduces hardware costs while providing several levels of higher reliability. Attached Figure Description

[0027] Figure 1 Overall structural block diagram of the satellite solid-state storage SiP module according to an embodiment of the present invention;

[0028] Figure 2 Overall circuit schematic diagram of the satellite solid-state storage SiP module according to an embodiment of the present invention;

[0029] Figure 3 Block diagram of each functional unit of the satellite solid-state storage SiP module in this embodiment of the invention;

[0030] Figure 4 3D stereoscopic structure diagram of a satellite solid-state storage SiP module according to an embodiment of the present invention;

[0031] Figure 5 The schematic diagram of the high-speed serial-parallel signal design of the satellite solid-state storage SiP module in this embodiment of the invention. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0033] Please see Figure 1 This invention relates to a satellite-based solid-state storage (SiP) module based on a radiation-hardened SSD controller. It mainly includes a storage control unit, a data cache unit, a data storage unit, a program storage unit, a power supply reference unit, and a resistor-capacitor network. The program storage area contains a program storage unit, and the data cache area contains a data cache unit. The specific structure of each unit is as follows:

[0034] The storage control unit includes a radiation-hardened SSD controller, which receives commands and related data from the host, performs calculations and processes them, and outputs the required data or status.

[0035] The data caching unit consists of multiple dynamic random access memory chips, which cache data to match the data transfer rate between the storage control unit and the data storage unit;

[0036] The data storage unit consists of multiple NAND FLASH memory chips;

[0037] The program storage unit consists of a non-volatile SPI FLASH memory, used to store the SSD controller read / write program and the NAND FLASH lifetime and reliability management scheduling algorithm;

[0038] The power supply reference unit is composed of a power supply chip and is used to provide reference power to the dynamic random access memory of the data cache unit and the NAND FLASH memory of the data storage unit.

[0039] An RC network, consisting of resistors and capacitors, is used to ensure the signal and power integrity of the entire SiP module.

[0040] Please see Figure 2 The radiation-hardened SSD controller communicates directly with the host. The host sends write commands through the interface, and the radiation-hardened SSD controller receives the data sent by the host, caches the data in dynamic random access memory (DRAM), and when the cached data reaches a set threshold, the radiation-hardened SSD controller sends a request to write the cached data to NAND FLASH memory. When the host sends a read command, the radiation-hardened SSD controller obtains the address stored in NAND FLASH memory according to the host's needs, reads the corresponding data into DRAM, and finally returns it to the host through the interface.

[0041] To achieve the design goals of miniaturization and lightweighting of spaceborne solid-state storage systems, this invention employs SiP (System-in-Package) integrated design technology. The aforementioned radiation-hardened SSD controller, multiple dynamic random access memory (DRAM) chips, multiple NAND flash memory chips, SPI flash memory chips, power supply chips, resistors, and capacitors are integrated into a single package using a 3D structure. The 3D structure places the radiation-hardened SSD controller, multiple DRAM chips, SPI flash memory chips, and power supply chips on a single functional unit (referred to as the SSD layer). The NAND flash memory chips are placed on one or more functional units (referred to as NANDn layers (n≥1)) depending on storage capacity requirements. The resistors and capacitors are distributed throughout each functional unit layer. Please refer to [link to relevant documentation]. Figure 3 In one embodiment, the SSD layer primarily includes one SSD controller, one SPI FLASH chip, one power chip, and one DDR2 chip on the front side, and two DDR2 chips on the back side; the NAND 1 layer primarily includes two NAND FLASH chips on the front side and two NAND FLASH chips on the back side; the NAND 2 layer primarily includes two NAND FLASH chips on the front side, and signal lead-out pads on the back side. The stacking order between the SSD layer and the multi-layer NAND layers can be combined according to actual needs; the SSD layer can be placed on the top or bottom layer, and similarly, the NAND layers can be placed arbitrarily. Please refer to [link to relevant documentation]. Figure 4 In this embodiment, the SSD layer is on the top layer, the NAND1 layer is in the middle layer, and the NAND2 layer is on the bottom layer.

[0042] Please see Figure 5 Due to the adoption of a 3D integrated structure, there are a large number of high-speed parallel data signals between the SSD layer and the NAND layer, with signal rates reaching hundreds of Mbps or even higher. The SSD layer also has high-speed serial interfaces with the host, such as SATA and PCIe, with signal rates reaching Gbps or even higher. The transmission of a large number of high-speed serial and parallel signals within this 3D layered structure necessitates ensuring signal integrity to guarantee correct signal transmission. For high-speed serial signals, due to the large number of signals, a one-to-one ground design is used, meaning that every n signals (typically 1 ≤ n ≤ 10) are accompanied by one ground signal. For high-speed parallel signals, each parallel signal is accompanied by a ground signal on both its left and right sides.

[0043] In another embodiment, the satellite solid-state storage SiP module system design, based on user application requirements and the principle of component availability, selects one LSoCAM2R402RH radiation-hardened SSD controller, one JFM25FL032RH radiation-hardened SPI FLASH, one RSW3301RH radiation-hardened power chip, three IS43DR16128C DDR2 chips, and six MT29F1T08CUCCBH8 NAND FLASH chips. The radiation-hardened SSD controller interconnects with the SPI FLASH memory via the SPI bus; it interconnects with three DDR2 chips via a dedicated DDR2 data bus, a dedicated DDR2 address bus, and a dedicated DDR2 control line, of which two DDR2 chips are used for data storage and one DDR2 chip is used for ECC verification; it interconnects with the NAND FLASH memory via the NIS bus; the power supply chip provides a reference voltage of 0.9×(1±5%)V (VREF_0.9V) for the SSD controller and the NAND FLASH memory, and a reference voltage of 0.9×(1±5%)V (VREF_0.9V) and a termination voltage of 0.9×(1±5%)V (VTT_0.9V) for the DDR2 chips; the RC network provides pull-up / pull-down configurations for signals within the module and provides filtering for the chip power supply. The satellite solid-state storage SiP module of this invention has external interfaces including a power supply interface (3.3×(1±5%)V, 2.5×(1±5%)V, 1.8×(1±5%)V, 1.2×(1±5%)V), a clock interface (CLK), a reset interface (RESET), a high-speed bus interface (PCIE, SATA), and a low-speed interface (UART, CAN).

[0044] The space-based solid-state storage (SiP) module is primarily used for onboard data storage and playback. Taking data storage as an example, when the SSD controller receives a write command and the corresponding data, it caches the data in two DDR2 memory chips and allocates an address for a NAND flash memory region. When the data reaches a certain quantity, the SSD controller writes the data into the corresponding NAND flash memory based on the address of the NAND flash memory region. The playback process is similar. When the SSD controller receives a playback command, it processes the command internally, retrieves the address stored in the NAND flash memory as needed, reads the corresponding data into the two DDR2 memory chips, and finally returns the data to the host via interfaces such as SATA, SAS, and PCIe.

[0045] The design of the space-based solid-state storage (SiP) module's process structure, based on the functional division within the SiP module, divides the module into four layers: one SSD controller, one SPI FLASH memory chip, one power chip, and three DDR2 chips. The SSD layer comprises these components, with the controller, SPI FLASH memory, power chip, and DDR2 chips placed on the front side of the SSD layer carrier, and the two DDR2 chips placed on the back side. Four NAND FLASH memory chips are divided into a NAND2 layer, with two chips placed on the front side and two on the back side. Two NAND FLASH memory chips are divided into a NAND1 layer, with both on the front side and the back side of the NAND1 layer containing external signal pads. Considering the heat dissipation requirements of the space-based SiP module, this embodiment places the relatively power-intensive SSD layer on the top layer, the NAND2 layer in the middle layer, and the NAND1 layer on the bottom layer.

[0046] The space-based solid-state storage (SSD) SiP module features a high-speed serial-parallel signal design. A large number of high-speed parallel data signals exist between the SSD and NAND layers, with signal rates reaching 400Mbps. The SSD layer also has a high-speed serial interface with the host, such as SATA or PCIe, with signal rates reaching 6Gbps. In the high-speed serial-parallel signal design, grounding is implemented for each signal. For high-speed serial signals, an average of one ground signal accompanies every eight signals, arranged as GND, signal 1, signal 2, ..., signal 8, GND. For high-speed parallel signals, each parallel signal is accompanied by a ground signal on both sides, arranged as GND, signal P, signal N (signals P and N can be interchanged), GND.

[0047] Another embodiment provides a method for reading and writing a satellite solid-state storage SiP module based on a radiation-hardened SSD controller:

[0048] The host sends a write command, and the radiation-resistant SSD controller receives the command and related data from the host. The radiation-resistant SSD controller caches the data in multiple dynamic random access memories and allocates an address for a NAND flash memory for the data. When the data reaches a set threshold, the radiation-resistant SSD controller writes the data into the corresponding NAND flash memory according to the address of the NAND flash memory.

[0049] The host sends a read command, the radiation-hardened SSD controller receives the command from the host, processes it internally, obtains the address stored in the NAND FLASH memory as needed, reads the corresponding data into the dynamic random access memory, and finally returns it to the host.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the technical solution of the present invention in any way. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can be modified and replaced in several simple ways, and these modifications and replacements are all within the scope of protection covered by the claims.

Claims

1. A satellite solid-state storage SiP module based on a radiation-hardened SSD controller, characterized in that: It includes a storage control unit, a data cache unit, a data storage unit, a program storage unit, a power supply reference unit, and a resistor-capacitor network; The storage control unit includes a radiation-resistant SSD controller, which receives commands and related data from the host, performs calculations and processing, and outputs the required data or status. The data caching unit consists of multiple dynamic random access memory chips, which cache data to match the data transmission rate between the storage control unit and the data storage unit. The data storage unit is composed of multiple NAND FLASH memory chips; The program storage unit is composed of a non-volatile SPI FLASH memory, used to store the SSD controller read / write program and the NAND FLASH lifetime and reliability management scheduling algorithm; The power supply reference unit is composed of a power supply chip and is used to provide a reference power supply to the dynamic random access memory of the data cache unit and the NAND FLASH memory of the data storage unit. The aforementioned RC network, composed of connected resistors and capacitors, is used to ensure the signal and power integrity of the entire SiP module. The radiation-resistant SSD controller, multiple dynamic random access memory chips, multiple NAND flash memory chips, SPI flash memory chips, power supply chip, resistors and capacitors are integrated into a single package using a 3D three-dimensional structure. The 3D stereo structure is designed for serial signal interfaces such that every n signals are accompanied by one ground signal, where 1 ≤ n ≤ 10; the 3D stereo structure is designed for parallel signal interfaces such that every parallel signal is accompanied by one ground signal on both the left and right sides. If a die in a NAND flash memory fails, the functionality of the space-based solid-state storage SiP module can be maintained by disabling the die select and updating the back-end organization of the radiation-hardened SSD controller.

2. The satellite solid-state storage SiP module based on a radiation-hardened SSD controller according to claim 1, characterized in that: The radiation-resistant SSD controller communicates directly with the host. The host sends write commands through the interface, and the radiation-resistant SSD controller receives the data sent by the host. The data is first cached in the dynamic random access memory. When the data cache reaches a set threshold amount, the radiation-resistant SSD controller sends a request to write the cached data to the NAND FLASH memory. When the host sends a read command, the radiation-hardened SSD controller obtains the address stored in the NAND FLASH memory according to the host's needs, reads the corresponding data into the dynamic random access memory, and finally returns it to the host through the interface.

3. The satellite solid-state storage SiP module based on a radiation-hardened SSD controller according to claim 1, characterized in that: The 3D structure places the radiation-resistant SSD controller, multiple dynamic random access memory chips, SPI FLASH memory, and power supply chip on one functional unit, and places the NAND FLASH memory on one or more functional units according to storage capacity requirements; the resistors and capacitors are distributed in each functional unit.

4. The satellite solid-state storage SiP module based on a radiation-hardened SSD controller according to claim 3, characterized in that; The multiple dynamic random access memory chips are distributed on the front and back of the functional unit, the NAND flash memory is distributed on the front and back of the functional unit, and signal lead-out pads are set on the outer surface of the outermost functional unit.

5. The satellite solid-state storage SiP module based on a radiation-hardened SSD controller according to claim 1, characterized in that: If a NAND flash memory is damaged, the channel containing that device is disabled, and a backup channel is enabled.

6. The satellite solid-state storage SiP module based on a radiation-hardened SSD controller according to claim 1, characterized in that: The radiation-resistant SSD controller is model LSoCAM2R402RH, the SPI FLASH memory is model JFM25FL032RH, the power supply chip is model RSW3301RH, the dynamic random access memory is model IS43DR16128C, and the NAND FLASH memory is model MT29F1T08CUCCBH8.

7. A method for reading and writing a satellite solid-state storage SiP module based on a radiation-hardened SSD controller as described in any one of claims 1 to 6, characterized in that: The host sends a write command, and the radiation-resistant SSD controller receives the command and related data from the host. The radiation-resistant SSD controller caches the data in multiple dynamic random access memories and allocates an address for a NAND flash memory for the data. When the data reaches a set threshold, the radiation-resistant SSD controller writes the data into the corresponding NAND flash memory according to the address of the NAND flash memory. The host sends a read command, the radiation-hardened SSD controller receives the command from the host, processes it internally, obtains the address stored in the NAND FLASH memory as needed, reads the corresponding data into the dynamic random access memory, and finally returns it to the host.

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